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Unit-5Microcomputer

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What is Microcomputer?

A microcomputer is a general purpose system; i.e.; the system is organized in such a way that it can perform a large

variety of computation.

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How to achieve Objective

• Each computation is represented by a sequence of instructions (a program )that is stored in a read write memory and is executed by microcomputer.

• The execution of instructions produces transformations on the data.

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Basic components of a microcomputer

Processor

Memory Subsystem I/O Subsystem

I/O devices

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A microcomputer consist of three subsystems:

• A Processor• A memory subsystem• An input/output (I/O) subsystem

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Processor

• It is the computing engine of the microcomputer; it executes the sequence of instructions i.e.. the program. it is also known as Central Processing Unit.

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Memory Subsystem• It stores the program as well as the data

used by the program.

• The memory is divided into locations, such as bytes and words; these locations are identified by their address.

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Memory operations

• Read: the processor provides the address and receives the data read from the location addressed.

• Write: the processor provides both address and the data to be stored at the corresponding location.

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I/O subsystem

• It contains the interface to devices that allow transferring data input to/ from the computer.

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Specification of memory subsystem

Addr(24) data(32)

Length Rdy

Read

Write

Enable

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Memory subsystem signals specification

• Enable: enable signal has to be active for the system to be active

• Read/Write: the subsystem responds to an event when one of these control signals are active.

• Length: it tells the size of an operand. length=0 if size is in bytes

1 if size is in words

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Memory subsystem signals specification

• Addr: the address of the memory location being accessed.

• Data: data is transferred through signal data.• Rdy: it tells the memory operation

completion. Rdy=0 if operation is in progress

1 if operation completes

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How the operation would be performed

• Read Write Enable Operation

0 0 0 No operation

0 1 1 Write Access

1 0 1 Read Access

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Entity declaration of Memory subsystem

1. LIBRARY ieee;2. USE ieee.std_logic_1164.all;3. USE WORK.comp_pkg.ALL;4. ENTITY Memory IS5. PORT (Addr : IN MAddrT ; -- memory address bus6. Length : IN STD_LOGIC; -- byte/word operand7. Rd, Wr : IN STD_LOGIC; -- access control signals8. Enable : IN STD_LOGIC; -- enable signal9. Rdy : OUT STD_LOGIC; -- access completion signal10.Data : INOUT WordT ); -- memory data bus11.END Memory;

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Specification of I/O subsystem

Addr(11) data(32)

Length Rdy

Read

Write

Enable

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Entity declaration of I/O subsystem

1. LIBRARY ieee;2. USE ieee.std_logic_1164.all;3. USE WORK.comp_pkg.ALL;4. ENTITY IO IS5. PORT (Addr : IN IOAddrT ; -- I/O address bus6. Length : IN STD_LOGIC; -- byte/word control7. Rd, Wr : IN STD_LOGIC; -- I/O access control8. Enable : IN STD_LOGIC; -- I/O enable control9. Rdy : OUT STD_LOGIC; -- I/O completion signal10.Data : INOUT WordT ); -- I/O data bus11.END IO;

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Arithmetic Logic Unit(ALU)

• Definition:The arithmetic logic unit (ALU) is a digital

circuit that calculates an arithmetic operation (like an addition, subtraction, etc.) and logic operations (like an Exclusive Or) between two numbers. The ALU is a fundamental building block of the central processing unit of a computer.

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Entity Declaration of ALU1. library IEEE;2. use IEEE.STD_LOGIC_1164.all; 3. use work.pack.all;4. entity alu is5. port(6. a : in STD_LOGIC_VECTOR( 15 downto 0);7. b : in STD_LOGIC_VECTOR( 15 downto 0);8. sel : in opcode;9. c : out STD_LOGIC_VECTOR( 15 downto 0)10. );11.end alu;

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Architecture of ALUarchitecture alu of alu isbegin

aluproc: process (a, b, sel)begin

case sel iswhen alupass =>

c <= a after 1 ns;when andOp =>

c <= (a and b) after 1 ns;

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Architecture..

when orOp =>c <= a or b after 1 ns;

when xorOp =>c <= a xor b after 1 ns;

when notOp =>c <= not a after 1 ns;

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Architecture..

when plus =>c <= a + b after 1 ns;

when alusub =>c <= a - b after 1 ns;

when inc =>c <= a + "0000000000000001" after 1 ns;

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Architecture..when dec =>c <= a - "0000000000000001" after 1 ns;when zero =>c <= "0000000000000000" after 1 ns;when others =>c <= "0000000000000000" after 1 ns;

end case; end process;

end alu;

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Package( work.pack.all)Package used in ALUlibrary IEEE;use IEEE.STD_LOGIC_1164.all; package pack is

type opcode is (alupass ,andop ,orop ,xorop ,notop ,plus ,alusub ,inc ,dec ,zero);

function "+"(opd1,opd2:std_logic_vector( 15 downto 0))return std_logic_vector;

function "-"(opd1,opd2:std_logic_vector(15 downto 0))return std_logic_vector;

end package;

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Package Body(work.pack.all)package body pack is

function "+"(opd1,opd2:std_logic_vector( 15 downto 0))return std_logic_vector is

variable sum:std_logic_vector(15 downto 0);variable carry:std_logic:='0';beginfor i in 15 downto 0 loopsum(i):= opd1(i) xor opd2(i)xor carry;carry:= (opd1(i) and opd2(i))or(opd2(i) and carry)or (opd1(i) and carry);end loop; return sum;

end function;

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Package Body(work.pack.all)..function "-"(opd1,opd2:std_logic_vector( 15 downto 0))return

std_logic_vector is

variable diff:std_logic_vector( 15 downto 0);variable borrow:std_logic:='0';beginfor i in 15 downto 0 loop

diff(i):= opd1(i) xor opd2(i)xor borrow;borrow:= ( (not opd1(i)) and borrow)or((not opd1(i))and opd2(i) )or (opd2(i) and borrow);end loop; \ return diff;

end function;end pack;

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Simulation