Enabling Technologies for Reconfigurable Computing Reiner Hartenstein University of Kaiserslautern November 21, 2001, Tampere, Finland Enabling Technologies

Enabling Technologies for

Reconfigurable Computing

Reiner Hartenstein

University ofKaiserslautern

November 21, 2001, Tampere, Finland

Enabling Technologies for Reconfigurable Computing

part 1:Reconfigurable Computing (RC)

Wednesday, November 21, 8.30 – 10.00 hrs.

© 2001, [email protected] http://www.fpl.uni-kl.de2

University of Kaiserslautern

Xputer Lab

Schedule

time slot

08.30 – 10.00

Reconfigurable Computing (RC)

10.00 – 10.30

coffee break

10.30 – 12.00

Compilation Techniques for RC

12.00 – 14.00

lunch break

14.00 – 15.30

Resources for Stream-based RC

15.30 – 16.00

coffee break

16.00 – 17.30

FPGAs: recent developments



Xputer LabReconfigurable: why?

•Exploding design cost and shrinking product life cycles of ASICs create a demand on RA usage for product longevity.

•Performance is only one part of the story. The time has come fully exploit their flexibility to support turn-around times of minutes instead of months for real time in-system debugging, profiling, verification, tuning, field-maintenance, and field-upgrades.

•A new “soft machine” paradigm and language framework is available for novel compilation techniques to cope with the new market structures transferring synthesis from vendor to customer.



Xputer LabSOC Alternatives… not including

C/C++ CAD Tools [Gordon Bell]• The blank sheet of paper: FPGA

• Auto design of a basic system: Tensilica

• Standardized, committee designed components*, cells, and custom IP

• Standard components including more application specific processors *, IP add-ons and custom

• One chip does it all: SMOP ***) Processors, Memory, Communication & Memory Links, **) SMOP ??



Xputer LabSoC Alternatives [Gordon Bell]

product strategy vendor

FPGA “sea of uncommitted gate arrays”

Xylinx, Altera

compile a system

unique processor for every application

Tensilica

systolic array many pipelined or parallel processors + custom

DSP, VLIW special purpose processor cores + custom

TI

processor + RAM + ASICS

general purpose cores, specialized by I/O, etc.

IBM, Intel,

universal micro multiprocessor array, programmable I/O

Cradle



Xputer LabA Decade of Research in

Reconfigurable Computing

• Due to the achievements of numerous Research Projects throughout the 90ies the Breakthrough in Commercialization has started and already a quite comprehensive Methodology is available.

• Dear Colleague, the RC Scene welcomes your contributions to improve it and to push for Inclusion in contemporary CS&E Curricula.

• It is one of the Goals of this Talk to stimulate you by Highlights and introducing some Key Issues.



Xputer Labno more a strange niche area

• was “Hardware” design for a strange plattform– CAD, but no Compilation

• Emerging awareness: – New mind set– New curricular embedding

• coming Dichotomie of CS – SW <-> CW– HW <-> FW– computing in time <-> computing in space



Xputer Lab flexibility / universality trade-off

trade-offflexibility efficiency

applica

tion-

speci

fic

dom

ain

-sp

eci

fic

genera

lpurp

ose

FPGA

KressArray

Xplorerhard-wired



Xputer LabRAs are heading for Mainstream

ASPP, application-specific programmable product is: • Application-specific standard product and:• embedded programmable logic

Soap Chip: System on a programmable Chip

Logic

Analog

DRAM/Flash/SRAM

Prog

ram

mab

le L

ogic

Microprocessor

CSoC, configurable SoC is: • an industry standard µProcessor, • embedded reconfigurable array,• memory, dedicated systen bus ...

Logic

Flash / RAMmemory banks

ReconfigurableAccelerator

Array

ARM,

MIPS,

or...

... become indispensable for SoC products ?



Xputer LabReconfigurable Logic going Mainstream

• Please, Lobby for New Curricula.

• Comprehensive Methodology

• One of the goals of this talk: to motivate You by Key Issues and Visionary Highlights.

• Fine grain: FPGAs killing the ASIC market

• Coarse grain: several startups

• Substantially improved design flow and libraries

• Fastest growing segment of semiconductor market



Xputer LabDesigner-oriented Innovation

stalled ?

• EDA industry: about 7 bio $• leverages > 200 bio $ semconductor industry• FPGAs (7 bio $) fastest growing segment• EDA industry constantly redefining itself• „except logic synthesis nor really significant

innovation in the past decade“• CAD developers can‘t deliver their idear

effectively• CAD developers personally don‘t appreciate the

real problems facing designers



Xputer LabEDA the main bottleneck



Xputer LabBiggest Mistake of EDAguess it !



Xputer Lab>> History

• History

• Paradidgm Shift

• Coarse Grain: why ?

• Coarse Grain Architectures

• Reconfiguration Architecturehttp://www.uni-kl.de



Xputer Lab Logic Gate Price Trend

Source:Altera

Pri

ce (

Norm

aliz

ed t

o Q

1/1

993)

Q1'93

Q1'94

Q1'95

Q1'96

Q1'97

Q1'98

Q1'99

Q1'00

Price per Logic Element

40% lower per Year

0

0.2

0.4

0.6

0.8

1

1.2

0.261

0.086 0.042 0.029



Xputer Lab

?

What’s coming next ?

The History of Paradigm Shifts

“Mainstream Silicon Applicationis switching every 10 Years”

TTL µproc.,memory

“The Programmable System-on-a-Chipis the next wave“

custom

standard

1957

1967

1977

1987

1997

2007

Makimoto’s Wave

ASICs,accel’s

LSI,MSI

1st D

esig

n C

risis

2n

d D

esig

n C

risis

?

reconfigurablePublished

in 1989



Xputer LabMakimoto’s 3rd Wave

•

Fine Grain Subsystems (FPGAs):

–

1st half of 3rd wave

–

universal (but less efficient)

•

Coarse Grain Subsystems:

–

2nd half of 3rd wave

–

domain-specific

–

much more flexible than 2nd half of 2rd wave



Xputer LabHow’s next Wave ?

2007FPGAs

custom

standard

1957

1967

1977

1987

1997

Tredennick’sParadigm Shifts

procedural programming

algorithm: variable

resources: fixed

hardwired

algorithm: fixed

resources: fixed

2007

?

structural programming

algorithm: variable

resources: variable

Coarse grain

RAs

no further wave !

Hartenstein’s Curve

?4th wave ?



Xputer LabThe Impact of

Makimoto’s Paradigm Shifts

TTL µproc.,memory

custom

standard

ASICs,accel’s

LSI,MSI

reconfigurable

1957

1967

1977

1987

1997

2007

Proceduralpersonalization via RAM-based

Machine Paradigm

Personalization(CAD) beforefabrication

structuralpersonalization:

RAM-basedbefore run time

Dr. Makimoto: FPL 2000 keynote

Software Industry’sSecret of Success

Repeat Success Story bynew Machine Paradigm !



Xputer Lab>> Paradigm Shift

• History• Paradidgm Shift






Xputer Lab Sequential vs. structural RAM

re-

download

conf.accelerator(s)

RAM

Logic Synthesis

Route and Place

FPGA

“von Neumann”

downloading

RAM

downloading

data path instructionsequencer

I / O

(procedural)Software

sequentialRAM

structuralRAM



Xputer Lab Changing Models of Computing

“von Neumann” contemporary reconfigurablecomputing

downloading

RAM

downloading

data path instructionsequencer

I / O

host

hardwired

downloading

accelerator(s)

CAD

RAM

host

re-

downloading

conf.accelerator(s)

RAM RAM

(procedural)Software

SoftwareConfigware

(structural)

FlexwareHardware

occupies most silicon

the tail wagging the dog



Xputer Lab The Microprocessor is a Methuselah

• 1th 4004• 2nd 8008• 3rd 8086• 4th 80286• 5th 80386• 6th 80486• 7th P5 (Pentium)• 8th P6 (Pentium Pro / Pentium II)• 9th Pentium III

9 technology generations ...

... the steam engineof the silicon age



Xputer Lab… Decline of Wintel Business

Model

Billion Subscribers worldwide

1 Bio

cellular & PCS

0.5 Bio

20

Billion US-$ US Market [forrester]

15

10

20

1997 1998 1999 2000 2001 2002

Million Devices delivered in the U.S.

[IDC]

Consumer PC

Info

rmat

ion

Appl

ianc

es

1000 $

Consumer PCav. resale ($)

1500 $

[forrester]



Xputer LabBasics of Binding Time

run time

loading time

compile time

time of “Instruction Fetch”

microprocessorparallel computer

ReconfigurableComputing



Xputer Lab Binding Time vs. Computing Domain

time domain(procedural)

Binding time: (Set-up ofCommunication Channels)

at run time microprocessorparallel computer

time & space(hybrid)

systolicarrays

later fabrication step ASICs

space domain(structural)

before fabrication full customICs

at loading time

at compile time

ReconfigurableComputing

array processor

programming domain:

The KressArrayis a generalization

of the systolic array



Xputer LabDataquest Predicts

Programmability to be Predominant in SOC

• With programmability as a standard feature, ASPPs will be predominant system-on-a-chip products in five years

Dataquest Semiconductors ‘98 conference

EETimes 10/21/98

Jordan Selburn, principal analyst, ASICs and system-level integration,Dataquest Inc.’s Semiconductors Group

• Application-specific programmable products (ASPPs) will be the next best thing in semiconductor technology



Xputer Lab Applications

The 10th International Conference on Field-programmable Logic and Applications

The Roadmap to Reconfigurable Systems

*) keynotes and papers at FPL 2000

Villach, Austria, August 27 - 30, 2000

http://www.fpl.uni-kl.de/FPL/

• next generations’ wireless*• network processors*• many other areas*



Xputer LabApplications (2)

• Image Processing:– for smart car (collision avoidance, others ...),

– Smart traffic pilots, robotics, fast material inspection,

– smart stub finders, motion detection (MPEG-4, ...)

• Signal Processing, Speech Processing, Software Radio,

• Correlation, Encryption, Comm. Switching / Protocols,

• Innovative consumer electronics:– super smart cards, smart handies, wearable,

– portable, set-top, laptop, desktop, embedded, ...

• many others, ...



Xputer Lab Applications

•new cellular standard: up to 2 Mbit/sec: new CDMA standard: > 500 MIPS needed just for RF receiver part

•wide variety of end-user‘s devices: smart handies, palm pilots, laptops, games, camcorder-likes, ..the internet car, many new types of devices to come ...

•increasing wide variety of services available from network provider:download just what a particular customer is subscribed to

•expert group [Vissers]: > 20% of it will be accelerator code*



Xputer Lab

Sources: Proc ISSCC, ICSPAT, DAC, DSPWorld

microprocessor / DSP

No

rmal

ized

pro

cess

or

spee

d

battery performance

Algorithmic Complexity(Shannon’s Law)

memory

Tra

nsi

sto

rs/c

hip

1960 1970 1980 1990 2000 2010

100 000 000

10 000 000

1000 000

100 000

10 000

1000

100

10

1

2G

3G

4GWhy coarse

grain ?

1G

wireless

100

10

1

0.1

0.01

0.001

mA/ MIP

computational efficiency

StrongARMSH7752



Xputer LabShannon‘s Law

•In a number of application areas throughput requirements are growing faster than Moore's law

•Fundamental flaws in software processor solutions

•32 soft ARM cores fit onto contemporary FPGA

•Stream-based distributed processing is the way to go



Xputer LabIt’s a Paradigm Shift !

• Using FPGAs (fine grain reconfigurable) just mainly is classical Logic Synthesis on a “strange hardware” platform

• Coarse Grain Reconfigurable Arrays (Reconfigurable Computing), however, mean a really fundamental Paradigm Shift

• This is still ignored by CS and EE Curricula and almost all R&D scenes



Xputer Lab >> Coarse Grain: why ?

• History

• Paradidgm Shift• Coarse Grain: why ?





Xputer Lab It’s a General Paradigm Shift !

• Using FPGAs (fine grain reconfigurable): just Logic Synthesis on a strange platform

• Coarse Grain Reconfigurable Arrays (Reconfigurable Computing): a fundamental Paradigm Shift

• ignored by Curricula & most R&D scenes

• Replacing Concurrent Processes by much more efficient parallelism: Stream-based ComputingArrays

systolic array* [1980]

KressArray** [1995]

chip-on-a-day* [2000]____

*) hardwired

**) reconfigurable



Xputer Lab Fine-grained vs. coarse-grained

• Fine-grained reconfiguration versus coarse-grained reconfiguration.

• fine grain is general purpose

• slow and area-inefficient, but high parallelism• coarse grain is application domain-specific

• coarse grain is highly area-efficient

• extremely high performance



Xputer LabReconfigurability Overhead

S S

S Sresources needed for reconfigurability

partly for configuration code storage

L

L L

LL

L

L LL

area used by application

“hidden RAM”not shown



Xputer LabPrinciple of a Typical FPGA

FF

FF

FF

FF

FF FFFF FF

Connection-Point

Tap

CLBCLB

CLBCLB

CLBCLBFF of hidden RAM



Xputer LabRouting Overhead in FPGAs

FF

FF

FF

FF

FF FF

>1000 transistorsat each cross bar

FF part of thehidden RAM

most FPGAvendors’gate count:

1 flipflop ofconfigurationRAM = 4 gates

Routing Congestion [DeHon]:often 50% or less of CLBs used

FF FF

Ý 40 transistorsat eachswitchingpoint

>

Ý 15 transistorsat each tap>



Xputer Lab

Sources: Proc ISSCC, ICSPAT, DAC, DSPWorld

Why Coarse Grain instead of FPGA ?

physicallogical

supersystolic

FPGAlogical

1980 1990 2000 2010

FPGAphysical

100 000 000 000

10 000 000 000

1000 000 000

100 000 000

10 000 000

1000 000

100 000

10 000

1000

Tra

nsi

sto

rs /

chip

~ 10

~ 10 000

drastically smaller configuration memorya lot of more benefits

much faster loading

FPGArouted

memory

microprocessor

reduced reconfigurability overhead by up to ~ 1000



Xputer Lab>>> extremely high efficiency

1. avoiding address computation overhead

2. avoiding instruction fetch and interpretation

overhead

3. high parallelism, massively multiple deep pipelines

4. much less configuration memory

5. no routing areas to configure functions from CLBs



Xputer LabConfigurable Computing Systems

• combine programmable sequential processor with Flexware (structurally programmable „hard“ware):

• capitalize on the strength of both,flexware and software.

• early 60ies: Estrin (UCLA): enabling technology not available

• 90ies: significant increase of research activities (DARPA ...)

• FPGAs: not the enabling technology: hardware skills needed

• Verilog or VHDL based systems often result in poor

performance



Xputer Lab Platforms available

• Soft Data Path Arrays– KressArray– Xtreme (PACT)– ACM (Quicksilver Tech)– CHESS Array (Elixent)– others

• Compilation techniques feasibility studies:– Partitioning Co-Compiler– Design Space Explorer– others



Xputer LabAlso as an autonomous Machine

• New Machine Paradigm (Xputer)

• is the counterpart of the so-called von Neumann paradigm – CONS: confuses customers (paradigm switch: the brain hurts)– PROS: strong guidance of EDA tool development– more effective hardware/software APIs– compilation techniques similar to traditional compilation– better Application Development Tools accepting C or Java

• easy to teach: simple machine principles– scan patterns (data counter) similar to control flow (program

counter)– general model of hardware / software co-design– fascination for freak effect: opening up a new R&D discipline



Xputer Lab >> Coarse Grain Architectures

• History

• Paradidgm Shift

• Coarse Grain: why ?• Coarse Grain Architectures




Xputer Lab

Triscend System on Chip Sell Chips Embedded Systems

Company

Adaptive Silicon

Chameleon SystemsMalleable

Silicon Spice

Systolix

MorphICs

Architecture

Not disclosed

32 bit datapath arrayNot disclosed

Not disclosed

Bit Serial Systolic Array

Not disclosed

Business ModelSell Cores

Sell Chips

Sell Chips

Sell Solutions

Sell Cores

Sell Cores

Markets

Embedded DSP

Networking

Voice over IP

Networking

Signal Conditioning

Wireless Commun.

Network Processors: > 20 Players

Cisco: Xilinx’s largest Customer

Some Players in Silicon Valley and ….



Xputer LabCommercial rDPAs

XPU family (IP cores):PACT Corp., Munich

XPU128**) bought

**

**

flexible array: MorphICs

CALISTO: Silicon Spice

CS2000 family:Chameleon Systems

MECA family: Malleable

FIPSOC: SIDSA

ACM: Quicksilver Tech

CHESS array: Elixent

MorphoSys: Morpho Tech

*

*

*) here at SoC



Xputer LabPACT Corp

• Xtreme Processor Platform (XPP) family of IP cores, high-speed data-stream-capable, scalable, reconfigurable clusters of arrays of 32-bit DPUs with embedded memories, and high-speed I/O ports -

• Application development support software featuring a flow graph-style algorithm mapping language - to minimize training requirements.

• XPP's fabrics, featuring automatic DataFlow synchronization and flagged Event Network to dynamically configure the execution flow,

• Supports dynamic RTR: hierarchical configuration managers free the designer from chip-level details and ensure that configurations are independently loaded in exactly the intended order.

• Automatic event-based task swapping along with data streams: released resources automatically reconfigured immediately



Xputer Lab

Reconfigurable Interconnect Fabric

separate routing area

rDPA (Reconfigurable Datapath Array)

rDPU rDPU rDPU rDPU

rDPU rDPU rDPU rDPU

rDPU rDPU rDPU rDPU

rDPU rDPU rDPU rDPU

rDPU rDPU rDPU rDPU

rDPU rDPU rDPU rDPU

rDPU rDPU rDPU rDPU

rDPU rDPU rDPU rDPU

RIF layouted over rDPUs:rDPA wired by abutment



Xputer Lab Generically defined Fabrics: KressArray Family

f)g) i)

a)

e)routing

routing

d)b)

h)

only

andfunction

c) rDPU:

rDPU:

rDPU

+

Some Application Areas, like e. g. Wireless Communication,need extraordinarily powerful Communication Resources



Xputer LabUniversal RAs are not always

feasible

... often Functional Resources are not the Throughput Bottleneck

Some Application Areas, such as e. g. Wireless Communication, need extremely rich Communication ResourcesUse Domain-specific Platform Generators !

The General Purpose (coarse grain) Reconfigurable Array

may appear to be an Illusion ...



Xputer LabKressArray Family Example

16 24

32

4

8

2 rDPU external view: onlyNNport AbutmentArchitecture shown

taylored KressArrayrDPU example

http://kressarray.de



Xputer Lab

KressArray Family generic Fabrics: a few examples

Examples of 2nd Level Interconnect:layouted overrDPU cell - no separate routing areas !

+

rout-through and function

rout-throug

h only more NNports:

rich Rout Resources

Select Function

Repertory

select Nearest Neighbour (NN) Interconnect: an example

16 32 8 24

4

2 rDPU

Select mode, number, width of NNports




Xputer LabCMOS intercoonnect resources

Foundries offer up to 8 metal layers

and up to 3 poly layers

reconfigurable interconnect fabric layouted over the

rDU cell



Xputer Lab

Super Pipe Networks

pipeline properties array applications

shape resources

mapping scheduling

(data stream formation)

systolic array

regular data dependencies

only

linear only

uniform only

linear projection or algebraic synthesis

super-systolic rDPA

no restrictions simulated

annealing or P&R algorithm

(e.g. force-directed) scheduling algorithm

The key is mapping, rather than architecture

**) KressArray [1995]



Xputer Lab Communication Resource Requirements

... often Functional Resources are not the Throughput

BottleneckIn some Application Areas,such as e. g. Wireless Communication, Reconfigurable Computing Arraysneed extraordinarily rich and powerful Communication ResourcesThe Solution: Generators for Domain-specific RA Platforms



Xputer Lab

rDPU not used used for routing only operator and routing port location markerLegend: backbus connect

array size: 10 x 16 = 160 rDPUs


SNN filter KressArray Mapping Example

rout thru only

not usedbackbus connect



Xputer Lab

route-thru-only rDPU

3 vert. NNports, 32 bit


Xplorer Plot: SNN Filter Example

+[13]

2 hor. NNports, 32 bit

operator

result

operand

operand

route thru

backbus connect



Xputer LabSuper Pipe Networks

pipeline propertiesarray applications

shape resources

mappingscheduling

(data streamformation)

systolicarray

regular datadependencies

only

linearonly

uniformonly

linear projection oralgebraic synthesis

super-systolicRA

no restrictionssimulated

annealing orP&R algorithm

(e.g. force-directed)schedulingalgorithm

The key is mapping, rather than architecture

**) KressArray [ASP-DAC-1995]



Xputer LabKressArray: try out youself !

• You may experiment yourself

• You may use it over the internet

• Map an application onto a KressArray

• Start with a simple example

• Visit http://kressarray.de

• Click the link to Xplorer

• ... does not run on internet explorer ....

• ... since Bill Gates does not like Java

try Netscape 4.7x



Xputer Lab Michael Herz

DissertationMichael Herz: • ... on mapping parallel memory

architectures for stream-based arrays onto KessArrays

• ... also transformation of storage schemes to optimize memory bandwith

• (MoM scan pattern transformations)

Agilent, Sindelfingen



Xputer Lab Ulrich Nageldinger

DissertationUlrich Nageldinger: • ... on mapping applications onto KessArrays• ... simultaneous routing and placement by

simulated annealing• Supporting a huge family of KressArrays• fuzzy logic improvement proposal generator• profiling• design space exploration

infineon technologies, Munich



Xputer Lab Rainer Kress

DissertationRainer Kress: • ... on mapping applications onto his*

KessArray• DPSS datapath synthesis system• Including a data scheduler• (data stream scheduler)• Generalization of the Systolic Array• (KressArray is a super systolic array)• 32 bit design via Eurochip support

infineon technologies, Munich



Xputer Lab Jürgen Becker

DissertationJürgen Becker: • ... Automatically partitioning Co-compiler• (configware / software co-compilation)• Resource-parameter-driven retargettable• Profiler-driven optimization• Accepts HLL „ALE-X“ (extended C subset)• (subset: pointers not supported)

Professor at Univ. Karlsruhe



Xputer Lab Karin Schmidt

DissertationKarin Schmidt: • Compilation Techniques for Xputers• modified loop transformations• Modified parts of implementation used

for Jürgen Becker‘s Ph. D. thesis

DaimlerChrysler Research



Xputer LabCHESS Array w. embedded RAM

(Elixent)

RAM

RAM

RAM

RAM

RAM

RAM

RAM

RAM

RAM

RAM

RAM

RAM

RAM

RAM

RAM

RAM

RAM

RAM

RAM

RAM

RAM

RAM

RAM

RAM

RAM

RAM

RAM

RAM

RAM

RAM

RAM

RAM

User Registers Clock Control

Mem

ory

In

terf

ace

multi-granular e. g. 16 * 4 Bits = 64 Bits

ALUALU

ALU

ALU

ALUALU

16by

4 R

AM

Sequencer

Sta

te M

achin

e



Xputer LabChameleon Systems

•RISC processor and an array of 108 arithmetic processing units. Each of those 32-bit processing cores runs at 125 MHz.

•The CS2112 is the industry's first Reconfigurable Communications Processor

(RCP), a streaming data processor. •The vendor claims a performance of 20 billion 16-bit operations per second, and 2.4 billion 16-bit multiply-accumulates per second - and 1.6 GBytes / sec for ist programmable I/O (PIO) banks.

•It also has a PCI interface.

•Tool suite C~SIDE for developing, verifying and optimizing.



Xputer Lab Coarse Grain Architectures

style project first

publ.

source architecture granularity fabrics mapping intended target application

DP-FPGA 1994 [4] 2-D array 1 & 4 bit multi-granular Inhomog. routing channels switchbox routing regular datapaths KressArray 1995 [5,11] 2-D mesh family: sel. pathwidth multiple NN & bus segments (co-)compilation (adaptable) Colt 1996 [12] 2-D array 1 & 16 bit inhomogenous run time reconfiguration highly dynamic reconfig. Matrix 1996 [15] 2-D mesh 8 bit, multi-granular 8NN, length 4 & global lines multi-length general purpose RAW 1997 [17] 2-D mesh 8 bit, multi-granular 8NN switched connections switchbox rout experimental Garp 1997 [16] 2-D mesh 2 bit global & semi-global lines heuristic routing loop acceleration REMARC 1998 [18] 2-D mesh 16 bit NN & full length buses (info not available) multimedia MorphoSys 1999 [19] 2-D mesh 16 bit NN, length 2 & 3 global lines manual P&R (not disclosed) CHESS 1999 [20] hexagon 4 bit, multi-granular 8NN and buses JHDL compilation multimedia DReAM 2000 [21] 2-D array 8 &16 bit NN, segmented buses co-compilation next generation wireless CS2000 family 2000 [23] 2-D array 16 & 32 bit inhomogenous array (not disclosed) communication MECA family 2000 [24] 2-D array multi-granular (not disclosed) (not disclosed) tele- & datacommunication CALISTO 2000 [25] 2-D array 16 bit multi-granular (not disclosed) (not disclosed) tele- & datacommunication

mesh

FIPSOC 2000 [26] 2-D array 4 bit multi-granular (not disclosed) (not disclosed) tele- & datacommunication RaPID 1996 [27] 1-D array 16 bit segmented buses channel routing pipelining

linear PipeRench 1998 [29] 1-D array 128 bit (sophisticated) scheduling pipelining PADDI 1990 [30] crossbar 16 bit central crossbar routing DSP PADDI-2 1993 [32] crossbar 16 bit multiple crossbar routing DSP and others

Cross bar

Pleiades 1997 [33] mesh+crossbar multi-granular multiple segmented crossbar switchbox routing multimedia



Xputer LabPrimarily Mesh-based ….

market project bits granularity source

KressArray variable U. KaiserslauternGarp 2 UC BerkeleyCHESS 4 Hewlett PackardMatrixRAW

8 M.I.T.

Colt 1 & 16 Virginia TechDReAM 8 &16 TU DarmstadtREMARC Stanford

research

MorphoSys UC IrvineCALISTO Slicon SpiceMECA family

16

MalleableCS2000 family 16 & 32 Chameleon SystemsFIPSOC 16 & analog SIDSA

commercial

XPP XPU128 32 PACT Corp.



Xputer LabUC Berkeley (Jan Rabaey)

market project bits granularity source

PADDIPADDI-2researchPleiades

16 UC Berkeley



Xputer Lab Crossbar-based Architectures

1993: PADY-II (Jan Rabaey)

EXUCTL

EXUCTL

EXUCTL

EXUCTL

EXUCTL

EXUCTL

EXUCTL

EXUCTL

crossbar switchI/OI/O

1990: UC Berkeley (Jan Rabaey)

16 bit

1997: Pleiades (mesh & crossbar)

32 bit



Xputer LabPADDI-II Architecture

NetworkP47

P48

P46

P45

P1P2P3P4

P5P6P7P8

P9P10P11P12

P13P14P15P16

P17P18P19P20

P21P22P23P24

P25P26P27P28

P29P30P31P32

P33P34P35P36

P37P38P39P40

P41P42P43P44

P45P46P47P48

bre

ak-s

wit

ch

bre

ak-s

wit

ch

I/O I/O I/O I/O

I/O I/O I/O I/O

6 x 16b

16 x 6 switch matrix

Level-2

16 x 16b

Level-1 Network

4-PE Cluster



Xputer LabMorphoSys



Xputer Lab PipeRench Architecture (CMU 1998)

highly dynamic reconfiguration

alternating data/instruction stream

© 2001, [email protected] http://www.fpl.uni-kl.de


Xputer Lab

75

M.I.T.

MIPS-likeprocessor

core

crossbar

globallines

globallines

RAW (M.I.T. 1997)

Reconfigurable Architecture Workbench

MATRIX (1996)Multiple Alu archiTecture with Reconfigurable Interconnect eXperiment

0.5 CMOS8 bit 10 x 101.8 mm2

100 MHz

multi-

granular

ALU8 bit

256x8 bit

Mem

WE mode

Net

wor

k Po

rt A

Netw

ork Port B

Mem

Func PortALU

Fun

c P

ort

compare / reduce 2

C / R Network

compare / reduce 1

C / R NetworkLevel-1 Network

BFU opc operation0123456789

101112131415

×× +

× + + × const

inshnshdshcsh

++0+1

:=nand

norxor



Xputer Lab MATRIX Interconnect Fabrics

BFU

itsneighbours

BFUsCommunication Resources are often the bottleneck



Xputer LabMore Research Projects

.... and others

Garp (UC Berkeley)

RaPiD (U. Washington )

REMARC (Stanford)published between1996 - 2000

DReAM (U. Karlsruhe)

Asia / Pacific: alsosee embedded tutorials by Prof. Amano (ASP_DAC’99, FPL-2000)



Xputer LabRaPiD Architecture

ALU

RAM

MULT

ALU

RAM

ALU

RAM

Bus Connectors Input Multiplexers Output Drivers

DatapathRegisters



Xputer Lab REMARC



Xputer Lab Future Coarse Grain RA Development

• It is indispensable to operate within the Convergence Area of Compilers, Co-Compilers, Architecture and full-custom-style VLSI Design (array cells).

• It is a must, that Products come with a Development Platform which encourages users,especially also those with a limited Hardware Background.



Xputer Lab >> Reconfiguration Architecture

• History

• Paradidgm Shift


• Coarse Grain Architectures• Reconfiguration Architecture

http://www.uni-kl.de



Xputer Lab

statically re-configurable

Dimensions of Reconfigurability

Class ofprocessor product vendor

ASIP Tensilica Tensilica

MECA family Malleable

CALISTO SiliconSpiceNetworkProcessor

many others many others

configuration time

ASIPfabrication

time

run time NetworkProcessor

designtime

compile time

dynamicallyreconfigurable

*) Application-Specific Instruction set ProcessorsASIPs* vs. Network Processors

Extremes:



Xputer LabConfiguration Architectures

hostCompiler, Mapper, RTOS

etc.

Soft Data Path

RAM

RAMRAMRAM

multi-context:

Soft Data Path

RAMhostCompiler, Mapper, RTOS

etc.

straight forward:

hostCompiler, Mapper, RTOS

etc.

Config. Cache

RAM

RAM

RAM

RAM

Soft Data Path

RAM

Configuration caching*:

Configuration Loading Resources:• separate configuration fabrics (e.g. FPGA)• wormhole routing (KressArray, Colt, PipeRench)• RA part computes code for other RA part (self reconfiguration)

(dynamic vs. static)

dynamic

*) no cache as

usual !



Xputer Lab Colt Architecture (P. Athanas 1996)

Multiplier

DP

DP

DP

SmartCrossbar

IFUIFUIFUIFU

IFUIFUIFUIFU

IFUIFUIFUIFU

IFUIFUIFUIFU

DP

DP

DPI/O Pins

I/O Pins

I/O Pins

I/O Pins

I/O Pins

I/O Pins

Studying highly dynamic reconfiguration

wormhole routing



Xputer Lab

Schedule

time slot

08.30 – 10.00

Reconfigurable Computing (RC)

10.00 – 10.30

coffee break

10.30 – 12.00

Compilation Techniques for RC

12.00 – 14.00

lunch break

14.00 – 15.30

Resources for Stream-based RC

15.30 – 16.00

coffee break

16.00 – 17.30

FPGAs: recent developments



Xputer Lab

- END -

Documents

Enabling Technologies for Reconfigurable Computing Reiner Hartenstein University of Kaiserslautern November 21, 2001, Tampere, Finland Enabling Technologies