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Embedded System Lab - 1Digital System Design Using VHDL
Introduction
HDL (Hardware Description Language) based design has established itself as
the modern approach to design of digital systems, with VHDL (VHSIC Hardware
Description Language) and Verilog HDL being the two dominant HDLs.Numerous universities thus introduce their students to VHDL (or Verilog). The
problem is that VHDL is complex due to its generality. Introducing students to
the language first, and then showing them how to design digital systems with
the language, tends to confuse students. The language issues tend to distract
them from the understanding of digital components. And the synthesis subset
issues of the language add to the confusion.
We developed the following tutorial based on the philosophy that the beginning
student need not understand the details of VHDL -- instead, they should be
able to modify examples to build the desired basic circuits. Thus, they learn
the importance of HDL-based digital design, without having to learn the
complexities of HDLs.
Basic Logic Gates
Every VHDL design description consists of at least oneentity-architecture pair,
or one entity with multiple architectures. The entity section of the HDL design
is used to declare theI/O ports of the circuit, while the description code resides
within architecture portion. Standardized design libraries are typically used
and are included prior to the entity declaration. This is accomplished by
including the code
library ieee;
use ieee.std_logic_1164.all;
Example Design 1: Behavioral design of OR gate
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Figure 1 VHDL Module of OR Gate
-------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
--------------------------------------------------------------------------
entity OR_ent is
port( A: in std_logic;
B: in std_logic;
Y: out std_logic
);
end OR_ent;
-----------------------------------------------------
architecture OR_beh of OR_ent is
begin
Y
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Embedded System Lab - 1Digital System Design Using VHDL
Figure 2 VHDL Module of XOR Gate
-------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------
entity XOR_ent is
port( A: in std_logic;
B: in std_logic;
Y: out std_logic
);
end XOR_ent;
-------------------------------------------------------
architecture behv2 of XOR_ent is
begin
Y
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Embedded System Lab - 1Digital System Design Using VHDL
Figure 3 VHDL module for myDesign1
-------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------
entity myDesign1 is
port(A, B, C, D: in std_logic;
Y : out std_logic
);
end myDesign;
--------------------------------------------------------------------------
Architecture Behavioral of myDesign1 is
Signal w1, w2 : std_logic;
Begin
W1
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Embedded System Lab - 1Digital System Design Using VHDL
Y
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Embedded System Lab - 1Digital System Design Using VHDL
TheStructural level describes a system as a collection of gates and
components that are interconnected to perform a desired function. A structural
description could be compared to a schematic of interconnected logic gates. It
is a representation that is usually closer to the physical realization of a system.
Example Design 4: Structural Design of myDesign2
Figure 4 VHDL Module of myDesign2
-----------------------------------------------------------------------------
-- Combinational Logic Design
-- A simple example of VHDL Structure Modeling
-- we might define two components in two separate files,
-- in main file, we use port map statement to instantiate
-- the mapping relationship between each components
-- and the entire circuit.
------------------------------------------------------------------------------
--Component #1
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------------
entity OR_GATE is
port( X : in std_logic;
Y : in std_logic;F2 : out std_logic
);
end OR_GATE;
architecture behv of OR_GATE is
begin
Prepared By: Bikash PoudelHCOE
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Embedded System Lab - 1Digital System Design Using VHDL
F2
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B : in std_logic;
F1 : out std_logic
);
end component;
component OR_GATE is -- as entity of OR_GATE
port( X : in std_logic;
Y : in std_logic;
F2 : out std_logic
);
end component;
signal wire : std_logic; -- signal just like wire
begin
-- use sign "=>" to clarify the pin mapping
Gate1: AND_GATE port map (
A=>input1,
B=>input2,
F1=>wire
);
Gate2: OR_GATE port map (
X=>wire,
Y=>input3,
F2=>output
);
end struct;
-------------------------------------------------------------------------------------------------
Lab Work III:
3.Design and Implement following Digital System using Structural
Modeling.
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Embedded System Lab - 1Digital System Design Using VHDL
You must prepare initial for the lab. The initial must contain:
e.Theory section: It must include Truth table and VHDL module
with connecting wires.
f.VHDL code.
After the completion lab, students must prepare lab report. Lab report
must contain Test Bench Code, Timing Diagram, Description of Timing
Diagram, and Conclusion.
Figure 5 VHDL Module of myDesign3
Lab Work IV:
Design and implement following system.
1.Derive two Boolean equation for Y1 (Good Flame) and Y2 (Sensor
Disagreement) from the truth table using K-map method.
2.Write VHDL code for the flame detection Logic System.
Real World Example Design: Flame Detection System
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Embedded System Lab - 1Digital System Design Using VHDL
Suppose we were given the task of designing a flame detection circuit for a toxic
waste incinerator. The intense heat of the fire is intended to neutralize the
toxicity of the waste introduced into the incinerator. Such combustion-based
techniques are commonly used to neutralize medical waste, which may be
infected with deadly viruses or bacteria.
So long as a flame is maintained in the incinerator, it is safe to inject waste into
it to be neutralized. If the flame were to be extinguished, however, it would be
unsafe to continue to inject waste into the combustion chamber, as it would
exit the exhaust un-neutralized, and pose a health threat to anyone in close
proximity to the exhaust. What we need in this system is a sure way of
detecting the presence of a flame, and permitting waste to be injected only if a
flame is "proven" by the flame detection system as Good Flame.
Several different flame-detection technologies exist: optical (detection of light),
thermal (detection of high temperature), and electrical conduction (detection of
ionized particles in the flame path), each one with its unique advantages and
disadvantages. Suppose that due to the high degree of hazard involved with
potentially passing un-neutralized waste out the exhaust of this incinerator, it is
decided that the flame detection system be made redundant (multiple sensors),
so that failure of a single sensor does not lead to an emission of toxins out the
exhaust. Each sensor comes equipped with a normally-open contact (open if no flame, closed if flame detected) which we will use to activate the inputs of a logic
system.
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Embedded System Lab - 1Digital System Design Using VHDL
Our task, now, is to design the circuitry of the logic system to open the
waste valve if and only if there is Good Flame proven by the sensors.
First, though, we must decide what the logical behavior of this controlsystem should be.
A strategy that would meet our needs would be a "two out of three" sensor
logic, whereby the waste valve is opened if at least two out of the three
sensors showGood Flame.
We are also extending the functionality of the system by adding a logic
circuitry to detect if any one of the sensors does not agree with the othertwo(Sensor Disagreement).
The first step in designing this “Good Flame” and "sensor disagreement"
detection circuit is to write a truth table describing its behavior. The
truth table for such a system would look like this:
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Embedded System Lab - 1Digital System Design Using VHDL
Prepared By: Bikash PoudelHCOE