Embedded Memory Generator v1.0 LogiCORE IP Product Guide...True Dual-Port RAM Single-Port ROM Dual-Port ROM • Supports synchronous and asynchronous reset • Supports sleep and auto-sleep

Embedded MemoryGenerator v1.0

LogiCORE IP Product GuideVivado Design Suite

PG326 (v1.0) July 14, 2020

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Table of ContentsChapter 1: Introduction.............................................................................................. 4

Features........................................................................................................................................4IP Facts..........................................................................................................................................5

Chapter 2: Overview......................................................................................................6Navigating Content by Design Process.................................................................................... 6Introduction to Versal ACAP.......................................................................................................6Core Overview..............................................................................................................................8Applications..................................................................................................................................8Feature Summary........................................................................................................................8Licensing and Ordering............................................................................................................ 10

Chapter 3: Product Specification......................................................................... 11Performance.............................................................................................................................. 11Port Descriptions.......................................................................................................................11

Chapter 4: Designing with the Core................................................................... 13General Design Guidelines.......................................................................................................13Power Saving............................................................................................................................. 30Auto Sleep Mode....................................................................................................................... 30Clocking...................................................................................................................................... 31Resets..........................................................................................................................................31

Chapter 5: Design Flow Steps.................................................................................32Customizing and Generating the Core...................................................................................32

Chapter 6: Detailed Example Design................................................................. 39

Chapter 7: Test Bench.................................................................................................40

Appendix A: Verification, Compliance, and Interoperability...............41

Appendix B: Upgrading............................................................................................. 42

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Appendix C: Debugging.............................................................................................43Finding Help on Xilinx.com...................................................................................................... 43Debug Tools............................................................................................................................... 44Simulation Debug......................................................................................................................44Hardware Debug....................................................................................................................... 45

Appendix D: Additional Resources and Legal Notices............................. 46Xilinx Resources.........................................................................................................................46References..................................................................................................................................46Revision History......................................................................................................................... 46Please Read: Important Legal Notices................................................................................... 47




Chapter 1

IntroductionThe Xilinx® LogiCORE™ IP Embedded Memory Generator (EMG) core is an advanced memoryconstructor that generates area and performance-optimized memories using embedded blockRAM, UltraRAM, and distributed RAM resources in Xilinx devices.

Features• Configurable memory initialization

• Individual write enable per byte

• Selectable operating modes per port: write first, read first, or no change

• Standard DOUT block RAM/UltraRAM cascading

• Configurable port aspect ratios for dual-port configurations and read-to-write aspect ratios

• Supports the built-in hamming error correction capability (ECC). Error injection pins allowinsertion of single and double-bit errors. Following are the supported ECC modes:

○ Encode only

○ Decode only

○ Both encode and decode

• Supports memory sizes up to a maximum of 150 Mb (limited only by memory resources on aselected part)

• Supports read latency up to 128.

• Following are the supported memory primitives:

○ block RAM

○ UltraRAM

○ Distributed RAM

• Following are the supported memory types:

○ Single-Port RAM

○ Simple Dual-Port RAM

Chapter 1: Introduction




○ True Dual-Port RAM

○ Single-Port ROM

○ Dual-Port ROM

• Supports synchronous and asynchronous reset

• Supports sleep and auto-sleep modes

IP FactsLogiCORE™ IP Facts Table

Core Specifics

Supported Device Family1 Versal™ ACAP

Supported User Interfaces Memory Interface

Provided with Core

Design Files System Verilog

Example Design N/A

Test Bench N/A

Constraints File N/A

Simulation Model N/A2

Supported S/W Driver N/A

Tested Design Flows2

Design Entry IP integrator

Simulation For supported simulators, see the Xilinx Design Tools: Release Notes Guide.

Synthesis Vivado Synthesis

Support

Provided by Xilinx at the Xilinx Support web page

Notes:1. For supported simulators, see theFor a complete list of supported devices, see the Vivado® IP catalog.2. For the supported versions of the tools, see the Xilinx Design Tools: Release Notes Guide.

Chapter 1: Introduction


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Chapter 2

Overview

Navigating Content by Design ProcessXilinx® documentation is organized around a set of standard design processes to help you findrelevant content for your current development task. This document covers the following designprocesses:

• Hardware, IP, and Platform Development: Creating the PL IP blocks for the hardwareplatform, creating PL kernels, subsystem functional simulation, and evaluating the Vivado®

timing, resource use, and power closure. Also involves developing the hardware platform forsystem integration. Topics in this document that apply to this design process include:

• Port Descriptions

• Clocking

• Resets

• Customizing and Generating the Core

• Chapter 6: Detailed Example Design

Introduction to Versal ACAPVersal™ adaptive compute acceleration platforms (ACAPs) combine Scalar Engines, AdaptableEngines, and Intelligent Engines with leading-edge memory and interfacing technologies todeliver powerful heterogeneous acceleration for any application. Most importantly, Versal ACAPhardware and software are targeted for programming and optimization by data scientists andsoftware and hardware developers. Versal ACAPs are enabled by a host of tools, software,libraries, IP, middleware, and frameworks to enable all industry-standard design flows.

Chapter 2: Overview




Built on the TSMC 7 nm FinFET process technology, the Versal portfolio is the first platform tocombine software programmability and domain-specific hardware acceleration with theadaptability necessary to meet today's rapid pace of innovation. The portfolio includes six seriesof devices uniquely architected to deliver scalability and AI inference capabilities for a host ofapplications across different markets—from cloud—to networking—to wireless communications—to edge computing and endpoints.

The Versal architecture combines different engine types with a wealth of connectivity andcommunication capability and a network on chip (NoC) to enable seamless memory-mappedaccess to the full height and width of the device. Intelligent Engines are SIMD VLIW AI Enginesfor adaptive inference and advanced signal processing compute, and DSP Engines for fixed point,floating point, and complex MAC operations. Adaptable Engines are a combination ofprogrammable logic blocks and memory, architected for high-compute density. Scalar Engines,including Arm® Cortex™-A72 and Cortex-R5F processors, allow for intensive compute tasks.

The Versal AI Core series delivers breakthrough AI inference acceleration with AI Engines thatdeliver over 100x greater compute performance than current server-class of CPUs. This series isdesigned for a breadth of applications, including cloud for dynamic workloads and network formassive bandwidth, all while delivering advanced safety and security features. AI and datascientists, as well as software and hardware developers, can all take advantage of the high-compute density to accelerate the performance of any application.

The Versal Prime series is the foundation and the mid-range of the Versal platform, serving thebroadest range of uses across multiple markets. These applications include 100G to 200Gnetworking equipment, network and storage acceleration in the Data Center, communicationstest equipment, broadcast, and aerospace & defense. The series integrates mainstream 58Gtransceivers and optimized I/O and DDR connectivity, achieving low-latency acceleration andperformance across diverse workloads.

The Versal Premium series provides breakthrough heterogeneous integration, very high-performance compute, connectivity, and security in an adaptable platform with a minimizedpower and area footprint. The series is designed to exceed the demands of high-bandwidth,compute-intensive applications in wired communications, data center, test & measurement, andother applications. Versal Premium series ACAPs include 112G PAM4 transceivers and integratedblocks for 600G Ethernet, 600G Interlaken, PCI Express® Gen5, and high-speed cryptography.

The Versal architecture documentation suite is available at: https://www.xilinx.com/versal.

Chapter 2: Overview


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Core OverviewThe Embedded Memory Generator core uses embedded block RAM/UltraRAM Memoryprimitives in Xilinx® devices to extend the functionality and capability of a single primitive tomemories of a variety of configurable widths and depths. Sophisticated algorithms within theVivado® Synthesis core produce optimized solutions to provide convenient access to memoriesfor a wide range of configurations.

This core has two fully independent ports that access a shared memory space. Both A and Bports have a write and a read interface. When not using all four interfaces, you can select asimplified memory configuration (for example, a single-port memory or simple dual-port memory)to reduce device resource usage.

ApplicationsThe Embedded Memory Generator core is used to create customized memories to suit anyapplication. Typical applications include:

• Single-port RAM: Including processor scratch RAM and look-up tables

• Simple dual-port RAM: Including content addressable memories and FIFOs

• True dual-port RAM: Including multiprocessor storage

• Single-port ROM: Including program code storage and initialization ROM

• Dual-port ROM: Including single ROM shared between two processors/systems

Feature SummaryThe Embedded Memory Generator core uses embedded block RAM/UltraRAM and DistributedRAM to generate five types of memories:

• Single-port RAM

• Simple dual-port RAM

• True dual-port RAM

• Single-port ROM

• Dual-port ROM

Chapter 2: Overview




For dual-port memories, each port operates independently. Operating mode, optional readlatency, and optional pins are selectable per port. For simple dual-port RAM, the operatingmodes are not selectable. See Collision Behavior for additional information.

Configurable Width and Depth

The Embedded Memory Generator core can generate memory structures up to 50 megabits.

Selectable Operating Mode per Port

The Embedded Memory Generator core supports the following block RAM primitive operatingmodes: Write first, read first, and no change. Each port can be assigned its own operating mode.

Selectable Port Aspect Ratios

The core supports the aspect ratios across the ports only when:

• The A port width might differ from the B port width by a factor of 1, 2, 4, 8, 16, or 32.

• The read width might differ from the write width by a factor of 1, 2, 4, 8, 16, or 32 for eachport. The maximum ratio between any two of the data widths (dina → doutb, dinb → douta) is32:1.

Optional Byte-Write Enable

The Embedded Memory Generator core provides byte-write support for memory widths whichare multiples of eight (no parity) or nine bits (with parity).

Optional Output Registers (Read Latency A/B)

The Embedded Memory Generator core provides up to 64 stages of pipeline registers to increasememory performance. The output registers for port A and port B can be chosen separately. Thecore supports the built-in block RAM/UltraRAM output registers as well as registersimplemented in the FPGA general interconnect.

Memory Initialization

The memory contents can be optionally initialized using a memory initialization (MEM) file or byusing the default data option. A MEM file can define the initial contents of each individualmemory location, while the default data option defines the initial content of all locations.

For more details, see Update MEM to Update Bit Files with MMI and ELF Data in Vivado DesignSuite User Guide: Embedded Processor Hardware Design (UG898).

Chapter 2: Overview


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Hamming Error Correction Capability

Simple dual-port RAM memories support the built-in FPGA Hamming Error Correction Capability(ECC) available block RAM/UltraRAM primitives for data widths greater than 64 bits. The built-inECC (ECC) memory automatically detects single-bit and double-bit errors, and is able to auto-correct the single-bit errors.

Licensing and OrderingThis Xilinx® LogiCORE™ IP module is provided at no additional cost with the Xilinx Vivado®

Design Suite under the terms of the Xilinx End User License.

Information about other Xilinx® LogiCORE™ IP modules is available at the Xilinx IntellectualProperty page. For information about pricing and availability of other Xilinx LogiCORE IP modulesand tools, contact your local Xilinx sales representative.

Chapter 2: Overview


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Chapter 3

Product SpecificationThis chapter includes details on performance and port descriptions.

PerformancePerformance and resource usage for a Embedded Memory Generator core varies depending onthe configuration and features selected during core customization.

Port DescriptionsThe following table provides a description of the Embedded Memory Generator core ports. Youcan select the widths of the data ports (dina, douta, dinb, and doutb) in the Vivado® IDE. Theaddress port (addrb) widths are determined by the memory depth with respect to each port. Thewrite enable ports (wea and web) are buses (of width one) when byte-writes are disabled. Whenbyte-writes are enabled, wea and web widths depend on the byte size and write data widthsselected in Vivado IDE.

Table 1: Core Port Pinout

Port Name I/O Port Descriptionclka Input Port A Clock Port A operations are synchronous to this clock. For synchronous

operation, this must be driven by the same signal as CLKB.

addra Input Port A Address Addresses the memory space for port A Read and Write operations.Available in all configurations.

dina Input Port A Data Input: Data input to be written into the memory through port A. Availablein all RAM configurations.

douta Output Port A Data Output Data output from Read operations through port A. Available in allconfigurations except Simple Dual-port RAM.

ena Input Port A Clock Enable Enables Read, Write, and reset operations through port A. Optionalin all configurations.

wea Input Port A Write Enable Enables Write operations through port A. Available in all RAMconfigurations.

rsta Input Port A Set/Reset Resets the Port A memory output latch or output register. Optionalin all configurations.

Chapter 3: Product Specification




Table 1: Core Port Pinout (cont'd)

Port Name I/O Port Descriptionregcea Input Port A Register Enable Enables the last output register of port A. Optional in all

configurations with port A output registers.

sbiterra Output Single-Bit Error Single-bit error in memory which has been auto corrected on theoutput bus.

dbiterra Output Double-Bit Error Flags the presence of a double-bit error in memory. Double-biterrors cannot be auto-corrected by the built-in ECC decode module.

injectsbiterra Input Inject Single-Bit Error

injectdbiterra Input Inject Double-Bit Error

clkb Input Port B Clock Port B operations are synchronous to this clock. Available in dual-port configurations. For synchronous operation, this must be drivenby the same signal as CLKA.

addrb Input Port B address Addresses the memory space for port B Read and Write operations.Available in dual-port configurations.

dinb Input Port B Data Input Data input to be written into the memory through port B. Availablein True Dual-port RAM configurations.

doutb Output Port B Data Output Data output from Read operations through Port B. Available in dual-port configurations.

enb Input Port B Clock Enable Enables Read, Write, and reset operations through Port B. Optionalin dual-port configurations.

web Input Port B Write Enable Enables Write operations through Port B. Available in Dual-port RAMconfigurations.

rstb Input Port B Set/Reset Resets the Port B memory output latch or output register. Optionalin all configurations.

regceb Input Port B Register Enable Enables the last output register of port B. Optional in dual-portconfigurations with port B output registers.

sbiterrb Output Single-Bit Error Flags the presence of a single-bit error in memory which has beenauto-corrected on the output bus.

dbiterrb Output Double-Bit Error Flags the presence of a double-bit error in memory. Double-biterrors cannot be auto-corrected by the built-in ECC decode module.

injectsbiterrb Input Inject Single-Bit Error

injectdbiterrb Input Inject Double-Bit Error

sleep Input Dynamic Power Saving If sleep pin is High, the Embedded Memory Generator core is inpower saving mode.

Chapter 3: Product Specification




Chapter 4

Designing with the CoreThis chapter describes the steps required to turn a Embedded Memory Generator core into afully functioning design integrated with the user application logic. It is important to note thatdepending on the configuration of the Embedded Memory Generator core, only a subset of theimplementation details provided are applicable. The guidelines in this chapter provide detailsabout creating the most successful implementation of the core.

General Design GuidelinesThe Vivado® Synthesis implements an optimal memory by arranging block RAM primitives basedon user selections, automating the process of primitive instantiation and concatenation. This isused to build custom memory modules from block RAM/UltraRAM primitives in the VivadoDesign Suite IP catalog, you can configure the core and rapidly generate a highly optimizedcustom memory solution.

Memory TypeThe Embedded Memory Generator core creates five memory types: single-port RAM, simpledual-port RAM, true dual-port RAM, single-port ROM, and dual-port ROM. The following figuresillustrate the signals available for each type. Optional pins are displayed in italics.

For each configuration, optimizations are made within the Vivado® Synthesis to minimize thetotal resources used. The single-port ROM allows read access to the memory space through asingle-port, as illustrated in the following figure.

Chapter 4: Designing with the Core




Figure 1: Single-port ROM

Single-Port ROM

ADDRAENA

RSTA

CLKA

DOUTA

REGCEA

SLEEP

INJECTDBITERRA

INJECTSBITERRA

SBITERRA

DBITERRA

X21864-110918

The dual-port ROM allows read access to the memory space through two ports, as shown in thefollowing figure.

Figure 2: Dual-port ROM

Dual-Port ROM

ADDRAENA

RSTA

CLKA

DOUTA

DOUTB

REGCEA

ADDRBENB

RSTB

CLKBREGCEB

SLEEP

INJECTDBITERRA

INJECTSBITERRA

SBITERRA

DBITERRA

INJECTSBITERRB

INJECTSBITERRB

SBITERRB

DBITERRB

X21871-110918

The single-port RAM allows read and write access to the memory through a single port, as shownin the following figure.





Figure 3: Single-port RAM

Single-Port RAM

ADDRADINA

ENAWEA

RSTA

CLKA

DOUTA

REGCEA

INJECTDBITERRAINJECTSBITERRA

SLEEP

SBITERRA

DBITERRA

X21865-110918

The simple dual-port RAM provides two ports, A and B, as illustrated in the following figure.Write access to the memory is allowed through port A, and read access is allowed through portB.

Figure 4: Simple Dual-port RAM

Simple Dual-Port RAM

CLKA

DOUTBADDRBENB

RSTB

CLKBREGCEB

ADDRADINA

ENA DBITERRA

INJECTDBITERRAINJECTSBITERRA

SBITERRAWEA

SLEEP

X21866-110918

The true dual-port RAM provides two ports, A and B, as illustrated in the following figure. Readand write accesses to the memory are allowed on either port.





Figure 5: True Dual-port RAM

True Dual-Port RAM

ADDRA

DINA

ENA

WEA

RSTA

CLKA

DOUTA

DOUTB

REGCEA

ADDRB

DINB

ENB

WEB

RSTB

CLKB

REGCEB

INJECTSBITERRAINJECTDBITERRA

SBITERRA

DBITERRA

INJECTSBITERRBINJECTDBITERRB

SBITERRB

DBITERRB

X21863-110918

Selectable Width and DepthThe Embedded Memory Generator core generates memories up to 50 megabits, and with depthsof two or more words. The memory is built by concatenating block RAM/UltraRAM/distributedRAM primitives.

Write operations to out-of-range addresses are guaranteed not to corrupt data in the memory,while read operations to out-of-range addresses can return invalid data. The set/reset functionshould not be asserted while accessing an out-of-range address as this also results in invalid dataon the output in the present or following clock cycles depending upon the output register stagesof the core.

Operating Mode (Only for Block RAM/UltraRAM)

The operating mode for each port determines the relationship between the write and readinterfaces for that port. Port A and port B can be configured independently with any one of threewrite modes: write first mode, read first mode, or no change mode. These operating modes aredescribed in the sections that follow.





The operating modes have an effect on the relationship between the A and B ports when the Aand B port addresses have a collision. For detailed information about collision behavior, see Collision Behavior. For more information about operating modes, see the block RAM/UltraRAMsection of the user guide specific to the device family.

• Write First Mode: In the write first mode, the input data is simultaneously written intomemory and driven on the data output, as shown in the following figure. This transparentmode offers the flexibility of using the data output bus during a write operation on the sameport.

Figure 6: Write First Mode Example

aa

WEA

DINA[15:0]

DOUTA[15:0]

CLKA

ADDRA bb

1111

ENA

cc dd

2222

MEM(aa) 1111 2222 MEM(dd)0000

DISABLED READWRITE

MEM(bb)=1111

WRITEMEM(cc)=

2222READ

X21868-110918

This operation is affected by the optional byte-write feature. It is also affected by the optionalread-to-write aspect ratio feature. For detailed information, see Write First ModeConsiderations.

• Read First Mode: In the read first mode, data previously stored at the write address appearson the data output, while the input data is being stored in memory. This behavior is illustratedin the following figure.

Figure 7: Read First Mode Example

aa

WEA

DINA[15:0]

DOUTA[15:0]

CLKA

ADDRA bb

1111

ENA

cc dd

2222

MEM(aa) old MEM(bb) old MEM(cc) MEM(dd)0000

DISABLED READWRITE

MEM(bb)=1111

WRITEMEM(cc)=

2222READ

X21869-110918

• No Change Mode: In the no change mode, the output latches remain unchanged during awrite operation. As shown in the following figure, the data output is still the previous Readdata and is unaffected by a write operation on the same port.





Figure 8: No Change Mode Example

aa

WEA

DINA[15:0]

DOUTA[15:0]

CLKA

ADDRA bb

1111

ENA

cc dd

2222

MEM(aa) MEM(dd)0000

DISABLED READWRITE

MEM(bb)=1111

WRITEMEM(cc)=

2222READ

X21870-110918

Data Width Aspect RatiosThe Embedded Memory Generator core supports data width aspect ratios. This allows the port Adata width to be different than the port B data width, as described in Port Aspect Ratios in thefollowing section. All four data buses (dina, douta, dinb, and doutb) can have differentwidths, as described in the following sections.

Note: The aspect ratio is supported only across ports (port A to port B or port B to port A).

The limitations of the data width aspect ratio feature (some of which are imposed by otheroptional features) are described in the following sections. The Vivado® IP integrator GUI ensuresonly valid aspect ratios are selected.

Port Aspect Ratios

The Embedded Memory Generatorcore supports port aspect ratios of 1:32, 1:16, 1:8, 1:4, 1:2,1:1, 2:1, 4:1, 8:1, 16:1, and 32:1. The port A data width can be up to 32 times larger than theport B data width, or vice versa. The smaller data words are arranged in little-endian format

Port Aspect Ratio Example

Consider a True Dual-port RAM of 32x2048, which is the A port width and depth. From theperspective of an 8-bit B port, the depth would be 8192. The addra bus is 11 bits, while theaddrb bus is 13 bits. The data is stored little-endian, as shown in the following figure.

Note: An is the data word at address n, with respect to the A port. Bn is the data word at address n withrespect to the B port. A0 is comprised of B3, B2, B1, and B0.





Figure 9: Port Aspect Ratio Example Memory Map

31 0

B3A0 =

...

7 0. .7 0. .7 0. .7 0. .

7 0. .7 0. .7 0. .7 0. .

B2 B1 B0

B7 B6 B5 B4A1 =

X21880-110918

Read-to-Write Aspect Ratios

When implementing RAMs, the Embedded Memory Generator core allows read and write aspectratios on either port. On each port A and port B, the Read to Write data width ratio of that portcan be 1:32, 1:16, 1:8, 1:4, 1:2, 1:1, 2:1, 4:1, 8:1, 16:1, or 32:1.

Because the read and write interfaces of each port can differ, it is possible for all four data buses(dina, dinb, douta, and doutb) of True Dual-port RAMs to have a different width. Themaximum ratio between any two data buses is 32:1. The widest data bus can be no larger than4096 bits.

If the read and write data widths on a port are different, the memory depth is different withrespect to read and write accesses. For example, if the read interface of port A is twice as wide asthe write interface of port B, then it is also half as deep. The ratio of the widths is always theinverse of the ratio of the depths. For the shallower interface, the least significant bits of theaddress bus are ignored. The data words are arranged in little-endian format.

Aspect Ratio Limitations

In general, no port data width can be wider than 4096 bits, and no two data widths can have aratio greater than 32:1. However, when using byte-writes, no two data widths can have a ratiogreater than 4:1.

Byte-WritesThe Embedded Memory Generator core provides byte-write support. Byte-writes are availableusing either 8-bit or 9-bit byte sizes. When using an 8-bit byte size, no parity bits are used andthe memory width is restricted to multiples of 8 bits. When using a 9-bit byte size, each byteincludes a parity bit, and the memory width is restricted to multiples of 9 bits.

When byte-writes are enabled, the we[a|b] (wea or web) bus is N bits wide, where N is thenumber of bytes in din[a|b]. The most significant bit in the Write enable bus corresponds tothe most significant byte in the input word. Bytes are stored in memory only if the correspondingbit in the Write enable bus is asserted during the write operation.





When 8-bit bytes are selected, the din and dout data buses are constructed from 8-bit bytes,with no parity. When 9-bit bytes are selected, the din and dout data buses are constructedfrom 9-bit bytes, with the 9th bit of each byte in the data word serving as a parity bit for thatbyte.

The byte-write feature might be used in conjunction with the data width aspect ratios, which canlimit the choice of data widths as described in Data Width Aspect Ratios. However, it might notbe used with the no change operating mode. This is because if a memory configuration usesmultiple primitives in width, and only one primitive is being written to (using partial byte writes),then the no change mode only applies to that single primitive. The no change mode does notapply to the other primitives that are not being written to, so these primitives can still be read.The byte-Write feature also affects the operation of the write first mode, as described in WriteFirst Mode Considerations.

Byte-Write Example

Consider a single-port RAM with a data width of 24 bits, or 3 bytes with byte size of 8 bits. Thewrite enable bus, wea, consists of 3 bits. The following figure illustrates the use of byte-writes,and shows the contents of the RAM at address 0. Assume all memory locations are initialized to0.

Figure 10: Byte-Write Example

WEA[2:0]

DINA[23:0]

RAM Contents

CLKA

ADDRA[15:0]

b011

FF EE DD

0000

CC BB AA 33 22 11 00 FF 0099 88 77 66 55 44

b010 b101 b000 b110 b010

00 EE DD 00 BB DD 33 22 77 33 FF 7799 BB 77

X21897-111318

Write First Mode ConsiderationsWhen performing a write operation in the write first mode, the concurrent Read operation showsthe newly written data on the output of the core. However, when using the byte-Write or theRead-to-Write aspect ratio feature, the output of the memory cannot be guaranteed.

Collision BehaviorThe Embedded Memory Generator core supports dual-port RAM implementations. Each port isequivalent and independent, yet they access the same memory space. In such an arrangement, itis possible to have data collisions. The ramifications of this behavior are described for bothasynchronous and synchronous clocks.





Collisions and Synchronous Clocks: General Guidelines

Synchronous clocks cause a number of special case collision scenarios. Using asynchronousclocks, when one port writes data to a memory location, the other port must not read or writethat location for a specified amount of time. This time (clock-to-Q, TCQ) is defined in the devicedata sheet, along with other block RAM/UltraRAM switching characteristics.

• Synchronous Write-Write Collisions: A write-write collision occurs if both ports attempt towrite to the same location in memory. The resulting contents of the memory location areunknown. The write-write collisions affect memory content, as opposed to write-readcollisions which only affect data output.

• Using Byte-Writes: When using byte-writes, memory contents are not corrupted whenseparate bytes are written in the same data word. RAM contents are corrupted only whenboth ports attempt to write the same byte. The following figure illustrates this case. Assumeaddra = addrb = 0.

Figure 11: Write-Write Collision Example

7777 XX00

WEA[3:0]

DINB[31:0]

RAM Contents

CLKA

b1100

DINA[31:0]

WEB[3:0] b0011

b0101

b1010

b1110

b0011

b1111

b0110 b1111

7654 3210 BBAA BBAA AAXX XXAA XXXX XXXX

FFFF 3210 BBBB BBBB 0000 0000 BBBB BBBB 2222 2222

7654 FFFF AAAA AAAA 7777 7777 AAAA AAAA 1111 1111

X21879-110918

• Synchronous Write-Read Collisions: A synchronous write-read collision might occur if a portattempts to write a memory location and the other port reads the same location. Whilememory contents are not corrupted in write-read collisions, the validity of the output datadepends on the write port operating mode.

• If the write port is in the read first mode, the other port can reliably read the old memorycontents.

• If the write port is in the write first or no change mode, data on the output of the read portis invalid.

• In the case of byte-writes, only updated bytes are invalid on the read port output.

The following figure illustrates write-read collisions and the effects of byte-writes. doutb isshown for when port A is in the write first mode and the read first mode. Assume addra = addrb= 0, port B is always reading, and all memory locations are initialized to 0. The RAM contents arenever corrupted in write-read collisions.





Figure 12: Write-Read Collision Example

00XX 00XX

WEA[3:0]

DOUTB AWF

RAM Contents

CLKA

b0000

DINA[31:0]

b0101 b0000 b1100 b1111

3322 00AA

AAAA AAAA 3322 1100 1111 1111

0000 0000

DOUTB ARF 0000 0000 00AA 00AA

00AA 00AA 00AA

3322 00AA

b0000

1111 1111

1111 1111

1111 111100AA 00AA0000 0000

XXXX XXXX XXXX

X21878-110918

Collisions and Simple Dual-port RAM

For simple dual-port RAM, the operating modes read first, write first, and no change are availableirrespective of clocking.

The simple dual-port RAM is like a true dual-port RAM where only the Write interface of the Aport and the read interface of B port are connected. The operating modes define the write-to-read relationship of the A or B ports, and only impact the relationship between A and B portsduring an address collision.

For synchronous clocking and during a collision, the write mode of port A can be configured sothat a read operation on port B either produces data (acting like read first), or producesundefined data (Xs). For this reason, it is always advised to use read first when configured as asimple dual-port RAM. For asynchronous clocking, Xilinx recommends setting the write mode ofport A to write first for collision safety.

Optional Read LatencyThe Embedded Memory Generator core allows optional output registers, which might improvethe performance of the core. You might choose to include register stages at two places: at theoutput of the block RAM/UltraRAM primitives and at the output of the core.

Registers at the output of the block RAM/UltraRAM primitives reduce the impact of the clock-to-out delay of the primitives. Registers at the output of the core isolate the delay through theoutput multiplexers, improving the clock-to-out delay of the Embedded Memory Generator core.Each optional register stage used adds an additional clock cycle of latency to the read operation.

The Register Port [A|B] Output of Memory Primitives option might be implemented using theembedded block RAM/UltraRAM registers, requiring no further device resources. All otherregister stages are implemented in device general interconnect. The following figure shows anexample of memory that has been configured using both output register stages for one of theports.





Figure 13: Embedded Memory Generator with Port [A|B] Read Latency=2

Embedded Memory Generator Core

CoreOutputRegisters

Latches

Latches

Block RAM Primitives

Block RAM EmbeddedOutput Registers

N/A

Latches

CE SSR*


N/A

Latches

CE SSR*


N/A

Latches

ENREGCE

MUX

CLK

RST

DOUT

CER*

D Q

R* : The reset (R) of the flop is gated by CEX21861-110918





Optional Pipeline Stages

Figure 14: Memory Configuration with Read Latency=4

D Q

D Q

D Q

D Q

2:1

2:1

2:1

2:1

D Q

CE>

R *

DOUT

REGCE

RST

CLK

EN

vv

vv

EN

EN

EN

EN

RAMs

R

4:1

X21862-110918

Register Clock Enable PinsThe output registers are controlled by the regcea/regceb pins; the data output from the corecan be controlled independent of the flow of data through the rest of the core. When using theregce pin, the last output register operates independent of the en signal.





Memory Output Flow ControlThe combination of the enable (en), reset (rst), and register enable (REGCE) pins allow a widerange of data flows in the output stage. The following figures are examples on how this can beaccomplished. Keep in mind that the rst and REGCE pins apply only to the last register stage.

The following figure depicts how rst can be used to control the data output to allow onlyintended data through. Assume that both output registers are used for port A, the port A resetvalue is 0xFFFF, and that en and regce are always asserted. The data on the memory is labeledLATCH, while the output of the BRAM/URAM primitive register is labeled REG1. The output ofthe last register is the output of the core, dout.

Figure 15: Flow Control Using rst

REG1

CLKA

ADDRA[7:0] AA BB CC

data(AA) data(BB)

RST

LATCH data(AA) data(BB) data(CC)

DOUT data(AA) data(BB)

DD

FFFFFFFF

data(CC)

data(DD)

data(CC) FFFF

data(DD)

X21877-070720

The following figure depicts how REGCE can be used to latch the data output to allow onlyintended data through. Assume that only the memory primitive registers are used for port A, andthat en is always asserted and rst is always deasserted. The data on the block RAM memorylatch is labeled latch, while the output of the last register, the block RAM embedded register, isthe core output, dout.

Figure 16: Flow Control Using REGCE

CLKA

ADDRA[7:0] AA BB CC

REGCE

LATCH data(AA) data(BB) data(CC)

DOUT data(AA) data(BB)

DD

data(DD)

data(CC)data(BB) data(CC) data(DD)

X21902-111318





Read Data and Read Enable Latency

The following figure shows the read data (LATCH) and read enable (en) latency when there are nooutput registers are used is shown below. The LATCH signal is the data at the output of theprimitive.

Figure 17: Read Data and Read Enable Latency with no Output Registers

ADDRA

EN

LATCH

CLKA

AA BB CC DD EE

Data(AA) Data(BB) Data(CC) Data(DD) Data(EE)

FF

Data(FF)

X21898-111218

The following figure shows the read data (REG1) and read enable (en) latency when the primitiveoutput register is used. REG1 is the data at the output of the primitive output register.

Figure 18: Read Data and rEad Enable Latency with Primitive Output Registers

ADDRA

EN

LATCH

CLKA

AA BB CC

Data(AA) Data(BB) Data(CC)

DD EE FF

Data(DD) Data(EE) Data(FF)

REG1 Data(AA) Data(BB) Data(CC) Data(DD) Data(EE) Data(FF)

X21876-110918

The following figure shows the read data (REG2, REG3) and read enable (en) latency when twopipeline stages are used along with the primitive output register. REG2 is the data at the outputof the pipeline stage 1, and REG3 is the data at the output of the pipeline stage 2.





Figure 19: Read Data and Read Enable Latency with Two Pipeline Stages Used

ADDRA

EN

LATCH

CLKA

AA BB CC DD EE

REG1

REG2 Data(AA) Data(BB) Data(CC) Data(DD) Data(EE)

REG3 Data(AA) Data(BB) Data(CC) Data(DD) Data(EE)



X21874-110918

The following figure shows the read data (dout) and read enable (en) latency when the coreoutput registers are used along with the primitive output register and two pipeline stages. doutis the data at the output of the core output register.

Figure 20: Read Data and Read Enable Latency with Core and Primitive OutputRegisters

ADDRA

EN

LATCH

CLKA

AA BB

Data(AA) Data(BB)

DD EE

Data(DD) Data(EE)

REG1 Data(AA) Data(BB) Data(DD) Data(EE)



Data(AA) Data(BB) Data(DD) Data(EE)DOUTX21873-110918

Reset Behavior

The Embedded Memory Generator core provides the reset to output stages of the Memory.

The following figure illustrates the reset behavior in the Embedded Memory Generator. Here,reset is not dependent on enable and both reset operations occur successfully.





Figure 21: Reset Behavior in Embedded Memory Generator

Read

aa

ENA

DOUTA[15:0]

CLKA

ADDRA bb cc

MEM(aa) INIT_VAL MEM(cc) INIT_VAL

NoOperation Reset Read Reset

RSTA

eedd

0000

ReadX21899-111318

Error Correction Capability and Error InjectionThe Embedded Memory Generator core supports the use of built-in Hamming ECC mode (bothECC encoding and decoding enabled for all utilized write and read ports, respectively), encode-only ECC mode (ECC encoding enabled for all utilized write ports), and decode-only ECC mode(ECC decoding enabled for all utilized read ports), for block RAM and UltraRAM mapping byutilizing the built-in ECC functionality of those memory primitives. The various ECC modes areenabled by changing the parameter ECC_MODE from its default of 0 (disable) to 1 (encode only), 2(decode only), or 3 (encode and decode). When both encoding and decoding are enabled, eachwrite operation generates eight protection bits for every 64 bits of data, which are stored withthe data in memory. These bits are used during each read operation to correct any single-biterror, or to detect (but not correct) any double-bit error.

The write and read widths must be multiple of 64 bits for both encode and decode mode.

When encode only mode is enabled, each write operation generates eight protection bits forevery 64 bits of data which are stored with the data in memory. The read data directly come tothe core output. In this case the write widths must be multiple of 64 and read widths must bemultiple of 72.

When decode only mode is enabled, write width must be a multiple of 72 bits as you mustprovide the encoded information along with actual data which are stored in the memory. Thedecoding is done on the memory read data. In this case the write widths must be a multiple of 72and read widths must be a multiple of 64.

This operation is transparent for you. Two status outputs (sbiterr and dbiterr) indicate thethree possible read results: no error, single error corrected, and double error detected. For single-bit errors, the Read operation does not correct the error in the memory array; it only presentscorrected data on dout.





Error Injection

The Embedded Memory Generator core supports error injection through two optional pins:injectsbiterr and injectdbiterr. You can use these optional error injection pins asdebug pins to inject single or double-bit errors into specific locations during write operations.You can then check the assertion of the sbiterr and dbiterr signals at the output of thoseaddresses. You have the option to have no error injection pins, or to have only one or both of theerror injection pins.

The two error injection ports, and the two error output ports are optional and become availableonly when the ECC option is chosen. If you have not selected the ECC feature, the primitive'sinjectsbiterr and injectdbiterr ports are internally driven to '0', and the primitive'soutputs sbiterr and dbiterr are not connected externally.

The following figure shows the assertion of the sbiterr and dbiterr output signals whenerrors are injected through the error injection pins during a write operation.

Figure 22: Assertion of SBITERR and DBITERR Signals by Using Error Injection Pins

CLK

EN

NOOPERATION WRITE READ

WE

1ADDR 0 2 3 1 2 3 4

INJECTSBITERR

INJECTDBITERR

ADIN 0 B C D E F 9

DOUT 0 A B C A Bx Cx

SBITERR

DBITERR

WRITE WRITE READ READ READ

SBITERRCorrectedData DBITERRIncorrectDataX21875-110918

When the injectsbiterr and injectdbiterr inputs are asserted together at the sametime for the same address during a write operation (as in the case of address 3 in the abovefigure), the injectdbiterr input takes precedence, and only the dbiterr output is assertedfor that address during a read operation. The data output for this address is not corrected.





Power SavingThe Embedded Memory Generator pipelines the en[a|b] input internally to drive memoriesand registers at each pipeline stage. For pipelined designs that do not tie en[a|b] High, thisresults in a power savings with respect to the Embedded Memory Generator (EMG) IP, whichapplies en[a|b] to all resources in parallel and therefore enables memories for the duration ofthe pipeline depth.

The sleep port and WAKEUP_TIME parameters are used in conjunction to implement varioussleep modes on the underlying memory primitives. When WAKEUP_TIME is 0, the sleep input isunused. A WAKEUP_TIME value of 2 implies a two clock cycle wakeup period, and thereforeeither the BRAM SLEEP port or URAM SLEEP port function.

You are responsible for complying with relevant signaling requirements to avoid data corruptionor uncertainty.

When CLOCKING_MODE is 0, the sleep input port is pipelined such that it is applied tosynchronous elements in alignment with their pipeline stage, synchronous to clka. You willcontinue to receive valid read outputs for WAKEUP_TIME clka cycles after sleep is asserted, andmust wait for READ_LATENCY_[A|B] + WAKEUP_TIME clka clock cycles following thesynchronous removal of sleep until the corresponding dout[a|b] values are again valid.

When CLOCKING_MODE is 1, the sleep input port is not pipelined such that it is appliedasynchronously to all elements in parallel. As such, the user will begin to receive invalid readoutputs immediately, and must wait for READ_LATENCY_[A|B] + WAKEUP_TIME clk[a|b]clock cycles following the asynchronous removal of sleep until the corresponding dout[a|b]values are again valid.

Auto Sleep ModeUltraRAM offers a feature called the Auto Sleep Mode that looks ahead to RAM accessesthrough a variable-length input pipeline, and dynamically sleeps when none are pending. WhenAUTO_SLEEP_TIME is 0 (default), the feature is disabled and no input pipeline exists. WhenAUTO_SLEEP_TIME is nonzero (valid only when MEMORY_PRIMITIVE is UltraRAM), thatnumber of input register stages is constructed for all module input signals. However, reset portsrst[a|b] will not have any pipeline stages. An equal number of register stages is required on allinputs for simulation accuracy.





ClockingThe Embedded Memory Generator core has two clocks: clka and clkb. Depending on theconfiguration, one or two clocks can be enabled.

ResetsThe Embedded Memory Generator core has two resets. Depending on the configuration, thecore can have different reset operations.

Related InformationMemory Output Flow Control





Chapter 5

Design Flow StepsThis section describes customizing and generating the core, constraining the core, and thesimulation, synthesis, and implementation steps that are specific to this IP core. More detailedinformation about the standard Vivado® design flows and the IP integrator can be found in thefollowing Vivado Design Suite user guides:

• Vivado Design Suite User Guide: Designing IP Subsystems using IP Integrator (UG994)

• Vivado Design Suite User Guide: Designing with IP (UG896)

• Vivado Design Suite User Guide: Getting Started (UG910)

• Vivado Design Suite User Guide: Logic Simulation (UG900)

Customizing and Generating the CoreThis section includes information about using Xilinx® tools to customize and generate the core inthe Vivado® Design Suite.

If you are customizing and generating the core in the Vivado IP integrator, see the Vivado DesignSuite User Guide: Designing IP Subsystems using IP Integrator (UG994) for detailed information. IPintegrator might auto-compute certain configuration values when validating or generating thedesign. To check whether the values do change, see the description of the parameter in thischapter. To view the parameter value, run the validate_bd_design command in the Tclconsole.

For details, see the Vivado Design Suite User Guide: Designing with IP (UG896) and the VivadoDesign Suite User Guide: Getting Started (UG910).

Figures in this chapter are illustrations of the Vivado IDE. The layout depicted here might varyfrom the current version.

The following section defines the possible customization options in the Embedded MemoryGenerator core Vivado IDE. The Native Interface Embedded Memory Generator core Vivado IDEincludes the following tabs:

• Embedded Memory Generator Basic Options Tab

• Embedded Memory Generator Other Options Tab

Chapter 5: Design Flow Steps


https://www.xilinx.com/cgi-bin/docs/rdoc?v=latest;d=ug994-vivado-ip-subsystems.pdf

https://www.xilinx.com/cgi-bin/docs/rdoc?v=latest;d=ug896-vivado-ip.pdf

https://www.xilinx.com/cgi-bin/docs/rdoc?v=latest;d=ug910-vivado-getting-started.pdf

https://www.xilinx.com/cgi-bin/docs/rdoc?v=latest;d=ug900-vivado-logic-simulation.pdf






Embedded Memory Generator Basic Options TabThe main Embedded Memory Generator tab is used to define the interface options and blockRAM port options for the core.

Figure 23: Embedded Memory Generator Basic Options Tab

• Operating Mode: The mode in which the Embedded Memory Generator core is used in the IPintegrator. There are two modes available when using IP integrator, and the default is memorycontroller.

• Memory Controller Mode: Select this mode if you are using AXI block RAM Controller(axi_bram_ctrl ) or a Local Memory Bus Interface controller(lmb_bram_if_ctrl). Allport parameters are greyed out as they are generated from the master.

• Stand Alone Mode: Select this mode if you are using a custom interface controller. You canselect and update all the available parameters.

• Generate Byte-Wide Address: Indicates that the internally generated address is byte-wise orfor word. The default value is true.

• Memory Type: In the memory controller mode, the memory type options are single-port RAMor true dual-port RAM. In stand alone mode, the memory type options are

• Single-port RAM





• Single dual-port RAM

• True dual-port RAM

• Single-port ROM

• Dual-port ROM

Note: In Memory Controller mode, Width and depth parameters calculated and generated by themaster (either by AXI BRAM Controller or LMB Controller to which the EMG IP is connected) based onthe width selected in the master IP and the Address range set in the Address Editor.

Note: In Memory Controller mode, Embedded Memory Generator does not support Asymmetric portwidths or data widths.

• Clocking Mode: Select the common clock option when the clock (clka and clkb) inputs aredriven by the same clock buffer. Otherwise, select the Independent Clock.

• Memory Primitive: The Embedded Memory Generator IP supports generating the memorystructure with the following:

• AUTO: Allow Vivado Synthesis to choose

• LUTRAM: Distributed memory

• BRAM: Block memory

• URAM: UltraRAM memory

• ECC Mode: The Embedded Memory Generator IP supports following ECC options.

• No ECC: Both ECC encoding and decoding are disabled for all utilized write and read ports.

• Encode Only: ECC encoding enabled for all utilized write ports.

• Decode Only: ECC decoding enabled for all utilized read ports.

• Both Encode and Decode: Both ECC encoding and decoding enabled for all utilized writeand read ports, respectively.

• Memory Depth: Depth of the memory.

• Cascade Height: Cascade height of the memory. Its default value is 0 and maximum value is16 for block RAM and 64 for UltraRAM

• Optimize Unused Memory: Default value is Optimize to enable the optimization of unusedmemory or bits in the memory structure. Select Do Not Optimize to disable the optimizationof unused memory or bits in the memory structure.

• Use Embedded Constraint: : Select this option to enable the set_false_path constraintaddition between clka of Distributed RAM and doutb_reg on clkb.

• Port [A/B] Options: The Port [A/B] options are as follows:





• Write Width: Specify the port [A|B] Write width.

• Read Width: Select the port [A|B] Read width from the drop-down list of valid choices. Theread depth is calculated automatically.

• Write Mode Port [A/B]: Specify the port [A|B] write mode.

• READ_FIRST

• WRITE_FIRST

• NO_CHANGE

• Read Latency Port [A/B]: Specify the number of register stages in the port [A/B] read datapipeline. Read data output to port douta/doutb takes this number of clka/clkb cyclesrespectively.

• Read Reset Value Port [A/B]: Specify the reset value of the port A/B final output registerstage in response to rsta/rstb input port is assertion.

• Port [A/B] Byte Wide Write: Selects whether to use the byte-write enable feature

• Byte Size(Bits): Byte size is either 8-bit (no parity) or 9-bit (including parity). The data width ofthe memory are multiples of the selected byte size.

Embedded Memory Generator Other Options TabThe Other Options tab is used to define memory initialization and other memory sleep optionsfor the core.





Figure 24: Embedded Memory Generator Other Options Tab

• Memory Initialization File: Specify none for no memory initialization, or specify the name of amemory initialization file. Enter only the name of the file with .mem extension.

• Auto Sleep Latency: Number of clk[a|b] cycles to auto-sleep

• 0 - Disable auto-sleep feature.

• 3-15 - Number of auto-sleep latency cycles.

• Wakeup Time: Select Disable Sleep to disable the dynamic power saving option, and selectUse Sleep Pin to enable the dynamic power saving option.

• Enable Assertions: Enables the internal assertions present in XPM memory. The default valueis false.

• Enable Write Protection: The default value is true, which means that write is protectedthrough enable and write enable, and the LUT is consequently placed before the memoryprimitive. This is the same as previous behavior.

This option can be disabled only if an advanced user can guarantee that the write enable(WE) cannot be given without enable (EN).





User ParametersThe following table shows the relationship between the fields in the Vivado® IDE and the userparameters (which can be viewed in the Tcl Console).

Table 2: User Parameters

Vivado IDE Parameter/Value1 User Parameter/Value Default ValueBasic Options Tab

Operating Mode USE_MEMORY_BLOCK Memory Controller

Memory Type MEMORY_TYPE Single Port RAM

Generate Byte-Wide Address ENABLE_32BIT_ADDRESS TRUE

Clocking Mode CLOCKING_MODE Common Clock

Memory Primitive MEMORY_PRIMITIVE BRAM

ECC Mode ECC_MODE No ECC

Memory Depth MEMORY_DEPTH 2048

Cascade Height CASCADE_HEIGHT 0

Optimize Unused Memory MEMORY_OPTIMIZATION Optimize

Use Embedded Constraint USE_EMBEDDED_CONSTRAINT FALSE

Port A Options Tab

Write Width WRITE_DATA_WIDTH_A 32

Read Width READ_DATA_WIDTH_A 32

Write Mode Port A WRITE_MODE_A WRITE_FIRST

Read Latency Port A READ_LATENCY_A 1

Read Reset Value Port A READ_RESET_VALUE_A 0

Port A Byte Wide Writes ENABLE_BYTE_WRITES_A TRUE

Byte Size(Bits) BYTE_WRITE_WIDTH_A 8

Port B Options Tab

Write Width WRITE_DATA_WIDTH_B 32

Read Width READ_DATA_WIDTH_B 32

Write Mode Port B WRITE_MODE_B WRITE_FIRST

Read Latency Port B READ_LATENCY_B 1

Read Reset Value Port B READ_RESET_VALUE_B 0

Port B Byte Wide Writes ENABLE_BYTE_WRITES_B TRUE

Byte Size(Bits) BYTE_WRITE_WIDTH_B 8

Other Options Tab

Memory Initialization File MEMORY_INIT_FILE None

Auto Sleep Latency AUTO_SLEEP_TIME 0

Wakeup Time WAKEUP_TIME Disable Sleep

Enable Assertions SIM_ASSERT_CHK FALSE





Table 2: User Parameters (cont'd)

Vivado IDE Parameter/Value1 User Parameter/Value Default ValueEnable Write Protection WRITE_PROTECT TRUE

Notes:1. Parameter values are listed in the table where the Vivado IDE parameter value differs from the user parameter value.

Such values are shown in this table as indented below the associated parameter.

Output GenerationFor details, see the Vivado Design Suite User Guide: Designing with IP (UG896).

Constraining the CoreFollowing are the constraints associated with this core:

Clock Constraints

create_clock -period 20.0 -name aclk [get_ports clka]

Following constraint is applicable only for dual-port memories.

create_clock -period 20.0 -name bclk [get_ports clkb]

Other Constraints

set_false_path constraint is needed for the independent clock distributed RAM basedmemory if the design takes care of avoiding address collision (write address != read address atany given point of time). Set USE_EMBEDDED_CONSTRAINT = 1 if IP needs to take care ofnecessary constraints.

Simulation

For details, see the Vivado Design Suite User Guide: Logic Simulation (UG900).

Synthesis and Implementation

For details about synthesis and implementation, see the Vivado Design Suite User Guide: Designingwith IP (UG896).








Chapter 6

Detailed Example DesignThere is no example design for this IP core release.

Chapter 6: Detailed Example Design




Chapter 7

Test BenchThere is no test bench for this IP core release.

Chapter 7: Test Bench




Appendix A

Verification, Compliance, andInteroperability

The Embedded Memory Generator core and the associated XPM libraries are rigorously verifiedusing advanced verification techniques, including a constrained random configuration generatorand a cycle-accurate bus functional model.

Simulation

The Embedded Memory Generator core has been tested with the Xilinx® Vivado® Design Suite,Xilinx XSIM, Cadence Incisive Enterprise Simulator (IES), Synopsys VCS and VCS MX, and MentorGraphics Questa SIM.

Appendix A: Verification, Compliance, and Interoperability




Appendix B

UpgradingThis appendix is not applicable for the first release of the core.

Appendix B: Upgrading




Appendix C

DebuggingThis appendix includes details about resources available on the Xilinx® Support website anddebugging tools.

IMPORTANT! IP license level is ignored at checkpoints. The test confirms a valid license exists. It does notcheck IP license level.

Finding Help on Xilinx.comTo help in the design and debug process when using the core, the Xilinx Support web pagecontains key resources such as product documentation, release notes, answer records,information about known issues, and links for obtaining further product support. The XilinxCommunity Forums are also available where members can learn, participate, share, and askquestions about Xilinx solutions.

DocumentationThis product guide is the main document associated with the core. This guide, along withdocumentation related to all products that aid in the design process, can be found on the XilinxSupport web page or by using the Xilinx® Documentation Navigator. Download the XilinxDocumentation Navigator from the Downloads page. For more information about this tool andthe features available, open the online help after installation.

Answer RecordsAnswer Records include information about commonly encountered problems, helpful informationon how to resolve these problems, and any known issues with a Xilinx product. Answer Recordsare created and maintained daily ensuring that users have access to the most accurateinformation available.

Answer Records for this core can be located by using the Search Support box on the main Xilinxsupport web page. To maximize your search results, use keywords such as:

• Product name

• Tool message(s)

Appendix C: Debugging


https://www.xilinx.com/support.html

https://forums.xilinx.com/




https://www.xilinx.com/support/download.html





• Summary of the issue encountered

A filter search is available after results are returned to further target the results.

Technical SupportXilinx provides technical support on the Xilinx Community Forums for this LogiCORE™ IP productwhen used as described in the product documentation. Xilinx cannot guarantee timing,functionality, or support if you do any of the following:

• Implement the solution in devices that are not defined in the documentation.

• Customize the solution beyond that allowed in the product documentation.

• Change any section of the design labeled DO NOT MODIFY.

To ask questions, navigate to the Xilinx Community Forums.

Debug ToolsThere are many tools available to address Embedded Memory Generator design issues. It isimportant to know which tools are useful for debugging various situations.

Vivado Design Suite Debug FeatureThe Vivado® Design Suite debug feature inserts logic analyzer and virtual I/O cores directly intoyour design. The debug feature also allows you to set trigger conditions to capture applicationand integrated block port signals in hardware. Captured signals can then be analyzed. Thisfeature in the Vivado IDE is used for logic debugging and validation of a design running in Xilinx®

devices.

The Vivado logic analyzer is used to interact with the logic debug LogiCORE IP cores, including:

• ILA 2.0 (and later versions)

• VIO 2.0 (and later versions)

See the Vivado Design Suite User Guide: Programming and Debugging (UG908).

Simulation DebugFor details about simulating a design in the Vivado Design Suite, see the Vivado Design Suite UserGuide: Logic Simulation (UG900).





https://www.xilinx.com/cgi-bin/docs/rdoc?v=latest;d=ug908-vivado-programming-debugging.pdf




Hardware DebugHardware issues can range from link bring-up to problems seen after hours of testing. Thissection provides debug steps for common issues.

General ChecksEnsure that all the timing constraints for the core were properly incorporated from the exampledesign and that all constraints were met during implementation.

• Does it work in post-place and route timing simulation? If problems are seen in hardware butnot in timing simulation, this could indicate a PCB issue. Ensure that all clock sources areactive and clean.

• If using MMCMs in the design, ensure that all MMCMs have obtained lock by monitoring thelocked port.

• If your outputs go to 0, check your licensing.





Appendix D

Additional Resources and LegalNotices

Xilinx ResourcesFor support resources such as Answers, Documentation, Downloads, and Forums, see XilinxSupport.

ReferencesThese documents provide supplemental material useful with this guide:

1. Vivado Design Suite: AXI Reference Guide (UG1037)

2. Vivado Design Suite User Guide: Embedded Processor Hardware Design (UG898)

3. Vivado Design Suite User Guide: Designing IP Subsystems using IP Integrator (UG994)

4. Vivado Design Suite User Guide: Logic Simulation (UG900)

5. Vivado Design Suite User Guide: Implementation (UG904)

6. Vivado Design Suite User Guide: Designing with IP (UG896)

7. ISE to Vivado Design Suite Migration Guide (UG911)

8. Vivado Design Suite User Guide: Programming and Debugging (UG908)

9. Vivado Design Suite User Guide: Getting Started (UG910)

Revision HistoryThe following table shows the revision history for this document.

Appendix D: Additional Resources and Legal Notices




https://www.xilinx.com/cgi-bin/docs/ipdoc?c=axi_ref_guide;v=latest;d=ug1037-vivado-axi-reference-guide.pdf

https://www.xilinx.com/cgi-bin/docs/rdoc?v=latest;d=ug898-vivado-embedded-design.pdf



https://www.xilinx.com/cgi-bin/docs/rdoc?v=latest;d=ug904-vivado-implementation.pdf


https://www.xilinx.com/cgi-bin/docs/rdoc?v=latest;d=ug911-vivado-migration.pdf

https://www.xilinx.com/cgi-bin/docs/rdoc?v=latest;d=ug908-vivado-programming-debugging.pdf




Section Revision Summary07/14/2020 Version 1.0

Initial release. N/A

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