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The Next Wave of EMBEDDED ArchitectureAltera’s SoC FPGAs Meet the Performance Requirements of the Most Demanding ApplicationsInterview with Altera’s Chris Balough

Embedded IoT Security

Carbon Nanotube Memory

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Embedded Developer CONTENTS

TECH TRENDS

Securing the IoTIcon Labs Offers Embedded Security for Smart Devices

CONTEST HIGHLIGHT

Winning Projects from NXP’s Big I.D.E.A. Contest

INDUSTRY INTERVIEW

The Next Wave of Embedded ArchitectureInterview with Altera’s Chris Balough

EEWeb FEATURE

Embedded NRAM MemoryNantero Utilizes Carbon Nanotubes for Unparalleled High-density Memory

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TECH TRENDS

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Icon Labs Offers Embedded Security for Smart DevicesYou’ve heard the warning. You’ve ignored it and now, it’s too late. You’ve been

hacked. More sinister than identity theft, hacking dooms your privacy, your home,

your car, and your family with the inevitability of cyber-intrusion. Unfortunately,

Hollywood writers aren’t fantasizing these cyber-crises; they’re fictionalizing

today’s headlines. While IoT-ready devices are being rushed to the market at

unprecedented speeds to keep up with demand, important security protocols are

getting pushed to the side, creating unsafe smart networks in hospitals, at work,

and at home. The good news is that Icon Labs—an embedded security solutions

company—has developed a Floodgate Security Framework to prevent these

occurrences from happening.

Securingthe IoT

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has been in the embedded world for over 20 years, focused on real-time operating system-based devices. “Over the last several years, our specialty has been insuring the security of embedded devices,” says Ernie Rudolph, Executive Vice President of Icon Labs. “The reason is that these devices were not designed to be connected to the Internet and today they are. Twenty years ago, few thought of the Internet connected world. Twenty years ago nobody ever thought it would be important to secure those devices. Now we know and many of these devices are now out in the world, unprotected and vulnerable to attack.”

For example, many medical devices are at risk. It may sound like science fiction, but European hackers recently invaded blood gas analyzers in a hospital laboratory and turned these devices into a backdoor into the entire network of medical records. In another instance, cyber-pirates installed malware into x-ray machines, and patient medical records were uploaded to the Internet and sold on the black market.

Rudolph goes on to warn that not even pacemakers inside of patients are secure—it’s possible for embedded medical devices to be commandeered too, though it’s unlikely. That’s because most security breaks are aimed at gaining

access to personal medical records and health insurance information which can be worth 20 times the value of a credit card record on the black market. While still a threat to the health of the patient, it is known that most disaffected cyber-technicians are simply after the money.

The basic software architecture of many medical devices and hospital systems has not upgraded to improve security since then, due to an overhaul that would cost hundreds of billions of dollars. According to Rudolph, securing medical devices from cyber-attack is just one of Icon Labs goals. Their Floodgate Security Framework protects everything from IoT appliances to the aerospace industry.

“What we have done is taken the lessons learned in the IT world about what needs to be done for security and tailored those to the embedded world,” Rudolph explains. “We can then bring attention to its importance, and build a framework for our products around the necessary elements of embedded security: things like secure boot, firewalls, intrusion detection, secure remote updates, and protocol filtering.”

Recent exploits of embedded devices have breached the realm of urban infrastructure. “There was a cyber-attack in Puerto Rico a few years ago,” says Rudolph. “It targeted

smart meters and sold discounts to change the meter so you get billed a lower electric bill. The reported loss on that was over 400 million dollars.”

Other unlikely, but vulnerable targets include machines as innocuous as refrigerators and printers. Hackers have been known to turn web-connected refrigerators and printers into bots that send out spam. “That leads to the second piece of our solution,” says Rudolph. “The first is being able to block unauthorized access. The second is visibility to the enterprise and the ability to manage, audit, track, correct, change rules, and keep those devices safe.”

In the event that an unauthorized access is attempted, reporting it is an essential part of the security paradigm, particularly in the commercial arena. The FDA recently reported hundreds of medical devices were shipped with hard-coded passwords—a security problem waiting to happen. If those passwords were found—which is not that difficult—hackers can

Ernie Rudolph, Executive Vice President of Icon Labs

Most security breaks are aimed at gaining access to personal medical records and health insurance information which can be worth 20 times the value of a credit card record on the black market.

Icon Labs’ Floodgate Security Framework protects everything from IoT appliances to the aerospace industry.

gain unfettered access to control the device, get more information, and, if it’s on the network, potentially use the device as an access point to infiltrate the network. This is happening regularly with credit card information being infiltrated and utilized—in particular, the epic Target Stores debacle last year, when forty million credit card numbers were stolen.

Insurance authorization access codes are even more valuable in the medical space and the losses could be even more staggering. Liabilities keep mounting as thousands of IoT devices are being rushed into development without commensurate developments in security. For any start-up, the prize in technology is always about being first to market and security takes a back seat.

“That is one of the reasons Icon Labs began our initiative called the Internet of Secure Things,” Rudolph says. “Our goal is to raise awareness that security should be designed in.” As hacker attacks are publicized, people are beginning to recognize what happens when security is not considered first. As Rudolph notes,

ICON LABS

TECH TRENDS

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“Executives are now asking if systems are secure before launching. We hope to expand those kinds of questions.”

As far as embedded devices are concerned, securing them at the very beginning, in the design phase, can be inherently less costly than trying to fix them after they have been discovered to have avenues for attack. Once a device is installed, modification is always more difficult and expensive. For this reason, Icon offers its Floodgate Defender Appliance—a line of security devices that are the first of their kind to protect connected devices from Internet-based attacks. Installed in front of a connected device that lacks designed in security, these modules run Icon’s Floodgate software and provide many safety functions like blocking, analyzing, feeding information back, and awareness of

unauthorized access. The information is sent back to an enterprise system to initiate action. This intuitive information affords flexibility to change rules and behaviors and integrates with security information and event management system to perform analytics.

Rudolph calls this “big data” for security. “Some engineers don’t like that term, but from a marketing standpoint, it makes sense, because we are gathering a lot of information, feeding it back, and analyzing it broadly to see if there are patterns that should not occur.”

Most of us take for granted that every device we put on an IT network has a firewall. In the industrial space and the operational technology space, that isn’t the case. One revelation that Icon Labs deals with is that their customers revealed 70 percent of the threats are internal. Not just malicious intrusions, but also accidental, with serious financial impacts. In other words, you can build a fence around your house, you can lock the door, but what if the intruder is locked inside? Blocking or mitigate against those impacts is an important piece of what Icon provides by securing the individual devices inside the perimeter.

“For example, some industrial protocols, like Modbus IP, do not have security,” says

Rudolph. “If someone has access to use Modbus, they can not only read, but write, because that capability inherently exists in this insecure protocol. Our protocol filtering determines whether that person is allowed to read or write. All that does is help to keep honest people honest. “

So what’s in the pipeline of prevention? Today, companies are building secure hardware modules that provide security and secure storage and encryption capability. The next necessity is software to utilize and manage these functions. Icon Labs is working with several manufacturers where software is used to manage the access and encryption storage and the secure update capability provided by the hardware. Icon Labs is also targeting the smart home with its Floodgate™ at Home, which features its suite of security products that provide device protection, management, and incident reporting via a secure web page. OEMs can embed Floodgate security in the communication chips found in many of the up-and-coming smart home devices like thermostats, smoke detectors, and home health sensors. The Floodgate Security Framework offers users unprecedented security in a new technology field that offers a broad swath of hackable access points. Luckily for you, Icon Labs has got you covered.

OEMs can embed Floodgate security in the communication chips found in many of the up-and-coming smart home devices like thermostats, smoke detectors, and home health sensors.

GRAND PRIZEClemens Valens

2015 Dual PCB Configurable Logic Design Contest

Over the six-month period from January to June

2015, NXP Logic sponsored a contest, hosted by

Convergence Promotions, that involved using not

one, but multiple products, like the new NXP 4AUP2G57GM

dual configurable logic devices in combination with the NXP

protection and filtering, small signal MOSFETs, small signal

diodes and load switch devices.

Co-branded as the 2015 Big IDEA (The International Design

Engineering Award), the contest was co-sponsored by

Mouser, and involved using Mouser’s new MultiSIM BLUE

online circuit configuration tool in combination with a

development board.

The response was very enthusiastic, with close to 600

engineers from over two dozen countries competing in the

contest over the six-month period from January to June

2015, and vying for over $10,000 in prizes.

NXP and Mouser received many exceptional entries.

Finalists, who are highlighted in this article, designed

projects as complex and varied as a Class D audio amplifier,

an amateur radio, a floor-cleaning robot, a telsa coil, and a

vibrating bracelet.

I.D.E.A.The Big

Winners

http://www.convergencepromotions.com/TheBigIdea

These applicants successfully completed three levels of competition during which close to 600 engineers from over two dozen countries competed, vying for over $10,000 in prizes.

» In the entry level, competitors submitted their registration and a questionnaire.

» In the submission level, contestants produced a schematic using the schematic tool MultiSIM BLUE from Mouser using a prescribed list of NXP Devices, including the Logic 74AUP2G57GM device.

» By the final completion level, contestants were sent a design kit containing an evaluation board with the prescribed elements, and a manual to help them with their final design

These submissions consisted of a detailed record and documentation of their entry process and results including:

» Videos and schematics

» Proof of execution on the finished board

Scoring was based on Creativity (100 pts.), Documentation (100 pts.), and Demonstration Videos (100 pts.) with Bonus Multipliers that included using each of these products in the block diagram or schematic and in the final board design:

» Protection & Filtering (20 Points)

» Small Signal MOSFETs (20 Points)

» Small Signal Diodes (20 Points)

» Load Switches (20 Points)

» Using MultiSIM BLUE (20 Points)

All for a total of 400 achievable points.

For more information about the contest and the winning projects, visit: http://www.convergencepromotions.com/TheBigIdea

About the Contest

» GRAND PRIZE WINNER ($3000) Federico Armesto of Argentina with his Class D Audio Amplifier

» FIRST PLACE WINNER ($2000) Frank Latos of the USA with his Amateur Radio

» SECOND PLACE WINNER ($1500) Ryszard Milewicz of Poland with his Clear Robo 2

» THIRD PLACE WINNER ($1000) Andreas Fiessler of Germany with his Tesla Coil

» HONORABLE MENTION ($500) Clemens Valens of France with his Vibrating Bracelet

The Winners

Frank Latos designed a transceiver for the amateur radio 40 meter band (7.0 - 7.3 MHz). It features a single-conversion receiver (not to be confused with the simpler “direct conversion” type), is designed to provide 1W of output and operates in the CW (“Morse code”) mode. For his design, Frank only used the parts provided by the Big Idea contest kit, with the exceptions of an external power supply and external amplified speaker.

Frank’s design (see below) had six basic components:

• An RF amplifier and local oscillator (LO), which when mixed provided the intermediate frequency (IF)

• A crystal filter/IF amplifier

• A beat frequency oscillator (BFO) for converting the IF signal to audio and

Federico Armesto used NXP’s 74AUP2G57GM Dual Configurable Logic ICs to make the control stage of a class D amplifier (see below). This type of amplifier uses a PWM generated signal to drive a full bridge. In creating his amplifier, he implemented several supporting circuits, including a dead time generator, a PWM generator, a control stage to avoid power failures, and a drive stage.

Federico began with the dead time generator, which he used to drive the FETs of a half or full H bridge. When driving the FETs in a bridge configuration, precautions should be taken to ensure that the FETs on the same column will not conduct at the same time. For this purpose, Federico implemented the dead time circuit to generate two signals, one for driving the high side FET and one

GRAND PIZE

Class D Audio Amplifier

Federico Armesto, Designer Argentina

FIRST PLACE

Amateur Radio

Frank Latos, Designer USA

Class D Audio Amplifier Board Implementation

Amateur Radio Board Implementation

for the lower side. He implemented this circuit only one capacitor, one resistor and a single 74AUP2G57GM IC (configurable multi-function gate circuit from NXP with Schmitt trigger inputs).

He then moved on to create the PWM (which he first simulated using Mouser’s MultiSIM Blue and a 100KHz square wave), the control stage, and the drive stage. Federico managed to use all of the contest-required parts, as well as capture his schematics and simulate his design on the MultiSIM Blue.

for providing the transmit versus receive frequency shifts

• Aproduct detector for mixing the IF and BFO signals to produce the audio output

• A transmit mixer for creating a 7 MHz signal from the LO and BFO

• The final audio amplifiers

Frank managed to use the contest kit MOSFETs, which were intended as power switches, to perform as RF amplifiers, and used all four sections of NXP’s 74AUP2G57GM logic ICs. He used Mouser’s MultiSIM along with NXP’s SPICE models to perform simulations. The gain predictions he obtained from his simulations matched the actual design results quite well.

Andreas Fiessler came up with the idea of designing a Tesla Coil driver (see Figure 4) after examining the various available parts that arrived with his contest kit. A Tesla coil uses a low voltage, high frequency current on the primary side to induce a very high voltage on the secondary side. Andreas decided to create a solid-state tesla coil, or a coil controlled by transistors. After a series of experiments with different designs, he ended up using a cable as an antenna placed near the coil to provide a feedback signal, which upon filtering could be used to trigger the driver.

Ryszard Milewicz modified a previous design for a small floor-cleaning robot to create his Clear Robo 2 entry (see below). His objective was to design a 2-wheeled robot that travels on the floor, and upon detecting a wall, furniture, or some other barrier, changes its route and continues.

Ryszard began by creating the “brain” of the robot, using switches as detectors of obstacles and to aid in navigation. Using LEDs on the outputs to confirm proper operation, he verified that his circuit worked as designed. To complete the robot, he assembled a three-wheel chassis, upon which he mounted the PC board “brain” and a battery pack.

Tesla Coil Driver Circuit

Clear Robot 2 Floor Cleaning Robot

Although in the previous implementation he had designed his schematic by hand, this time around he was able to use the MultiSIM software to create his schematics.

The majority of Andreas’ experimentation involved the gate driver design. After a couple of tries, he managed to get a circuit that performed well enough to achieve a working Tesla coil. The final experimentation involved tuning of the coil position, number of windings, etc.

SECOND PLACE

Clear Robo 2

Ryszard Milewicz, Designer Poland

THIRD PLACE

Tesla Coil

Andreas Fiessler, Designer Germany

CLICK HERE

Meet the experts in newSoC FPGA technologies.

FRANKFURT, GERMANYOCTOBER 14, 2015

SHENZHEN, CHINANOVEMBER 3, 2015

SANTA CLARA, CALIFORNIASEPTEMBER 30, 2015

™

SPONSORS

Get an edge in developing your next system design through in-depth technical workshops and connecting with industry leaders. ASDF are the industry’s �rst events dedicated to exploring the bene�ts of SoC FPGAs. What you’ll learn:

• The future of technology for IoT, data centers, industrial, military/aerospace, communications and more

• In-depth technical breakouts with hardware and software tracks

• Hands-on software workshop on embedded software development for ARM-based SoC FPGAs

• Leading edge technology demos and the opportunity to speak directly with industry experts

Attendance is free of charge, but space is limited. Request registration at www.altera.com/us-asdf

After carefully examining the specifications of the contest kit parts, Clemen Valens realized that many were applicable for low-power, battery-operated applications, and so oriented his thoughts to the direction of wearable electronics. He settled upon the idea of a vibrating bracelet (see below). A vibrating bracelet has use in a variety of applications, such as haptic communication (silent, non-visual communication), stress reduction, heart rate monitoring, or even as a metronome for musicians.

To control a vibration motor, one needs a driver, and this is the circuit Clemens designed. He first designed and simulated the circuit in the MultiSIM Blue software, and then transferred it to the contest demonstration board.

Except for the passive components (resistors & capacitors) Clemens built the complete circuit with the parts available in the contest kit demonstration board.

Mockup of Vibrating Bracelet

HONORABLE MENTION

Vibrating Bracelet

Clemens Valens, Designer France

INDUSTRY INTERVIEW

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Interview with Altera’s Chris Balough

Altera’s SoC FPGAs Meet the Performance Requirements of the

Most Demanding Applications

The Next Wave of EMBEDDED Architecture

As today’s computing applications become increasingly more complex, developers are

constantly seeking high-performance SoCs that not only provide low system cost, but add the flexibility of programmable logic. While architectures up to this point have addressed some of these needs, Altera’s Chris Balough states “History has shown us that every architecture reaches a limit.” With that in mind, Altera has aimed its efforts towards looking beyond the current limitations to create a line of SoC FPGAs, which boasts impressive performance specifications and flexibility to meet the high degree of system requirements of today’s applications. However, not all SoC FPGAs are created equal.

EEWeb spoke with Balough to elucidate this new field of embedded architecture.

INDUSTRY INTERVIEW

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What are the benefits that come from combining an FPGA with an SoC?At a fundamental level, this combination is a classic integration benefit. If you can do on a single monolithic die, which was previously done in two die, your solution will be lower cost, lower power, less area, and will eliminate the delay times across the two-chip scenario—leading to high levels of performance. This value proposition is ideal for people who have adopted FPGAs, which have become extremely widespread now and happen to use a comparably classed processor. This is a large market for us, and we help take what the users are doing at the system level and make it better, which allows Altera to service more of the board. There is also a second, emerging benefit of this combination, which uses them as an integrated computing platform.

Could you explain more about the devices’ use as an integrated computing platform? People are beginning to think about SoC FPGAs not as two separate chips with two separate development environments that happen to inhabit the same piece of silicon, but as an integrated computing platform. In our view, we see this as the next wave of embedded computing architectures and topologies. The evolution started

many years ago with a single processor, like the x86. From there, the goal was to find more ways to leverage Moore’s Law and do architectural enhancements to increase performance continuously. As the needs for processing continue to grow, the evolution moved to multi-core processors because the industry ran into a dead end in terms of being able to crank up the performance of a single core.

There are still limitations with homogeneous multi-core computing, and what started to emerge here recently was this idea of heterogeneous multi-core computing. ARM coined the term big.LITTLE, which means that they will provide developers different kinds of processors that can be used together. The big, fast, power-hungry processors can be used only for the workloads that need it, and smaller, more power-efficient processors will be for the more manageable types of workloads. This is the most power-efficient and area-efficient combination by the idea of heterogeneous multi-cores.

History has shown that each architecture reaches a limit. Our projection is that the next phase, which we are calling fine-grain heterogeneous computing, will use FPGAs as accelerators in data centers, as well as in many embedded applications. This will use the capacity and the innate

capabilities of the FPGA to be fine-grain on specific functions that need to be accelerated or computed, and coupling that with the traditional flexible compute idea of a traditional processor. We see that combination as really profound for the next stage in computing.

What differentiates Altera’s SoCs from the competition?Both Altera and Xilinx launched into the SoC FPGA category at the 28-nanometer node, which came out in 2012. Increasingly, our customers are now thinking of this in more traditional application processor terms—they are thinking of us as a long-term application processor vendor. They are looking at us as the ones that will take care of the software application code, which is often the crown jewel for our customers.

The main tagline that we use is “architecture matters.” We have done a very detailed comparison of these two products and we have published an in-depth white paper on the silicon and development software. There are a number of items, as you go from 50-thousand feet down to a much closer view, where we think we got it right from an overall device and total solution architecture standpoint. One example of that is we support 32-bit-wide DRAM with error correction code (ECC) on all of our devices, and our competitors do not. In many embedded applications, it’s just unthinkable that you wouldn’t have the ability to have ECC memory, especially in reliability-intensive markets like automotive and industrial control.

People are beginning to think about SoC FPGAs not as two separate chips with two separate development environments that

happen to inhabit the same piece of silicon, but as an integrated computing platform.

Our projection is that the next phase, which we are calling fine-grain heterogeneous computing, will use FPGAs as accelerators in data

centers, as well as in many embedded applications.

INDUSTRY INTERVIEW

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A good example of software differentiation is how we have stuck with open standard, which our customers really value. We didn’t create our own development tool—we decided to partner with ARM and develop their flagship DS-5 software and turn it into the Altera edition of the DS-5. With our kits, the customer gets ARM’s DS-5 full development software tool as a part of the kit experience. We partnered with ARM to innovate what we call FPGA-adaptive debug, which allows the debug environment that is native to DS-5 to connect with the FPGA debug environment so that you can really synchronize the debug sessions.

The portfolio level is becoming a dominant way of looking at things, and that is where the differences between our competitors and us become especially significant. Altera is in this for the long haul in a big way. We see this as a substantial disruption in the programmable logic business. After 28-nanometers, we went all-in and invested in a full SoC FPGA offering at 20-nanometers in our Arria 10 family. For our 14-nanometer family, we are all-in with the Stratix 10. Furthermore, we have also upgraded to the 64-bit processor in that family. When we present at a portfolio layer, we have a very strong story to tell because we have the best products at 28-nanometers that are in the cost-sensitive range. At the advanced 20-nanometer node, we are the only ones in the game if you want a 20-nanometer mid-range SoC FPGA. We are also the only game in town if you want the most advanced

technology at the highest densities. Above one million logic elements (LE), our competitors have no stated plans to be in the business. We are the technology leader at 14-nanometers at the high density and we are the portfolio leader with an all-in game plan at 28- and 14-nanometers.

Let’s talk about Stratix 10 and the switch to the Intel Tri-Gate process. Could you comment on that switch and the benefits you have seen as a result?As you can imagine, that wasn’t a light decision—this switch was considered for a long period of time. Furthermore, we have a deep, lasting relationship with Taiwan Semiconductor Manufacturing Company (TSMC), so we really only moved with careful study. So far, it is living up to our expectations. For one thing, Intel is so advanced and we have historically only rolled out products very early in the process technology life—we are one of the firsts to be on the process technology and we are taping out right at the time that it is fully qualified for production. Intel was in volume production of their 14-nanometer Tri-Gate process since last year, which is a very new experience for us. They have shipped billions of these advanced transistors in production, and everyone else has shipped zero. We inherited a very mature production process, and that is significant. Since they are on a true 14-nanometer process, we are able to announce 5-million LE devices, which is five times bigger than the largest monolithic FPGA that has ever been produced. The performance, density, and capacity we can achieve on these is where you see the true value of the 14-nanometers.

MYLINK

https://www.altera.com/events/northamerica/altera-soc-developers-forum/overview.highResolutionDisplay.html

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Additionally, we inherited some amazingly advanced packaging technologies like the embedded, multi-die interface bridge—or the EMIB technology—that we are using to deploy the Stratix 10 and the transceiver technology. That allows us to decouple the transceivers and use existing, solid 20-nanometer transceiver tiles, which are extremely high performance, and couple that with a digital FPGA device. This allows the device to be less limited on what would be a typical interposer-based multi-chip approach. With the EMIB technology, you are no longer reticle limited. You can build your base-FPGA to the full reticle size and get rid of all the transceivers, which allows you to basically fill the reticle with FPGA gates. The combination of the 14-nanometer process and the packaging technology allows us to deliver a knockout technology winner.

What markets or industries will benefit most from Altera’s SoC FPGAs?We deployed this three-generation portfolio, so we expect to see a substantial adoption of SoC FPGA technology in all of our end markets. The first generation at 28-nanometers was tuned a little more towards the industrial automation and automotive area. The Arria 10 generation is geared more towards wireless infrastructure, storage, test, medical, and high-end industrial automation. The Stratix 10 family is what takes us into heavy-duty data center and computing industries, as well as military and defense and wire communications.

The Altera SoC Developers Forum (ASDF) is coming up on October 14th. What are your goals with this forum and do plan on getting developers not only educated, but engaged with SoC FPGAs?

We have come a long way on that already. For example, for 28-nanometers, we have 24 different production-qualified operating systems. We have already tremendous engagement and momentum in the OS ecosystem space with a number of design partners and development kits. The ASDF is made to be an amplifier and accelerator because what we haven’t done yet is get everyone together for a single-purpose SoC FPGA-focused event.

In your view, what would be the main reason to attend the ASDF? If you are a developer, this is a can’t-miss event because this is going to be a single day of the most in-depth exposure you can get to the very latest technology from Altera and our industry-leading technology partners such as ARM, Lauterbach, MathWorks, Terasic, Wind River Systems, Arrow, and many more. There will be technical tracks that will highlight some of the newest case studies and tips and tricks on how to accelerate your development and be more productive. There will also be highlights on what is coming next in the industry.

For more information about the ASDF event, visit: https://www.altera.com/events/northamerica/altera-soc-developers-forum/overview.highResolutionDisplay.html

· ASDF Silicon Valley on September 30 (Santa Clara) · ASDF Europe on October 14 (Frankfurt, Germany) · ASDF Asia on November 3 (Shenzhen, China

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EEWeb FEATUREEmbedded Developer

NRAM from Nantero Utilizes

CARBON NANOTUBES for Unparalleled High-density Memory

50 times stronger than steel — 1/50,000th the diameter of a human hair

Carbon Nanotube used to create Nantero’s NRAM®

In the fascinating microcosmic world of modern

semiconductor technology, it’s sometimes amazing

to realize that there are still huge leaps and bounds

ahead in both form and function. What may be even

more incredible in what is undeniably one of the tech

industry’s most competitive fields—memory—is that

a company like Massachusetts startup Nantero is

confidently holding their own on the crest of a market

dominated by household name giants like Micron

and Samsung.

With a little forethought and considerate

collaborative effort—just the sort of stuff that turns

your everyday startup into a force to be reckoned

with—Nantero’s co-founder, president, and CEO Greg

Schmergel came face to face with Tom Rueckes, a

PhD at Harvard who had an idea to make memory

using carbon nanotubes. Of course, as Greg recalls, he

knew the basic idea, but the question remained: “OK,

but what exactly is a carbon nanotube?” In coming

to answer that question, Greg, Tom, and Nantero

have found themselves standing deservedly on the

leading edge of the development of the memory of

the future.

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EEWeb FEATUREEmbedded Developer

For those unfamiliar with the nature of this game-changing materials breakthrough, the name says it all. Carbon nanotubes are nanoscopic tubes of fullerene carbon in the family of carbon structures named after geodesic dome pioneer Buckminster Fuller, and as such for their general structure of a hollow space surrounded by a thin ‘net’ of carbon atoms. Some are round, but carbon nanotubes are tunnel-shaped and known for possessing almost preternatural strength and conductivity. Nantero does a good job of concisely summing up the basic idea behind the benefits of using the tiny carbon tubes in semiconductor devices on their website: “Considered one of the strongest materials known, with one CNT being just 1/50,000th the diameter of a human hair, these tiny cylinders are 50 times stronger than steel, half the density of aluminum, and have better

thermal and electrical conductivity properties than any other material scientists are aware of today.” In all honesty, it’s pretty exciting stuff.

What Schmergel did understand, he points out, was “the need for

ultra-fast, non-volatile memory” and that carbon nanotubes could be the

chance to push the envelope past the capabilities of common DRAM. “Based on that, I spent the next couple of months talking with

experts, professors, and so on, and did enough research to know that I

wanted to pursue this technology.” And so, in 2001, Nantero was brought to life to do just that. Today, the company’s nearly 200 granted US patents and pending make it clear that it hasn’t been in vain.

Though Schmergel pointed out that it was a bit of a slow road for Nantero at first, he acknowledges wisely that, as things have always gone in the field, truly innovative semiconductor devices “take many years to develop and get into production.” He remembered that, “for the first few years, we were really focused on small-scale lab work to demonstrate the performance of the memory and to show that it is low-power enough.” In the first stages, carbon nanotubes are grown from iron nanoparticles as a catalyst. To make things work as best as possible in their unique applications, Nantero also had to figure out how to actually make the carbon nanotube material compatible with existing technology. “That led to some intensive work and we hired some of the world’s top carbon nanotube experts,” Schmergel explained, “and now, we are the only company that has managed to figure out how to purify carbon nanotubes to less than one part per billion of any contaminants.”

In a closer examination of what goes into creating these futuristic building blocks, Schmergel points out that “there are two definitions of ‘purity’: the one we use is what percent of carbon nanotubes is actually carbon, versus iron, nickel, cobalt, etc.” Nantero has come a long way in its relatively short lifespan to be able to create the purest form of nanotubes available in the industry. “A few years ago, our standard was less than ten parts-per-billion, but those requirements have gotten more stringent as we’ve scaled down to smaller nodes. Now it’s generally less

than one part-per-billion. We can achieve that.” The other definition of purity is what percentage of the nanotubes are semiconducting versus how many are metallic. This is something that Nantero’s designs don’t need to take into account, and it adds to the efficiency of their designs. “We actually don’t separate the semiconducting tubes from the metallic tubes. This is because we’re using them as nano-electromechanical memory. It actually doesn’t matter.”

The effectiveness of nanotube-based memory is also strongly rooted in the material’s downright Herculean strength. “In terms of endurance, nanotubes are 50 times stronger than steel, so moving them a nanometer back and forth will never wear them out,” Schmergel explained. Unlike other materials that wear out by changing their state a certain number of times, nanotubes don’t seem to suffer from the same degradation. “We have tested the nanotube switching cycles and have not witnessed any signs of them wearing out at all.”

Nantero’s NRAM designs have definite proven advantages, with their nanotube structures allowing them to be both as fast as and denser than standard DRAM. NRAM, which is short for Nano-RAM, is non-volatile, too, and has very low energy needs. Outlining some of the design’s other unique strengths, Schmergel related that “in terms of other memory, we feel we have a unique combination with very fast speeds and the ability to operate with a DDR4 interface, which a lot of other competitors cannot. We can scale

Carbon nanotubes are tunnel-shaped and known for

possessing almost preternatural strength and conductivity.

“...carbon nanotubes

could be the chance to push

the envelope past the

capabilities of common DRAM.”

MYLINK32

Embedded Developer

down to below 5nm, too, which is another unique characteristic of our memory. Our memory was originally conceived by Dr. Tom Rueckes as a 2-nanometer memory with just two nanotubes moving in and out of contact with each other. If anything, our big challenge was scaling up as opposed to scaling down!”

Another obvious advantage of nanotube-based memory is the ease of manufacture. Because it is a very simple structure and straightforward manufacturing process—“no steps that anyone is unfamiliar with”—manufacturers can expect to find higher yields at lower costs. With just a little deserved pride leaking out from an altogether humble and dedicated demeanor, Schmergel beamed that “the carbon nanotube material is also far stronger than any of the materials used in designs by our closest competitors, so that leads to much more robustness, higher endurance, and faster speed overall.”

For those interested more in the specific architecture at work with Nantero’s designs, we asked Schmergel what to expect. “We are working on single-layer as well as 3D multi-layer implementations, for even higher densities and lower costs. where we get to multiple layers which are less than 6FSquared. We have shown MLC in silicon as well, can have both multi-layer and MLC as well, since we have many nanotubes-per-bit and can create intermediate resistance states.”

It would certainly seem, to this amateur observer at least, that the discoveries of the advantages of carbon nanotube technology are blissfully far from being exhausted any time soon. It can only be fairly assumed that, through the demonstrative innovation of companies like Nantero, much has yet to be learned and gained from the awesome carbon nanotube.

Unlike other materials that wear out by changing their state a certain

number of times, nanotubes don’t seem to suffer from the

same degradation.

SEM image of the deposited film (or fabric) of crossed nanotubes that can be either touching or slightly separated depending on their position.

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