Electromigration Studies on 6 Solid Cu TSV (Via …...Menglu Li1, Prakash Periasamy2, K. N. Tu1, and Subramanian S. Iyer1 1 Center for Heterogeneous Integration and Performance Scaling,

Electromigration Studies on 6 �� Solid Cu TSV (Via last) in 32 nm SOI Technology

Prakash Periasamy1, Michael Iwatake2, Menglu Li3, Joyce Liu2, Troy Graves-Abe2, Thuy Tran Quinn2, Subramanian S. Iyer3

1 GLOBALFOUNDRIES INC, Malta, NY12020, 2 GLOBALFOUNDRIES INC, Hopewell Junction, NY12533 3 Center for Heterogeneous Integration and Performance Scaling, UCLA, Los Angeles, CA90024.

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IEEE 66th ECTC – Las Vegas, NV USA May 31 – June 3, 2016 Session 29. Paper 5. Prakash Periasamy

Outline

2

Background – Via Last TSV Integration

Problem Statement (What, Why and How?)

1

2

Experimental Details3

Results & Discussions4

Concluding Remarks5

ation

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Background: via-last TSV IntegrationNeed for via-last TSV integration

Elements/links of interest in this study

� TSV/Capture Level

� TSV itself

� TSV/Redistribution layer (RDL)

This study

6 µm solid Cu via-last TSV

What is the electromigration limited min/max. current for each of these links?

Iyer, Subramanian S. "Three-dimensional integration: An industry perspective." MRS Bulletin 40.03 (2015): 225-232

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Problem StatementWhat?

Why?

How?

� What is the electromigration limited min/max. current for the links comprising of TSV, TSV/Capture Level and TSV/GrindsideRDL?

� Maximize the current loading (within the existing design) per TSV and thereby reduce the number of TSVs per chip if possible

� Aid designers and package engineers with electromigration related guidelines

� By making each of the elements (TSV, Capture Level, GrindsideRDL) in the link as the weakest in properly designed electromigration test structure to gain failure distribution

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6 µm solid Cu TSV (not drawn to scale)

25 µm wide capture level landing pad

redistribution level landing pad25 µm wide

Experimental Details – Test Structures (TSV/Capture Level)(a) single finger

(b) five fingers

Link of interest: TSV/Capture level. All other links are design robust

Two variations: (a) Single capture level finger vs (b) Five fingers

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Experimental Details – High Current Electromigration Oven

1

2

3

4

Current range: ± 2 µA to 4 ATemperature: 60°C to 400°C

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Experimental Details – TSV RIE and Fill Process

TSV post Metallization

Cu seed

TaN/Ta

TSV post etch

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Results & Discussions – TSV/Capture Level

Popup failures (rapid rise in resistance) �� five parallel capture level fingers connecting two TSVs

10% failure criteria -> chip that exhibits 10% increase in resistance than the baseline resistance at stress temperature is classified as failed chip.

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Results & Discussions – Electromigration Performance (TSV/Capture Level)

� Single finger exhibits 10x times better EM performance than five fingers capture level

� Higher joule heating in five finger indicates a design influenced current crowding (intrinsic integrity of the link is robust)

� At lower stress current as that of single finger, five finger lasted with no faill till 2700 hrs

Joule heating extracted by TCR (temperature co-efficient of resistance) measurements

10ºC 2ºC

Stress current is 2.4x times higher for five fingers (300 vs 125 mA)

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Results & Discussions – Cross sectional Image (Single finger versus Five fingers)

Five Fingers

Single Finger

No significant degradation. Few voids at capture pad and TSV

No significant degradation. Voids at capture pad and capture level

single finger

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Experimental Details – Test Structures (TSV/RDL)

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Results & Discussion– Electromigration Performance (TSV/RDL)

� TSV/RDL structure EM performance equivalent to TSV/five finger capture level

� The failure criteria is aggressive and it only takes 0.05 ohms resistance increase to classify as a failure for this huge structure. The structure didn’t result in hard open

� Test done at lower current didn’t tail till 2700 hrs of stress

10ºC 2ºC Stress current range (300 to 750 mA)

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Results & Discussion– Cross-sectional Images (TSV/RDL)

TSV/RDL structure post EM performance is still intact. No significant degradation was observed

Showing robust TSV/Capture level

interface

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Experimental Details – Test Structures (TSV itself)

Link of interest: TSV. All other links are design robust

RDL only

Capture level only

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Experimental Details – Test Structures (TSV itself)

Good candidate to test in package form with C4s. Need a robust design to maintain TSV as the weakest link and uniform current distribution

(a) Wirebonds are not robust enough to test the TSV itself structure

(b) 1.5 mil diameter wirebonds fuse beyond 1 A for 5 parallel wires (250 mA/wire)

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Take Away Message/Concluding Remarks

Link of Interest

Experimental Condition CurrentLoading

Capability*

Stress Current

(mA)

Stress Temperature

(ºC)

Joule Heating

(ºC)

Electrical C/S Area

(µm2) TSV/Capture Level (Single Finger) 125 300 2 ~5 1A

TSV/Capture Level (Five Fingers) 300 300 10 ~12 >1A

TSV/Grindside RDL 300 300 Negligible ~20 >1A

TSV element by itself 540-1000 300 Negligible ~20 >>1A

* By passing electromigration targets comfortably. Parameters used in this calculation: 10KPOH, Activation Energy: 0.9 eV, Current Exponent=1.1, Operation condition = 100ºC, 1A, Lifetime=11.4 years

What is the electromigration limited min/max. current for the links comprising of TSV, Capture Level and Grindside RDL?

Integration Scheme is robust enough to handle 1A* and above

eating (ºC)

ElectC/S Ar

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Concluding Remarks� In the 6 µm solid Cu via-last integration scheme, current loading as high

as 1 A is demonstrated successfully

� Results indicate strong interaction of current crowding. EM intelligent design to route the TSVs in the device side and grind side RDL will result in current loading higher than 1A comfortably

� Improved structures and testing methodology needs to be derived to test the limitation of the TSV element itself by making other elements/links robust enough. >1 A stress current to 5 parallel wire bond wires had fused

17

Optimized Power Delivery for 3D IC Technology Using Grind Side

Redistribution Layers

Menglu Li1, Prakash Periasamy2, K. N. Tu1, and Subramanian S. Iyer1

1Center for Heterogeneous Integration and Performance Scaling, Henry Samueli School of Engineering and Applied ScienceUCLA, Los Angeles, CA 90024 2GLOBALFOUNDRIES INC, Malta, NY-12020Friday, June 3, 2016. Session 41: Student Interactive Presentations8:30 AM - 10:30 AM

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Acknowledgements

� One of the authors (Prakash P) sincerely thank Tim Sullivan (IBM, Retired) for his mentorship and structure concepts used in this study

� Authors also thank Carole Grass, Dinesh Badami, Henry Nye and Gary St Onge for their managerial support during this work

� Thanks to Daniel Berger for financially supporting the wire bonding activity

Thank You18

� Thanks to Hally McHugh and Chad Burke (GLOBALFOUNDRIES,BTV) for preparing the EM samples

� Thanks to GLOBALFOUNDRIES management and Technical Council for the opportunity to present this work

Sullivs used in t

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Documents

Electromigration Studies on 6 Solid Cu TSV (Via …...Menglu Li1, Prakash Periasamy2, K. N. Tu1, and Subramanian S. Iyer1 1 Center for Heterogeneous Integration and Performance Scaling,