electrodes PDP-5.pdf

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96 CHANNEL PLASMA DISPLAY PANEL DATA DRIVER

JUN . 2004.

Ver. 1.2

Prepared by: Jae il Byeon

[email protected]

S6PR001

Contents in this document are subject to change without notice. No part of this document may be reproduced or

transmitted in any form or by any means, electronic or mechanical, for any purpose, without the express written

permission of Samsung Electronics CO. Ltd.


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3/17

96 CH. PDP DATA DRIVER S6PR001 PRELIMINARY SPEC

3

CONTENTS

INTRODUCTION.......................................................................................................4FEATURES ...............................................................................................................4BLOCK DIAGRAM ...................................................................................................5PIN ASSIGNMENT ...................................................................................................6PIN DESCRIPTION ..................................................................................................7ABSOLUTE MAXIMUM RATINGS.........................................................................8RECOMMENDED OPERATION RATINGS...........................................................8DC CHARACTERISTICS.........................................................................................9AC TIMING REQUIREMENTS............................................................................. 10AC TIMING CHARACTERISTICS ....................................................................... 10AC TIMING DIAGRAM .......................................................................................... 11OPERATION DESCRIPTION............................................................................... 12

DATA BUS CONFIGURATION..........................................................................................................12INTERNAL FUNCTION DESCRIPTION............................................................................................13TEST CONFIGURATION....................................................................................................................14

PADS DIMENSIONS AND LOCATIONS ............................................................ 15


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S6PR001 PRELIMINARY SPEC 96 CH. PDP DATA DRIVER

4

INTRODUCTION

S6PR001 is a data driver for Plasma Display Panel (PDP). This device is designed in CDMOS high voltage

process technology. Using a 3 or 6bit wide data bus, it can control 96 high voltage-high current outputs.

S6PR001 is supplied with a separated 75V power output supply and a 5V logic supply. All control inputs are

CMOS and 3.3V logic levels compatible.

FEATURES

96 High Voltage Output Channels.

Absolute Maximum Supply Voltage = 95V.

Bi - directional Shift Register.

3.3V / 5V Flexible Logic Input.

40 / 30mA Source / Sink Output Mos.

50 / 50 mA Source / Sink Output Diode.

3 or 6 Bit Data Bus (40 MHz).

CDMOS Process.

Packaging Adapted To Customer Request.


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5

BLOCK DIAGRAM

Output Control Circuit

96 Ouput Buffer and Level Shifter

OUT1 OUT2 OUT95 OUT96

CLK

F/R

96 Bit Data Latch

16 Bit BI-directional Shift registerS / R06

S / R

96


S / R

95


S / R

94


S / R93


S / R

92


S / R

91

ModeControlCircuit

A4

A5

A6

A1

A2

A3

BS

POC

BLK

VPP

VSSP

STBVSSSUB

VCC

VSSLOG

Figure 1. Block Diagram


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6

PIN ASSIGNMENT

OUT96

OUT95

OUT94

OUT93

VSSP

VSSP

VPP

VPP

OUT1

OUT2

OUT3

OUT4

VSSP

VSSP

VPP

VPP

V

S

S

L

O

G

C

L

K

F

/

R

P

O

C

V

C

C

S

T

B

B

L

K

A

1

A

2

A

3

A

4

A

5

A

6

V

S

S

S

U

B

BS

V

S

S

L

O

G

O

U

T

4

1

O

U

T

4

2

O

U

T

4

3

O

U

T

4

4

O

U

T

4

5

O

U

T

4

6

O

U

T

4

7

O

U

T

4

8

O

U

T

4

9

O

U

T

5

0

O

U

T

5

1

O

U

T

5

2

O

U

T

5

3

O

U

T

5

4

O

U

T

5

5

O

U

T

5

6

OUT57

OUT58

OUT59

OUT60

OUT40

OUT39

OUT38

OUT37

(0,0)

Y

X

Figure 2. Pin Assignment


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7

PIN DESCRIPTION

Symbol Pin NameI /

O

Description

OUT

(01 to 96)PDP Drive output O

Power Output

The output signals change in synchronization with the rising

edge of latch clock input, STB.

The amplitude of the driver output is VPP - VSSP.

F/R_

Shift direction control input IWhen F/R

_

= L, An OUT1 OUT96, Forward Shift

When F/R_

= H, An OUT96 OUT1, Reverse Shift

CLK Shift clock input I

Clock of data shift register

The shift register operates in synchronization with the rising

edge of this input

BS Bus width selection input I This input selects the input data width between 3Bit and 6Bit

STB Strobe input I This input transfers the data of shift register to the output latch.

BLKOutput Blank control input I

This input controls the state of the driver outputs.

This pin is prior to the data of shift register and POC signal

When BLK = L, the driver output is fixed to VSSP.

When BLK = H, the driver output is VPP or VSSP

corresponding to the data and the state of POC.

POC Power output control input I

This input controls the state of the driver outputs.

If the state of BLK is High,

When POC = L, the driver output is fixed to VPP

When POC = H, the driver output is VPP or VSSP

corresponding to the data.

VSSP High voltage output ground I Ground of power outputs.

VSSLOG Logic ground I Logic ground.

VSSSUB Substrate ground I Substrate ground.

VCC Logic power supply I 5V logic supply.

VPP Drive power supply I High voltage supply of power outputs.

IN(A1-A6) Data input I Shift register input for BS=L

IN(A1-A3) Data input I Shift register input for BS=H

OUT(A4-A6) Data output O Shift register output for BS=H


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8

ABSOLUTE MAXIMUM RATINGS

Table 1. Absolute Maximum Ratings

Parameter Symbol Ratings Unit

Logic power supply Vcc - 0.3 to 7.0 V

Driver power supply Vpp - 0.3 to 95.0 V

Input voltage Vin - 0.3 to VCC + 0.3 V

Driver output current (Note1) Ipout -50 / 35 mA

Output power voltage range Vout - 0.3 to 95.0 V

Maximum junction temperature Tjmax 125 C

Storage temperature Tstg - 50 to 150 C

NOTES:

1. Through one power output for all power outputs (see Figure 4. Test configuration page14) with junction temperature

lower than or equal to Tjmax

RECOMMENDED OPERATION RATINGS

Table 2. Recommended Operation Ratings

(Vcc = 5V, Vpp = 75V, Vssp = 0V, Vss = 0V, Tamb = 25C, FCLK = 40MHz, unless otherwise specified)

Parameter Symbol Min. Typ. Max. Unit Pin

Logic supply voltage Vcc 4.5 5 5.5 V

Power output supply voltage mode Vpp 30 - 75 V

Logic supply static current (Note 2) Iccs - 50 100 uA

Logic supply dynamic current

(FCLK = 20MHz) (Note 3)Iccd - 5 10 mA

Power output supply current

(steady outputs)Ipps - 5 10 uA

Power

(Vpp,Vcc)

NOTES:

2. Logic input levels compatible with 5V CMOS logic.3. All data inputs are commuted at 10MHz.


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9

DC CHARACTERISTICS

Table 3. DC Characteristics

(Vcc = 5V, Vpp = 70V, Vssp = 0V, Vss = 0V, Tamb = 25C, FCLK = 40MHz, unless otherwise specified)

Parameter Symbol Min. Typ. Max. Unit Pin

Power output high level (voltage drop versus Vpp)

@ Ipouth = -20mA and Vpp = 70VVpouth - 7.5 14

Power output low level

@ Ipoutl = 20 mAVpoutl - 5 11

V

Output diode voltage drop

@ Idouth = 30mA (Note 4)Vdouth 1 2 V

Output diode voltage drop

@ Idoutl = -30mA (Note 4)Vdoutl -2 -1 -

Output

(OUT1

to

OUT96)

Input high level Vih 2.0 - -

Input low level Vil - - 0.9

High level input current (Vih >= 2.0V) Iih - - 5

Low level input current (Vil = 0V) Iil - - 5uA

Input capacitance (Note 5) Cin - - 15 pF

Input

(CLK,

BS,

STB,

POC,

BLK,

F/R_

, A1

to A6

NOTES:

4. See Figure4. Test configuration page 14

5. This parameter is not tested on the part.


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10

AC TIMING REQUIREMENTS

Table 4. AC Timing Requirement

(Tamb = - 20 to 85 C, VCC = 4.5 to 5.5 v, input signal2 max leading edge & trailing edge(tr,tf) =5nS)

Parameter Symbol Min. Typ. Max. Unit Remark

Data clock period tCLK 25 - -

Duration of CLK pulse at high level tWHCLK 10 - -

Duration of CLK pulse at low level tWLCLK 10 - -

Set-up time of data input before low to high clock transition tSDAT 5 - -

Hold-time of data input after low to high clock transition tHDAT 5 - -

Hold-time of STB after low to high clock transition tHSTB 5 - -

STB low level pulse duration tSTB 10 - -STB set-up time before CLK rise tSSTB 5 - -

nS

-

AC TIMING CHARACTERISTICS

Table 5. AC Timing Characteristics

(Vcc = 5V, Vpp = 75V, Vssp = 0V, Vsssub = 0V, Vsslog = 0V, Tamb =25 C, FCLK = 40MHz)

Parameter Symbol Min. Typ. Max. Unit Remark

Delay of power output change after CLK transition

- high to low

- low to high

tPHL1

tPLH1

-

-

-

-

100

100

Delay of power output change after STB transition

- high to low

- low to high

tPHL2

tPLH2

-

-

-

-

95

95

Delay of power output change after BLK, POC transition

- high to low

- low to high

tPHL3

tPLH3

-

-

-

-

90

90

Delay of logic output A4-A6 data after CLK transition

- high to low- low to high

tPHL4

tPLH4

-

-

-

-

100

100

Power output rise time (Note 6) tROUT 50 - 200

Power output fall time (Note 6) tFOUT 50 - 200

nS

Vilmax =

0.2Vcc

Vihmin =

0.8Vcc

NOTES:

6. One output among 96, loading capacitor CL=50pF, other outputs at low level.


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11

AC TIMING DIAGRAM

tCLK

tWHCLK tWLCLK

tSDAT tHDAT

tHSTBtSTB

tSSTB

tPHL2

tPLH2

tPHL1

tPLH1

tPHL3 tPLH3

50% 50% 50%

50% 50%

50% 50%

50% 50%

90%

10%

90%

10%

CLK

AINPUT

STB

OUTn

BLK

(POC="L")

OUTn

tFOUT tROUT

90%

10% 10%

90%

LOGIC OUT

(A4- A6)

tPHL4 tPHL4

"1"

"0"

"1"

"0"

"1"

"0"

"1"

"0"

"1"

"0"

"1"

"0"

"1"

"0"

Figure 3. AC Timing Diagram


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12

OPERATION DESCRIPTION

DATA BUS CONFIGURATION

This table describes the position of the first data sampled by the first rising edge of the CLK signal.

For the first configuration described in the below table, (BS =L and F/R_

= L), data on A1 bus sampled by the

1st

clock pulse is applied on Output1. After 16 clock pulses this data will be shifted to Output91.

The shifting relationship between A1 and A6 data is as follows:

Table 6. The relationship between A1 and A6 data corresponding to the BS and F/R_

Data shiftBS F/R

_

INCLK 01 02 03 04 05 06 - 11 12 13 14 15 16

L L

A1

A2

A3

A4

A5

A6

Out

Out

Out

Out

Out

Out

01

02

03

04

05

06

07

08

09

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

- 61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

For

L H

A1

A2

A3

A4

A5

A6

Out

Out

Out

Out

Out

Out

91

92

93

94

95

96

85

86

87

88

89

90

79

80

81

82

83

84

73

74

75

76

77

78

67

68

69

70

71

72

61

62

63

64

65

66

- 31

32

33

34

35

36

25

26

27

28

29

30

19

20

21

22

23

24

13

14

15

16

17

18

07

08

09

10

11

12

01

02

03

04

05

06

Rev

Data shiftBS F/R

_

INCLK 01 02 03 04 05 06 - 27 28 29 30 31 32

H L

A1

A2

A3

Out

Out

Out

01

02

03

04

05

06

07

08

09

10

11

12

13

14

15

16

17

18

- 79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

For

H H

A1

A2A3

Out

OutOut

94

9596

91

9293

88

8990

85

8687

82

8384

79

8081

- 16

1718

13

1415

10

1112

07

0809

04

0506

01

0203

Rev


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13

INTERNAL FUNCTION DESCRIPTION

S6PR001 includes all the logic and power circuits necessary to drive column electrodes of a Plasma Display Panel

(P.D.P). Binary values of each pixel of a selected line are loaded into the shift register by a 6bit wide (A1 - A6) databus depending on the configuration of the BS input pin. Data are shifted at each rising edge of the CLK clock.

The forward / reverse (F/R_

) input is used to select the direction of the shift register. The BS input is used to configure

the shift register either in 3 X 32 bits or in 6 X 16 bits.

In case of 3bit mode (BS = H), A1, A2 and A3 pins are used. The 3 shift registers are loaded with 32 clock pulses.

A4 to A6 pins are used as output pin for cascade connection. The maximum frequency of the shift clock is 40MHz.

This leads to an equivalent 240MHz serial shift register for a 6 X 16 bits shift register configuration.

When the STB signal is Low, data are transferred from the shift register to the latch and power output stages.

All the output data are kept memorized and held in the latch stage when the latch input STB is pulled high.

Vsssub and Vsslog must be connected as close as possible to the logical reference ground of the application.S6PR001 is supplied with a 5volt power supply. All the logic inputs can be driven either by 5V CMOS logic, or by

3.3V CMOS logic.

Table 7. Shift register truth table

Input pin status Shift register function

BS F/R_

CLK Output Q

X L Rising edge Forward shift

X L H or L Steady

X H Rising edge Reverse shiftX H H or L Steady

H X X 3 bits shift register

L X X 6 bits shift register

Table 8. Power output truth table

Qn STB BLK POC Driver Output Comments

X X L X All L Output at low level

X X H L All H Output at high level

X H H H Qn Data latched

L L H H L Data copied

H L H H H Data copied


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14

TEST CONFIGURATION

Vpp=Vssp

Vssp

VdouthI douth

Vdoutl I doutl

Vssp

Vpp=Vssp

Output sinking current as positive value, sourcing current as negative value

Figure 4. Test circuit configuration for the Power Output Diode


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15

PADS DIMENSIONS AND LOCATIONS

The reference is the center of the die (X=0, Y=0)

Name Center:X Center:Y Size:X Size:Y Name Center:X Center:Y Size:X Size:Y

OUT57 -892.67 1950.79 90 75 OUT77 -892.67 -113.01 90 75

OUT58 -892.67 1847.60 90 75 OUT78 -892.67 -216.20 90 75

OUT59 -892.67 1744.41 90 75 OUT79 -892.67 -319.39 90 75

OUT60 -892.67 1641.22 90 75 OUT80 -892.67 -422.58 90 75

OUT61 -892.67 1538.03 90 75 OUT81 -892.67 -525.77 90 75

OUT62 -892.67 1434.84 90 75 OUT82 -892.67 -628.96 90 75

OUT63 -892.67 1331.65 90 75 OUT83 -892.67 -732.15 90 75

OUT64 -892.67 1228.46 90 75 OUT84 -892.67 -835.34 90 75

OUT65 -892.67 1125.27 90 75 OUT85 -892.67 -938.53 90 75

OUT66 -892.67 1022.08 90 75 OUT86 -892.67 -1041.72 90 75

OUT67 -892.67 918.89 90 75 OUT87 -892.67 -1144.91 90 75

OUT68 -892.67 815.70 90 75 OUT88 -892.67 -1248.10 90 75

OUT69 -892.67 712.51 90 75 OUT89 -892.67 -1351.29 90 75

OUT70 -892.67 609.32 90 75 OUT90 -892.67 -1454.48 90 75

OUT71 -892.67 506.13 90 75 OUT91 -892.67 -1557.67 90 75

OUT72 -892.67 402.94 90 75 OUT92 -892.67 -1660.86 90 75

OUT73 -892.67 299.75 90 75 OUT93 -892.67 -1764.05 90 75

OUT74 -892.67 196.56 90 75 OUT94 -892.67 -1867.24 90 75

OUT75 -892.67 93.37 90 75 OUT95 -892.67 -1970.43 90 75

OUT76 -892.67 -9.82 90 75 OUT96 -892.67 -2073.62 90 75


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16


VPP -892.67 -2176.81 90 75 VSSP 892.67 -2486.38 90 75

VPP -892.67 -2280.00 90 75 VSSP 892.67 -2383.19 90 75

VSSP -892.67 -2383.19 90 75 VPP 892.67 -2280.00 90 75

VSSP -892.67 -2486.38 90 75 VPP 892.67 -2176.81 90 75

VSSLOG -773.54 -2701.05 75 90 OUT1 892.67 -2073.62 90 75

BS -670.35 -2701.05 75 90 OUT2 892.67 -1970.43 90 75

VSSSUB -567.16 -2701.05 75 90 OUT3 892.67 -1867.24 90 75

A6 -463.97 -2701.05 75 90 OUT4 892.67 -1764.05 90 75

A5 -360.78 -2701.05 75 90 OUT5 892.67 -1660.86 90 75

A4 -257.59 -2701.05 75 90 OUT6 892.67 -1557.67 90 75

A3 -154.40 -2701.05 75 90 OUT7 892.67 -1454.48 90 75

A2 -51.21 -2701.05 75 90 OUT8 892.67 -1351.29 90 75

A1 51.98 -2701.05 75 90 OUT9 892.67 -1248.10 90 75

BLK 155.17 -2701.05 75 90 OUT10 892.67 -1144.91 90 75

STB 258.36 -2701.05 75 90 OUT11 892.67 -1041.72 90 75

VCC 361.55 -2701.05 75 90 OUT12 892.67 -938.53 90 75

POC 464.74 -2701.05 75 90 OUT13 892.67 -835.34 90 75

F/R_

567.93 -2701.05 75 90 OUT14 892.67 -732.15 90 75

CLK 671.12 -2701.05 75 90 OUT15 892.67 -628.96 90 75

VSSLOG 774.31 -2701.05 75 90 OUT16 892.67 -525.77 90 75


17/17


17


OUT17 892.67 -422.58 90 75 OUT37 892.67 1641.22 90 75

OUT18 892.67 -319.39 90 75 OUT38 892.67 1744.41 90 75

OUT19 892.67 -216.20 90 75 OUT39 892.67 1847.60 90 75

OUT20 892.67 -113.01 90 75 OUT40 892.67 1950.79 90 75

OUT21 892.67 -9.82 90 75 OUT41 773.46 2700.96 75 90

OUT22 892.67 93.37 90 75 OUT42 670.27 2700.96 75 90

OUT23 892.67 196.56 90 75 OUT43 567.08 2700.96 75 90

OUT24 892.67 299.75 90 75 OUT44 463.89 2700.96 75 90

OUT25 892.67 402.94 90 75 OUT45 360.70 2700.96 75 90

OUT26 892.67 506.13 90 75 OUT46 257.51 2700.96 75 90

OUT27 892.67 609.32 90 75 OUT47 154.32 2700.96 75 90

OUT28 892.67 712.51 90 75 OUT48 51.13 2700.96 75 90

OUT29 892.67 815.70 90 75 OUT49 -52.06 2700.96 75 90

OUT30 892.67 918.89 90 75 OUT50 -155.25 2700.96 75 90

OUT31 892.67 1022.08 90 75 OUT51 -258.44 2700.96 75 90

OUT32 892.67 1125.27 90 75 OUT52 -361.63 2700.96 75 90

OUT33 892.67 1228.46 90 75 OUT53 -464.82 2700.96 75 90

OUT34 892.67 1331.65 90 75 OUT54 -568.01 2700.96 75 90

OUT35 892.67 1434.84 90 75 OUT55 -671.20 2700.96 75 90

OUT36 892.67 1538.03 90 75 OUT56 -774.48 2700.96 75 90

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electrodes PDP-5.pdf