Electro-Thermal Simulations and Measurements of …14846/FULLTEXT01.pdfElectro-Thermal Simulations and Measurements of Silicon Carbide Power Transistors A dissertation submitted to

ISRN KTH/EKT/FR-2004/7-SE

Electro-Thermal Simulations and Measurements of Silicon Carbide Power Transistors

Doctoral Thesis

by Wei Liu

Stockholm, 2004 Sweden

Laboratory of Solid State Electronics (SSD)

Department of Microelectronics and Information Technology (IMIT) Royal Institute of Technology (KTH)

Electro-Thermal Simulations and Measurements of Silicon Carbide Power Transistors

A dissertation submitted to the Royal Institute of Technology, Stockholm, Sweden, in partial fulfillment of the requirements for the degree of Doctor of Technology. 2004 Wei Liu Department of Microelectronics and Information Technology KTH, Royal Institute of Technology Electrum 229 SE-16440 Kista Sweden

ISRN KTH/EKT/FR-2004/7-SE ISSN 1650-8599 TRITA-EKT Forskningsrapport 2004:7

Printed in 100 copies by Universitetsservice USAB, Stockholm 2004

Liu, Wei: Electro-Thermal Simulations and Measurements of Silicon Carbide Power Transistors, ISRN KTH/EKT/FR-2004/7-SE, Department of Microelectronics and Information Technology (IMIT), Royal Institute of Technology (KTH), Stockholm 2004.

Abstract

The temperature dependent electrical characteristics of silicon carbide power transistors – 4H-SiC metal semiconductor field-effect transistors (MESFETs) and 4H-SiC bipolar junction transistors (BJTs) have been investigated through simulation and experimental approaches. Junction temperatures and temperature distributions in devices under large power densities have been estimated.

The DC and RF performance of 4H-SiC RF Power MESFETs have been studied through two-dimensional electro-thermal simulations using commercial software MEDICI and ISE. The simulated characteristics of the transistors were compared with the measurement results. Performance degradation of transistors under self-heating and high operating temperatures have been analyzed in terms of gate and drain characteristics, power density, high frequency current gain and power gain. 3D thermal simulations have been performed for single and multi-finger MESFETs and the simulated junction temperatures and temperature profiles were compared with the results from electro-thermal simulations. The reduction in drain current caused by self-heating was found to be more prominent for transistors with more fingers and it imposes a limitation on both the output power and the power density (in W/mm) of multi-fingered large area devices. Thermal issues for design of high power multi-fingered SiC MESFETs were also investigated. A couple of useful ways to reduce the self-heating effects were discussed. Trap-induced performance instabilities of the devices were analyzed by carrying out DC, transient, and pulse measurements at room and elevated temperatures.

Electrical characteristics of 4H-SiC BJTs have been measured. A reduction in current gain at elevated temperatures was observed. Based on the collector current-voltage diagram measured at three different ambient temperatures the junction temperature was extracted using the assumption that the current gain only depends on the temperature. Temperature measurements have been carried out for SiC BJTs. Thermal images of a device under operation were recorded using an infrared camera. 3D thermal simulations were conducted using FEMLAB. Both the simulations and the measurement showed a significant temperature increase in the vicinity of the device when operated at high power densities, thus causing the decrease of the DC current gain. The junction temperatures obtained from the thermal imaging, simulation and extraction agree well.

Keywords: silicon carbide, power device, metal semiconductor field-effect transistor, bipolar junction transistor, electro-thermal simulation, thermal simulation, temperature, self-heating, DC measurement, HF measurement, s-parameter, traps, thermal image.

i

Table of Contents

Table of Contents ......................................................................................................................i

List of Papers...........................................................................................................................iii

Author’s Contribution.............................................................................................................v

Acknowledgements .................................................................................................................vi

List of Symbols .......................................................................................................................vii

1 Introduction and State of the Art .................................................................................1

2 Electro-Thermal Investigation of Silicon Carbide RF Power MESFETs.................5

2.1 Device description .....................................................................................................5

2.2 Device simulation models..........................................................................................6

2.2.1 Basic equations ..................................................................................................6

2.2.2 Recombination models.......................................................................................7

2.2.3 Mobility models .................................................................................................8

2.2.4 Incomplete ionization of impurities .................................................................10

2.2.5 Impact ionization .............................................................................................11

2.2.6 Bandgap and effective density of states...........................................................11

2.2.7 Lattice heating models .....................................................................................12

2.3 Isothermal DC and HF simulations..........................................................................13

2.3.1 DC simulations.................................................................................................13

2.3.2 HF simulations .................................................................................................15

2.4 Self-heating effects ..................................................................................................18

2.5 DC and HF measurements .......................................................................................20

2.6 Comparison of simulations and measurements........................................................22

2.7 Trap-induced performance instabilities of SiC MESFETs ......................................24

ii ii

2.7.1 Substrate traps..................................................................................................24

2.7.2 Surface traps.....................................................................................................26

2.8 Thermal issues for SiC MESFET design.................................................................30

2.8.1 Comparison of thermal simulations and electro-thermal simulations .............30

2.8.2 Electro-thermal co-design issues for multi-fingered SiC MESFETs...............32

2.8.3 Thermal design issues for commercial SiC MESFETs....................................36

3 Electro-Thermal Investigation of Silicon Carbide Power BJTs ..............................43

3.1 Device description ...................................................................................................43

3.2 DC performance.......................................................................................................44

3.3 Extraction of junction temperature ..........................................................................44

3.4 Chip level thermal simulations ................................................................................46

3.5 Chip temperature measurements..............................................................................47

3.6 Comparison of simulations and measurements........................................................48

4 Summary and Future Work........................................................................................51

References...............................................................................................................................53

Appendix Material properties and parameters used in device simulations ....................59

iii

List of Papers

I. Thermal -Issues for Design of High Power SiC MESFETs

W. Liu, C.-M. Zetterling, M. Östling

Proc. 6th IEEE Int. Symp. on High Density Packaging and Component Failure Analysis in Electronics Manufacturing (HDP’ 04), Shanghai, China, Jun. 2004, pp. 331-335.

II. Self-Heating Study of Multi-Fingered SiC Power MESFETs


Submitted to Solid State Electronics

III. Trap-Induced Performance Instability of RF SiC Power MESFETs Evaluated

at up to 300 ˚C.

W. Liu, M. Domeij, C.-M. Zetterling, M. Östling, J. Eriksson, N. Rorsman, and H. Zirath


IV. High Frequency Measurements and Simulations of SiC MESFETs up to 250 ˚C.

W. Liu, C.-M. Zetterling, M. Östling, J. Eriksson, N. Rorsman, and H. Zirath

Mater. Sci. Forum, Vol. 457-460, pp. 1209-1212, 2003.

V. Electro-Thermal Simulations and Measurements of Silicon Carbide Bipolar Transistors.

W. Liu, E. Danielsson, C.-M. Zetterling, M. Östling

Mater. Sci. Forum, Vol. 433-436, pp. 781-784, 2002.

VI. Electro-Thermal Investigation of High Power Silicon Carbide Transistors

W. Liu, E. Danielsson, C.-M Zetterling and M. Östling

Proc. 4th IEEE Int. Symp. on High Density Packaging and Component Failure Analysis in Electronics Manufacturing (HDP’ 02), Shanghai, China, Jun. 2002, pp. 175-179.

iv iv

Related papers not included in the thesis

Self-Heating Investigation on 4H-SiC Power BJTs

W. Liu, E. Danielsson, C.-M. Zetterling, M. Östling


Characterization of SiC HF-Power MESFETs up to 250 ˚C

W. Liu, C.-M. Zetterling, M. Östling, J. Eriksson, N. Rorsman, and H. Zirath

Presented at GigaHertz 2003, Linköping, Sweden, Nov. 2003.

Challenges for High Temperature Silicon Carbide Electronics (Invited)

C.-M. Zetterling, S.-M. Koo, E. Danielsson, W. Liu, S.-K. Lee, M. Domeij, H. S. Lee, and M. Östling

Presented at MRS 2003 Spring Meeting and published in Mater. Res. Soc. Symp. Proc.

Measurements and Simulations of Self-heating and Switching with 4H-SiC Power BJTs

M. Domeij, E. Danielsson, W. Liu, U. Zimmermann, C-M. Zetterling, M. Östling

Presented at ISPSD, Cambridge, UK, Apr. 2003.

Optical and Electrical Characterization, and Physical Device Simulation of High Voltage High Temperature Silicon Carbide Bipolar Transistors

E. Danielsson, C.-M. Zetterling, W. Liu, and Mikael Östling

Presented at First Scandinavian Conference on Thermal Management of Electronics (ScandTherm), Stockholm, Sweden, Jun. 2002.

Electrothermal Simulation of 4H-SiC RF Power MESFETs


Presented at GigaHertz 2001, Lund, Sweden, Nov. 2001.

v

Author’s Contribution

The author’s contribution to the work in papers I-VI is as follows:

• In paper I, I built the electro-thermal and thermal simulation models, conducted the simulations using ISE and FEMLAB, examined different finger and unit cell layouts, stated the ways to reduce self-heating effects and improve device performance. I also wrote the manuscript.

• In paper II, I built the electro-thermal and thermal simulation models, conducted the simulations using ISE and FEMLAB, compared the electro-thermal simulation results using ISE with thermal results using FEMLAB. I also performed the optimisation of finger layouts for multi-fingered devices, discussed useful methods to minimize the self-heating effects and wrote the manuscript.

• In paper III, I performed the DC and pulse measurements for characterizing the performance instabilities caused by traps located in the semi-insulating substrate and the un-gated surface of the devices. I also wrote the manuscript.

• In paper IV, I performed the DC and HF measurements at room and elevated temperatures, built the simulation models for the SiC MESFETs and did the simulations using ISE. I also analyzed the results and wrote the manuscript.

• In paper V, I built the thermal simulation model, conducted the simulations using FEMLAB, completed the comparison of simulation results with the measurement results from thermal imaging using infrared camera, and wrote the manuscript.

• In paper VI, I built the electro-thermal simulation models for SiC MESFETs, performed the simulations on the MESFETs using MEDICI, analyzed the effects of elevated operating temperature and self-heating on the device performance. I also conducted the thermal simulations on SiC BJTs using FEMLAB, compared the simulated temperature profiles with the thermal images captured by an infrared camera and the extracted junction temperatures. I also wrote the manuscript.

vi vi

Acknowledgements

First I would like to thank my supervisors Prof. Mikael Östling and Dr. Carl-Mikael Zetterling for introducing me to the fantastic world of electronics and for supporting me all the way in my research work.

Great thanks go to Erik Danielsson for his continuous help in almost every aspect of the research, to Martin Domeij for teaching me how to work with the unix system and MEDICI at the beginning of my work and for helping me to do the pulse measurements, to Gunnar Malm, Martin Sanden and Uwe Zimmermann for helping me with the HF measurements, to all the members in the SiC group for the useful discussions and the time we shared at conferences.

I would also like to express my gratefulness to Ann-Chatrin Lindgren for her friendship and encouragement and to Zandra Lundberg for her great help with matters outside the research.

Thanks to all my colleagues at EKT for the happy time we shared at coffee breaks, lunches, dissertation parties, and in seminars.

Thanks also go to Dr. Joakim Eriksson, Dr. Niklas Rorsman and Prof. Herbert Zirath for providing the SiC MESFETs for the measurements.

Finally I would like to thank Swedish Foundation for Strategic Research (SSF) for the financial support through the EPROPER program and the project leader Dr. Lirong Zheng for his creative ideas and help in the program.

vii

List of Symbols Symbols Description Unit

A Area cm2

a Channel thickness cm

c Specific heat capacitance W/g⋅K

Dn Electron diffusivity cm2/s

Dp Hole diffusivity cm2/s

E Electric field V/cm

En Electric field for electrons V/cm

Ep Electric field for holes V/cm

E||,n Parallel electric field for electrons V/cm

E||,p Parallel electric field for holes V/cm

EA Acceptor energy level eV

ED Donor energy level eV

EFn Electron Fermi energy level eV

EFp Hole Fermi energy level eV

Eg Bandgap energy eV

Ei Fermi energy level eV

fmax Maximum frequency of oscillation Hz

fT Cut-off frequency Hz

gm Transconductance A/V

H Volumetric heat source W/cm3

|H21| Small signal current gain dB

h Planck’s constant (= 6.63×10-34 J⋅s) J⋅s

IB Base current A

IC Collector current A

Id Drain current A

Isat Saturation current A

viii viii

Symbols Description Unit

Jn Electron current density A/cm2

Jp Hole current density A/cm2

k Boltzmann’s constant (= 1.38×10-23 J/K) J/K

MAG Maximum available gain dB

MSG Maximum stable gain dB

Na Acceptor concentration #/cm3

Na+ Ionized acceptor concentration #/cm3

NC Effective conduction band density of state #/cm3

Nd Donor concentration #/cm3

Nd+ Ionized donor concentration #/cm3

NV Effective valence band density of state #/cm3

Ntotal Total impurity concentration #/cm3

n Electron concentration #/cm3

nie Effective intrinsic carrier concentration #/cm3

p Hole concentration #/cm3

Pdiss Dissipated power W

Pmax Maximum power density per unit gate width W/cm

q Electronic charge (= 1.6×10-19 C) C

qth Heat flux W/cm2

Rth Thermal resistance K/W

S11 S-parameter none




T Temperature K

Tamb Ambient temperature K

Tj Junction temperature K

t Time s

U Mason Unilateral Gain dB

ix

Symbols Description Unit

UAuger Auger recombination rate #/cm3⋅s

Un Electron recombination rate #/cm3⋅s

USRH Shockley-Read-Hall recombination rate #/cm3⋅s

Up Hole recombination rate #/cm3⋅s

Vbi Built-in potential V

Vbreak Breakdown voltage V

VCE Collector-emitter voltage V

Vd Drain voltage V

Vg Gate voltage V

Vknee Knee voltage V

Vp Pinch-off voltage V

VT Threshold voltage V

vnsat Electron saturation velocity cm/s

vpsat Hole saturation velocity cm/s

αn,ii Electron ionization coefficient cm-1

αp,ii Hole ionization coefficient cm-1

β DC current gain none

λ Thermal conductivity W/cm⋅K

µn Electron mobility cm2/V⋅s

µp Hole mobility cm2/V⋅s

µs,n Low field electron mobility cm2/V⋅s

µs,p Low field hole mobility cm2/V⋅s

ρ Mass density g/cm3

ρs Charge density C/cm3

τn Electron lifetime s

τp Hole lifetime s

χ Electron affinity eV

ψ Potential V

1

1 Introduction and State of the Art

Silicon carbide has become one of the most promising materials for high voltage, high power, high frequency, and high temperature device application due to the combination of the unique material properties and the relatively mature material growth and device fabrication technology [1-5]. These properties include wider bandgap, higher breakdown electric field, higher saturated electron drift velocity, and higher thermal conductivity compared with Si. The wider bandgap (3.25 eV for 4H-SiC) of the material makes it possible for SiC devices to work at extremely high temperatures without suffering from intrinsic conduction effects. The eight times higher breakdown electric field (2.2x106 V/cm) allows SiC transistors to operate at higher voltages, resulting in higher power density. The higher saturated electron drift velocity (2.0x107 cm/s) means both higher power and higher frequency. In addition, silicon carbide's much higher thermal conductivity (3.5-5 W/cm·K at room temperature) makes it easier to transfer heat to the environment, which in turn allows the realization of devices with higher power densities.

There are three SiC polytypes 3C, 4H and 6H, which are suitable for device fabrication. 4H-SiC seems to be the most interesting one for the time being due to its higher mobility [6]. A large part of the research work on SiC transistors is for the 4H polytype.

Two types of SiC power transistors are discussed here. One is the 4H-SiC metal semiconductor field effect transistor (MESFET) for RF power applications, and the other is the 4H-SiC bipolar junction transistor (BJT) for high power, high voltage switch applications.

MESFETs made of SiC have high power density per unit gate periphery (measured in W/mm) and high input and output impedances that are easy to match. Amplifiers built with these devices have less loss, are more broadband (since the matching circuits are lower Q), and are less sensitive to manufacturing and component tolerances. Continuous experimental [7-13] and simulation work [14-16] has been conducted to investigate the potential of the RF power performances of MESFETs. New techniques such as the recessed gate [16], the semi-insulating substrate [17], the very small gate length [18] and “buried-channel” structure [19] make this device available for operation under higher frequency and voltage. The recent innovation of method of growing ultrahigh-quality silicon carbide single crystals [20] will surely accelerate the speed of SiC power device into the market. The potential of SiC MESFET technology has been demonstrated by a number of groups [7, 18, 19, 21-23]. The highest SiC MESFET power density achieved using conducting substrate is 3.3 W/mm with Vd = 50 V at a frequency of 850 MHz [24]. Using a semi-insulating substrate, 5.2 W/mm has been achieved with Vd = 50 V at a frequency of 3.5 GHz [22]. The highest total power reported [8] was 80 W CW output power with 31% power added efficiency (PAE) at 3.1 GHz, from a single MESFET device with 48 mm of gate periphery operated in hybrid circuit. The highest cut-off frequency and maximum frequency of oscillation ever achieved are 22 GHz and 50 GHz [25] respectively. Simulation studies demonstrated a possible maximum frequency of oscillation as high as 100 GHz, and a theoretical maximum power density in excess of 20 W/mm [22]. The first commercial SiC RF MESFET was produced by CREE Inc. [26] in 2000, and now CREE is able to manufacture its second generation of 48 V SiC MESFETs with 10 W and 60 W output power. Both transistors have an operating frequency of 2.7GHz, and an operating voltage as

Wei Liu 1 Introduction and State of the Art

2 2

high as 28-48 V. The 10 W MESFET has a power gain of 15 dB and the 60 W device has a gain of 13 dB.

Although great progresses have been made towards fabricating SiC MESFETs with very good performance, the current state of the art of SiC device technology remains developmental [19]. Traps in the device structure are the biggest problem so far which prevents the realization of reliable devices in SiC [19, 27-30]. High purity semi-insulating substrate and better surface passivation technique will help to solve these problems.

Compared to SiC MESFETs there are fewer publications presented on SiC BJTs mainly due to the complicated device fabrication process. But recently, there are significant advances on 4H-SiC BJTs. The reported SiC BJTs are mainly used as power-switching devices [31-40], though there are some articles about SiC BJTs for amplifier applications [41-43]. As a switch device the SiC BJT has the advantage of high blocking voltage, high current density, and low on-resistance. High voltage npn BJTs in 4H-SiC were demonstrated by CREE [33]. The BJTs were able to block 1800 V in common emitter configuration and showed a peak current gain of 20 and an on-resistance of 10.8 mΩ⋅cm2. The active device area was 0.014 cm2 and the on-current was about 2.7 A. Larger area BJTs with an active area of 0.0665 cm2 were also fabricated by CREE [38]. A blocking voltage of 1300 V and an on-current as high as 17 A was obtained with these transistors. The specific on-resistance at room temperature was 8 mΩ⋅cm2 and the maximum current gain was 11. A maximum current gain of 32 has been obtained for 4H-SiC power BJTs using Al-free ohmic contact to the base [40]. By increasing the n- collector region, an epitaxial emitter BJT with a current gain of 20 and BVCEO >3200 V, which is the highest BV reported to date, has been achieved [36].

When operating at high power levels the power devices generate a large amount of heat that causes lattice heating (or self-heating) and the devices have to work at an elevated temperature. Despite the high thermal conductivity of SiC, the self-heating is still a big challenge at very high power operating conditions [44, 45]. The temperature rise in the devices by self-heating or directly by the high temperature environment results in the variation of the electrical properties of the material, such as carrier mobility, electron saturation velocity, ionization rate, thermal conductivity, etc. which in turn influence the electrical behavior of the devices. So far there are only a few articles [46, 47] published on the thermal related issues of the devices.

In this Ph.D thesis, the effects of self-heating and high environment temperature on the performance of 4H-SiC RF power MESFETs and 4H-SiC power BJTs are investigated through both simulations and experiments. Simulation and measurement are the two important methods for device design and characterization. Simulation is cost effective and time saving and especially useful at the design stage for comparison and optimization of different device structures and doping. However, its validation must be proved by measurement. On the other hand, the measurement is good for characterization of fabricated devices and can be used to verify the simulation models and calibrate the parameters in the simulation models.

The investigations of SiC RF power MESFETs are described in chapter 2. DC and HF measurements and two-dimensional electro-thermal simulations were performed. The performance degradation of 4H-SiC RF Power MESFETs caused by self-heating and high environment temperature is presented in terms of gate and drain characteristics (Id-Vg & Id-Vd), maximum power density (Pmax), high frequency current gain and power gain (|H21| & MSG/MAG), cut-off frequency and maximum frequency of oscillation (ft & fmax). 3D thermal simulations have also been done for single and multi-finger MESFETs to analyze the

Electro-Thermal Investigations of 4H-SiC RF Power MESFETs and 4H-SiC Power BJTs

3

phenomena of the decrease of power density with gate periphery. The thermal related design issues for large area high power devices have been discussed. The instabilities caused by traps in SiC semi-insulating substrate and on the un-gated surface of the device were analyzed up to 300 °C through experimental approaches.

In chapter 3 the simulation and experimental work is presented for SiC power BJTs. The junction temperature was extracted based on the collector current-voltage measurement and compared with the 3D thermal simulation results. An infrared camera was used for the chip surface temperature measurement. Increase of temperature in the vicinity of the device when operated at high power densities was observed, thus causing the decrease of the DC current gain. The thermal images from the infrared camera were compared with the simulated temperature profiles.

Summary and perspective of future work in the field of electro-thermal investigations of SiC power transistors can be found in chapter 4.

5

2 Electro-Thermal Investigation of Silicon Carbide RF Power MESFETs

The investigations of MESFETs are described in this chapter and can be partly found also in paper I, II, III, IV, and VI. In paper I the simulations were performed using MEDICI [48] and the simulated transistor has a gate length of 1 µm. In this thesis a transistor with a smaller gate length of 0.5 µm has also been investigated using another commercial software, ISE [49].

First the simulation models are described. Then the simulation results are demonstrated. Finally the results from measurements are shown and compared with the simulations. Thermal issues for design of SiC MESFETs and trap-induced instabilities in device performance are discussed at the end of this chapter.

2.1 Device description

The schematic structure of the MESFET under investigation is shown in Fig. 2.1. It is a unipolar FET with Schottky gate on top of a recessed channel. There are three epitaxial layers on a semi-insulating substrate, an n-type layer acting as the active channel, a p-type buffer layer between the channel and the substrate to prevent the channel from the influence of the substrate defects, and an n+ contact layer on the top to form Ohmic contacts for source and drain. The source is grounded. When a positive voltage is applied to the drain, current flows from the drain to the source, and the current is controlled through applying a negative voltage at the gate, which depletes the channel from the top. There is also a depletion of the channel from the P- buffer side.

Fig. 2.1 Perspective of SiC MESFET structure.

Source

Gate

Drain

N-channel

P-buffer

Semi-insulating substrate

N+-cap

++++++++ ++++++

Wei Liu 2 Electro-Thermal Investigation of Silicon Carbide RF Power MESFETs

6 6

The device dimensions and doping profiles are listed in Fig. 2.2.

LSCONT = 5.0 µm

LSC = 0.9 µm

LGS = 0.5 µm

LGATE = 0.5 µm

LGD = 1.0 µm

LDC = 0.9 µm

LDCONT = 5.0 µm

TCAP = 0.1 µm

TRECESS = 0.03 µm

TCHANNEL = 0.27 µm

TBUFFER = 0.2 µm

TSUBST = 0.25µm

Nd(cap) =1019 cm-3

Nd(channel) =3⋅1017 cm-3

Na(buffer) = 2⋅1017 cm-3

Nd(substrate) = 105 cm-3

Fig 2.2 Device structure and doping profile of 4H-SiC RF power MESFET

2.2 Device simulation models

Device simulation has been a very useful tool for the design of new devices and the characterization of fabricated devices. In this section the physical equations and models for SiC device simulation are described. The parameters used in the models are from the SiC material properties database [50] established in our laboratory based on recently published references and are listed in the Appendix.

2.2.1 Basic equations

The fundamental equations solved in simulations are the partial differential equations as follows:

Poisson’s equation

sad NNnpq ρψε −−+−−=∇ −+ )(2 (2-1)

TRECESS

LSCONT LSC

LGS LGATE LGD

LDC LDCONT

TCAP

TCHANNEL

TBUFFER

TSUBST

N+ N+

N-Channel

P-buffer

Semi-insulating substrate

N-channel


7

Continuity equations for electrons and holes

nUqt

n−⋅∇=

∂∂

nJ1 (2-2)

pUqt

p−⋅∇−=

∂∂

pJ1 (2-3)

Electron and hole current density equations based on Boltzmann transport theory

nqDqn nn ∇+= nn EJ µ (2-4)

pqDqp ppp ∇−= pEJ µ (2-5)

Neglecting the effect of bandgap narrowing and assuming Boltzmann carrier statistics, the electrical field E can be described as

ψ−∇=== EEE pn (2-6)

The electrostatic potential, ψ , and the electron and hole concentrations, n and p can be obtained through Equation (2-1), (2-2), and (2-3). The net electron and hole recombination rate Un and Up are calculated using recombination models. The electron mobility µn and the hole mobility µp are determined by mobility models.

2.2.2 Recombination models

Shockley-Read-Hall (SRH) and Auger recombination models were adapted in the simulation. That is

AugerSRHpn UUUUU +=== (2-7)

where

−++

+

−=

)E

exp()E

exp( TrapTrap

2

kTnp

kTnn

npnU

ieniep

ieSRH

ττ (2-8)

))(CC( 2pn ieAuger nnppnU −+= (2-9)

The parameter ETrap represents the difference between the trap energy level, Et, and the intrinsic Fermi energy, Ei (i.e., ETrap = Et - Ei), τn and τp are electron and hole carrier life times, and Cn and Cp are specified constants listed in the Appendix.


8 8

2.2.3 Mobility models

The mobility of SiC is anisotropic. The ratio between the electron mobility perpendicular and parallel to the c-axis is 0.83. There are different mobility models for simulations. The ARORA mobility model for low field and the Caughey-Thomas field dependent mobility model for high field were chosen in the simulations.

The low field mobility model takes into account the total impurity concentration, NTotal, and the temperature, T. The mobility expressions for electron and hole are

Tn

300

C1

µµ

refn,

ns,minns,,

α

µ

+

+=∆ T

Nna

Total

ns (2-10)

Tp

300

C1

µµ

refp,

ps,minps,,

α

µ

+

+=∆ T

Npa

Total

ps (2-11)

The parameters used in the equations are listed in the Appendix.


9

The electron and hole mobilities perpendicular to c-axis µ⊥,n and µ⊥,p defined in Eq. 2-10 and 2-11 are plotted in Fig. 2.3a and 2.3b. The mobilities have negative dependence on both doping concentration and temperature. The electron mobility at a doping level of 3⋅1017 (the channel doping concentration of the MESFETs) is about 415 cm2/V⋅s at room temperature (300 K) and 140 cm2/V⋅s at 500K.

1015 1016 1017 1018 1019 10200

200

400

600

800

1000

Doping concentration (cm-3)

Ele

ctro

n M

obilit

y (c

m2 V

-1se

c-1)

T = 300 KT = 400 KT = 500 K

Fig. 2.3a Electron mobility of 4H-SiC material

1015 1016 1017 1018 1019 102020

40

60

80

100

120

140T = 300 KT = 400 KT = 500 K

Hol

e M

obilit

y (c

m2 V

-1se

c-1)

Doping concentration (cm-3)

Fig. 2.3b Hole mobility of 4H-SiC material


10 10

The Caughey-Thomas expressions were used for high field mobilities

n

n

satn

nns

nsn

vE

ββµ

µµ 1

||,,

,

1

+

= (2-12)

p

p

satp

pps

psp

vE

ββµ

µµ 1

||,,

,

1

+

= (2-13)

where µs,n and µs,p are the low field mobilities and νnsat and νp

sat are saturation velocities for electrons and holes. The temperature dependent saturation velocities are described as:

nTv sat

nα−= )

300(Vn (2-14)

pTv satp

α−= )300

(Vp (2-15)

The dependence of the saturation velocity on temperature is also negative.

2.2.4 Incomplete ionization of impurities

Poisson’s equation (Eq. 2-1) includes the ionized impurity concentrations Nd+ and Na

- in the expression for space charge. Because the energy levels of dopants of SiC are much deeper than in Si (especially for the acceptors) the dopants cannot be fully ionized at room temperature. The ionization rates of the impurities are temperature dependent. Using Fermi-Dirac statistics with appropriate degeneracy factor for the conduction and valence bands GCB and GVB, the effective impurity concentration for donor (nitrogen, N, in this case) and acceptor (aluminum, Al, in this case) can be expressed as:

−+

=+

kTEE

NN

DF

dd

nexpG1 CB

(2-16)

−+

=+

kT

EEN

NpFA

aa

expG1 VB

(2-17)

where ED = EC-EDB and EA = EAB+EV are the donor and acceptor energy levels.


11

2.2.5 Impact ionization

If the electrical field exceeds a certain level, the carriers can get sufficient energy from acceleration in the field to cause ionizing collisions with the lattice and create new electron-hole pairs. The electron-hole generation rate due to impact ionization can be expressed as

qqG iipiin

II ||.||. ,,

pn JJ αα += (2-18)

where αn,ii and αp,ii are the electron and hole ionization coefficients, and Jn and Jp are the electron and hole current densities. The ionization coefficients can be expressed in terms of the local electric field according to

( )

−⋅= ∞

iin,

||,

cn,,

Eexp

α

ααn

iiniin ET (2-19)

( )

−⋅= ∞

iip,

||,

cp,,

Eexp

α

ααp

iipiip ET (2-20)

where nE||, and pE||, are the electric field components in the direction of current flow.

2n2n1n0, aaa)( TTTiin ⋅+⋅+=∞α (2-21)

2p2p1p0, aaa)( TTTiip ⋅+⋅+=∞α (2-22)

2.2.6 Bandgap and effective density of states

The bandgap and effective density of states have temperature dependence as follows

( ) ( )g

g

E

2E

0β

α

+−=

T

TETE gg

+−

++=

g

gE

Eg TTE

ββα

2

E

2

300g

300300 (2-23)

( )23

C300

23

2 300N

22

=

=

Th

kTmMTN de

CCπ

(2-24)

( )23

V300

23

2 300N

22

=

=

Th

kTmMTN dh

VVπ

(2-25)


12 12

2.2.7 Lattice heating models

When lattice temperature is to be included in the simulation, the heat flow equation is solved together with the Poisson’s equation and continuity equations.

Heat flow equation

( )( )TTHtTc ∇⋅∇+=

∂∂ λρ (2-26)

The thermal conductivity of SiC is temperature dependent and given by th/)( th

βαλ TT = (2-27)

The heat generation in the semiconductor is modeled using:

Upn HHHH ++= (2-28)

where Hn, Hp, and HU are lattice heating due to electron transport, hole transport, and carrier recombination/generation respectively.

Poisson’s equation

When the lattice temperature is not spatially constant, the intrinsic Fermi potential is no longer, in most cases, a solution to Poisson’s equation. In this case, Poisson’s equation is written as:

sad NNnpq ρθψε −−+−−=−∇⋅∇ −+ )()( (2-29)

where θ is the band structure parameter for the material and is given by

++=

V

Cg

NN

qkT

qE

ln22

χθ (2-30)

Current density equations

With lattice heating the current density equations are described as follows

( )TnnTkqn nn ∇+∇+= µµ nn EJ (2-31)

( )TppTkqp pppp ∇+∇−= µµ EJ (2-32)

Material properties and parameters used in the above equations for device simulations are listed in the Appendix.


13

2.3 Isothermal DC and HF simulations

In isothermal simulations the lattice temperature is assumed to be constant. The heat flow equation is not included in the simulations. Only the Poisson’s equation and continuity equations are numerically solved.

2.3.1 DC simulations

The drain and gate characteristics of the devices were simulated using ISE [49] at room and elevated temperatures up to 500 °C and the results are shown in Fig. 2.4-2.5. Based on these two current-voltage (Id-Vg or Id-Vd) curves many useful parameters, such as electron

-15 -10 -5 00

50

100

150

200

250

300

Gate voltage ( V )

Dra

in c

urre

nt (

mA

/mm

)

25°C100°C200°C400°C500°C

Vd = 10 V No Self-heating

Fig. 2.5 Gate characteristics at different temperatures

Fig. 2.4 Drain characteristics at different temperatures

0 20 40 60 80 100 120 140 160 180 2000

200

400

600

800

1000

1200

1400

Drain voltage ( V )

Dra

in c

urre

nt (

mA

/mm

)

25°C100°C200°C300°C400°C500°C

Vg = 0 V No self-heating

VbreakVknee

Isat


14 14

saturation current, Isat, knee voltage, Vknee, breakdown voltage, Vbreak, maximum power density, Pmax, threshold voltage, VT, and maximum transconductance, gm, were deduced or calculated and the results are given in Table 2.1.

Table 2.1 DC parameters at different temperatures

T

(°C )

Isat

( mA/mm )

Vknee

( V )

Vbreak

( V )

Pmax

( W/mm )

|VT|

( V )

gm

( mS/mm )

25 505 10 189 11.3 12 34.7

100 404 12 182 8.6 12 27.0

200 280 12 168 5.5 12.5 20.9

300 203 12 156 3.7 No

convergence

No

convergence

400 150 12 147 2.5 14 11.4

500 115 12 135 1.8 14 9.0

The maximum power density, Pmax, depends on maximum current swing from 0 to maximum saturation output current Isat and maximum voltage swing from the knee voltage Vknee to the breakdown voltage Vbreak and takes the form of

8)(

maxkneebreaksat VVIP −

= (2-33)

The transconductance is defined as

constdV

g

dm V

Ig =∂∂

= max| (2-34)

It can be derived according to the Id-Vg or Id-Vd curves.

The theoretical value of the threshold voltage can be obtained using the following equation

pbiT VVV −= (2-35)

where the Vbi is the built in potential of the Shottky gate and the pinch-off voltage Vp is expressed as

ε2

2aqNV d

p

+

= (2-36)

where Nd+ is the ionized donor concentration in the channel and a is the channel thickness.

As the temperature increases, the electron mobility and electron saturation velocity decrease, so the drain current at a given gate and drain bias decrease with temperature. The breakdown voltage could decrease or increase with temperature depending on whether the electrons or holes dominate in the avalanche process, since the ionization rate of electrons has a positive


15

dependence on the temperature while the ionization rate of holes has a negative dependence [51, 52]. In this case the channel is n-type with a pure donor impurity concentration of 3x1017. The electrons play a major role in the impact ionization process, resulting in a negative dependence of breakdown voltage on temperature (worst case). With acceptor compensation in the channel the holes could take part in the process and an opposite conclusion could be made (see breakdown simulation in paper I). There is no significant temperature influence on the knee voltage. However, the drop of the maximum power density with increased temperature is tremendous due to the combination of decrease in breakdown voltage and saturation current. The threshold voltage, VT, has a negative value and |VT| increases with temperature. This can be caused by the higher ionization of impurities at higher temperatures, resulting in a higher effective doping in the channel and higher pinch-off voltage. A drop of transconductance, gm, at high temperature was also observed (34.7 mS/mm at 25 °C and 20.9 mS/mm at 200 °C).

It should be mentioned that like in all simulations some simplifications have been made, it is assumed that the substrate and epi-layers are clean without traps, the channel thickness and doping are constant. For HF simulations (described in section 2.3.2) external parasitics are not considered, except the contact resistances at the source and drain. So the absolute values obtained from the simulations are not significant, but the trends are of interest.

2.3.2 HF simulations

The small signal high frequency behavior of the devices at room and elevated temperatures up to 500 °C was analyzed in the framework of two-port networks (Fig. 2.6). S-parameters as a function of frequency were obtained in the small signal simulations using ISE [49]. RF characteristics were extracted from the simulated S-parameters.

According to S-parameter theory, the current gain can be computed using the following formula:

|)1)(1(

2|||21122211

2121 SSSS

SH++−

−= (2-37)

The power gain including the Mason unilateral gain (U), maximum available gain (MAG), and maximum stable gain (MSG), are described as

||

|1|5.0

12

21

12

21

2

12

21

SSreal

SSk

SS

U−

−= (2-38)

)1(|||| 2

12

21 −−= kkSSMAG (2-39)

Vg Vd

G

D

S

1 2

Fig. 2.6 Two port circuit for the RF extraction simulation.


16 16

||||

12

21

SSMSG = (2-40)

where k is the stability factor and given by

||2||||||1

2112

222

211

221122211

SSSSSSSSk −−−+

= (2-41)

The power gain MSG/MAG takes the value of MSG when k<1, and MAG when k>1.

The current and power gain in dB is defined as:

( ) ||log20|| 211021 HdBH = (2-42)

( ) )/(log10/ 10 MAGMSGdBMAGMSG = (2-43)

The extracted current gain and power gain as a function of frequency are plotted in Fig. 2.7-2.8. Two very important RF characters, the cut-off frequency fT (defined as the frequency at which the current gain is equal to 1) and the maximum frequency of oscillation fmax (defined as the frequency at which the power gain is unity), were determined based on these figures and are listed in Table 2.2.

Table 2.2 HF parameters at different temperatures

T (°C ) fT (GHz) fmax (GHz) Current gain @ 2GHz (dB) Power gain @ 2GHz (dB)

25 18.5 43 18.4 17.4

100 13.6 31 15.5 15.6

200 7.3 16 10.6 12.3

300 6.8 14 9.7 12.0

400 5.4 12 8.0 11.4

500 4.7 11 6.8 10.7


17

It was observed that the HF performance degraded profoundly with increasing temperature. The cut-off frequency fT decreased from 18.5GHz to 4.7GHz and the maximum frequency of oscillation fmax from 43GHz to 11GHz when the temperature was raised from 25 to 500 °C. The RF power gain (@2GHz) at 500 °C is only about 60% of that at room temperature.

109 1010 10110

5

10

15

20

25

Frequency (Hz)

|H21

| (d

B)

25°C100°C200°C300°C400°C500°C

Vd = 30 V Vg = -5 V No self-heating

fT

Fig. 2.7 Simulated current gains at different temperatures

109 1010 10110

5

10

15

20

25

Frequency (Hz)

MS

G/M

AG

(dB

)

25°C100°C200°C300°C400°C500°C

Vd = 30 V Vg = -5 V No self-heating

fmax

Fig. 2.8 Simulated power gains at different temperatures


18 18

2.4 Self-heating effects

Self-heating caused by the conversion of electrical energy into thermal energy increases the lattice temperature which influences electron mobility, ionization and saturation velocity. The more heat generated, the more influence on device performance. Devices operating at high drain voltage and current suffer from the reduction of mobility and saturation velocity, resulting in a reduction in drain current. Increased density of ionized donors plays a minor role until Vd approaches the breakdown voltage. The self-heating effect is also dependent on the substrate and package thermal resistance. With lower thermal resistance the heat can be dissipated more easily and the heating is less severe.

Self–heating effects were investigated through electro-thermal simulations using ISE [49]. The Poisson’s equation, continuity equations, and heat transfer equation were solved simultaneously. The package and substrate were taken as a bulk thermal resistance connected with a heat sink. The results are partially shown here. More results can be found in Paper II. Thermal simulations with only the heat transfer equation being solved are described in section 2.8.

The simulated drain characteristics of a device undergoing self-heating is plotted in Fig. 2.9 and compared with the results from simulations without any consideration of heating. It was found that, with lattice heating, the drain current was smaller than without self-heating. The difference is negligible for low drain voltages (Vd < 5 V) but becomes larger at higher drain voltages due to the higher heat generation. At room temperature the difference is more obvious than at elevated temperatures for the same reason.

Fig. 2.9 Drain characteristics of a device with and without self-heating

0 10 20 30 400

100

200

300

400

500

Drain voltage ( V )

Dra

in c

urre

nt (

mA

/mm

)

Solid lines without self-heating Dashed lines with self-heating The temperatures are 25, 100,200, 300°C

increasing T


19

The simulations also showed that self-heating analysis is especially important for design of multi-finger devices. With the same size of substrate (300×300 µm2) and gate pitch (50 µm) the three-fingered device suffered much more from self-heating than the one-fingered device (shown in Fig. 2.10-2.11). At an operating condition Vg = -1 V and Vd = 40 V the maximum temperature in the three-fingered device is as high as 446 K while the one-fingered device has a temperature of 405 K. The value is 430 K for the two-fingered device. The temperature contour from ISE electro-thermal simulation for the three-fingered device is illustrated in Fig. 2.12. The backside thermal resistance was set to zero, but the 300 µm thick substrate was included in the simulation domain.

Fig. 2.10 Drain characteristics of deviceswith 1, 2, 3 gate fingers

0 10 20 30 400

50

100

150

200

250

300

350

400

Dra

in c

urre

nt (m

A/m

m )

One finger Two fingers Three fingers

Drain voltage ( V )

Vg = -1 V300um*300umRth = 0

0 10 20 30 40300

325

350

375

400

425

450

Drain voltage (V)

Max

imum

tem

pera

ture

(K)

Three fingersTwo fingersone finger

Vg = -1 V300um*300umRth = 0

Fig. 2.11 Maximum temperature of deviceswith 1, 2, 3 gate fingers

Fig. 2.12 Cross-section temperature contour of a device with three gate fingersworking at Vg = -1 V, Vd = 40 V.

(K)


20 20

Fig. 2.13 Measured gate characteristics at 25 °C and 250 °C.

2.5 DC and HF measurements

The measurements were carried out on a probe station equipped with a hot chuck. A HP4156 semiconductor parameter analyzer and a HP8510A network analyzer were used for current-voltage measurements and HF S-parameter measurements respectively. The measurements were performed up to 250 ˚C and 26.5 GHz. The results are partially shown here. Details can be found in Paper IV.

The measured gate and drain characteristics at 25 and 250 °C are shown in Fig. 2.13-2.14. The threshold voltage decreased with increased temperature and drain voltage. The shift of the threshold voltage was more prominent at low temperatures (2 V from 25 to 100 ˚C) than

-12 -10 -8 -6 -4 -2 00

50

100

150

200

250

Gate voltage (V)

Dra

in c

urre

nt (m

A/m

m)

Solid lines for 25°C Dotted lines for 250°CVd=30, 20, 10V from the top to the bottomfor both temperatures

Fig. 2.14 Measured drain characteristics at 25 °C and 250 °C.

0 5 10 15 20 25 30 350

50

100

150

200

250

300

Drain Voltage (V)

Dra

in c

urre

nt (

mA

/mm

)

Solid lines for 25°C Dotted lines for 250 °C Vg=-1V for the top line & the step is -1V


21

at high temperatures (negligible shift above 150 ˚C). A reasonable explanation of the dependence of the threshold voltage on the temperature is deep level traps in the substrate/buffer, which induce extra charges at the channel-buffer interface acting as a backside gate. As the temperature increases de-trapping starts to occur and the depletion from the backside to the channel becomes smaller, which causes the decrease of the threshold voltage. The knee voltage at room temperature (about 32 V) is larger than at 250 ˚C (20 V). The decrease of saturation current with temperature was witnessed from the measurements. No short channel effects were observed due to the self-heating. This could be a benefit because good linearity can be achieved through the balance of the short channel effects and the self-heating.

Current and power gain were extracted from the HF s-parameter measurement results and are plotted in Fig. 2.15 as a function of frequency. Decrease of the gains and fT and fmax with temperature can be seen. Their values are listed in Table. 2.3. The current gain and power gain values are extracted at a frequency of 2 GHz.

Fig. 2.15 Measured current and power gain at 25, 150, and 250 ˚C.

109 1010 10110

5

10

15

20

Frequency ( Hz )

|H21

|, M

SG

/MA

G (

dB )

Solid lines for power gainDotted lines for current gainThe temperatures are 25,150,250 °C from the topVg = -5 V, Vd = 30 V


22 22

Table 2.3 Measured HF parameters at different temperatures

|H21| (dB) at 2 GHz MAG (dB) at 2 GHz fT (GHz) fmax (GHz)

25˚C 9.2 12.2 6.2 24

150˚C 8.3 11.5 5.3 19

250˚C 6.8 10.7 4.4 14

2.6 Comparison of simulations and measurements

Fig. 2.16 shows the drain characteristics (Id-Vd) from measurements and simulations for a device operating at 250 °C. Good saturation and linearity were seen for devices operating at up to 250 °C. The measured knee voltages are larger than the simulated ones and the saturation currents are smaller compared with the simulated values. The difference could be caused by the surface and the substrate traps, which were not included in the simulations due to the difficulty to describe the temperature dependence of the trap behavior. The variation of the thickness and doping in the epilayers could also contribute to the difference.

Fig. 2.16 Measured and simulated drain characteristics at 250 °C.

0 5 10 15 20 25 30 350

50

100

150

200

250Solid lines for simulations Dotted lines for measurements Vg=-1V for the top line The step is -1V

Dra

in c

urre

nt (m

A/m

m)

Drain voltage (V)


23

Fig. 2.17-2.18 demonstrate the measured and simulated current gain and power gains. The measurements show a decrease of fT and fmax with a temperature increase from 25 °C to 250 °C. Higher fT and fmax were obtained from simulations. Traps in the device structure and parasitics (pad capacitance etc) are believed to be the main causes for the differences between the measurements and the simulations. A strong influence of contact resistance was seen on fT and fmax in the HF simulations. A reduction in fT from 13 to 7.1 GHz and a reduction in fmax from 39 to 16 GHz have been observed when taking the contact resistances into account. The measured and simulated fT and fmax at 25 and 250 °C are summarized in Table 2.4.

Fig. 2.17 Measured and simulated current gains at 25 °C and 250 °C.

109 1010 10110

5

10

15

20

25

30

Frequency (Hz)

|H21

| (dB

)

Current gains at different temperatures

Simulated @ 25°CSimulated @ 250°CMeasured @ 25°CMeasured @ 250°C

Vd = 30 V Vg = -5 VNo self-heating

fT

Fig. 2.18 Measured and simulated power gains at 25 °C and 250 °C.

109 1010 10110

5

10

15

20

25

30

Frequency (Hz)

MS

G /

MA

G (d

B)

Power gains at different temperatures

Simulated @ 25°CSimulated @ 250°CMeasured @ 25°CMeasured @ 250°C

Vd = 30 V Vg = -5 VNo self-heating

fmax


24 24

Table 2.4 Measured and simulated cut-off frequency and maximum frequency of oscillation

T(°C) fT

simulated

(GHz)

Rc = 0

fT

simulated

(GHz)

Rc = 10-4

Ω⋅cm2

fT

measured

(GHz)

fmax

simulated

(GHz)

Rc = 0

fmax

simulated

(GHz)

Rc = 10-4

Ω⋅cm2

fmax

measured

(GHz)

34 18.5 6.2 >100 43.0 24

13 7.1 4.4 39 16 14

2.7 Trap-induced performance instabilities of SiC MESFETs

The main obstacles for broad applications of SiC MESFET are the cost and difficulty to fabricate defect-free devices. Traps in substrate and at the surface of the devices can cause instabilities in device static and RF characteristics [11, 12, 19, 27-30, 53-56].

Trapping associated with the SiC substrate is apparent for MESFETs with vanadium-doped semi-insulating substrate [30, 53]. Using a buffer layer to insulate the channel from the substrate is a good solution [28, 54, 55]. However, optimized buffer thickness and doping are critical to realize the control function of the buffer. Recently the use of high purity substrate [12, 53, 54] greatly reduces the undesirable effects of substrate trapping. Surface related traps [19, 56] which typically cause the delay of response of drain current to gate voltage change (gate lag) [19] can be removed by good surface passivation [12, 56] or the use of an undoped “spacer” [19].

In this section trap-induced instabilities in device performance are investigated through experimental approaches − DC, pulse, and transient measurements. Two device structures have been studied. One has a vanadium-doped semi-insulating substrate grown by the classical Physical Vapor Transport (PVT) sublimation technique and the other has a high purity semi-insulating substrate grown by the high temperature (HTCVD) technique. Details can be found in Paper III.

2.7.1 Substrate traps

DC measurements on gate characteristics for SiC MESFETs with vanadium doped semi-insulating substrate show a temperature dependent threshold voltage (see Fig. 2.19). The results have been discussed in section 2.5-2.6. The filled traps in the substrate induce extra depletion of the channel from the backside (see Fig. 2.20), acting as a parasitic backside gate. At high temperatures trapped electrons are activated and the depletion from the backside to


25

the channel becomes less, thus a higher negative gate voltage is needed to pinch off the channel from the top, which causes the decrease of the threshold voltage. As discussed in section 2.5-2.6, the depletion from backside also results in a reduction in drain current and an increase in knee voltage, and finally a reduction in output power.

.

Source

Gate

Drain

N-channel

P-buffer

Vanadium doped semi-insulating substrate

N+-cap

Substrate Traps

Induced Depletion

Traps

Fig. 2.20 Cross-sectional schematic of SiC MESFET device structure showingsubstrate trap-induced depletion.

-12 -10 -8 -6 -4 -2 00

50

100

150

200

250

Gate voltage (V)

Dra

in c

urre

nt (m

A/m

m)


Id-Vg for device with vanadium doped substrate

Fig. 2.19 Measured gate characteristics at 25 and 250 °C for device with vanadiumdoped substrate


26 26

2.7.2 Surface traps

DC, pulsed and transient measurements were performed for devices with high purity substrate grown by the high temperature (HTCVD) technique.

Fig. 2.21 shows DC gate characteristics for SiC MESFETs with high purity substrate measured at 25 and 250 °C. No threshold voltage dependence on temperature can be observed, in contrast to the results for devices with vanadium-doped substrate (see Fig. 2.19). A reasonable explanation for the difference might be that there are much less traps in the high purity substrate compared to the vanadium-doped substrate, thus the backside depletion (backside gating) caused by the substrate traps is negligible for such devices. Fig. 2.22 shows the experimental drain characteristics of the device obtained in DC and pulse measurements

-12 -10 -8 -6 -4 -2 00

50

100

150

200

250

300

350

400

Gate voltage (V)

Dra

in c

urre

nt (m

A/m

m)

Id-Vg for device with high purity substrate


Fig. 2.21 Measured gate characteristics at 25 and 250 °C for device with high purity substrate.

Fig. 2.22 Experimental drain characteristics obtained in DC and by pulsing Vgfrom –15 V to the quoted Vg.

0 10 20 30 400

50

100

150

200

250

300

350

400

Drain voltage ( V )

Dra

in c

urre

nt (

mA

/mm

)

Solid lines for DC measurementDotted lines for pulse measurementVg= 0, -2, -4 V25°C


27

by pulsing Vg from –15 V (opening the channel from pinch-off state) to the quoted Vg. A significant reduction in Id (drain current collapse) is evident in the Vg turn-on pulsing mode compared with the DC values.

Experimental Id(t) from transient measurements with microscope illumination and Vg pulsing from –15 V to 0 V is shown in Fig. 2.23. The rise time for the pulse is 100 ns and the measurements were done at t = 300 ns. As can be seen, Id(t) increases with time. Channel current Id(t) can not respond as rapidly as the gate voltage (called gate lag). This gate lag is usually attributed to traps occurring at the un-gated channel surfaces with long time constants relative to the RF operation frequency [19]. During portions of the signal when a large negative voltage is present, electrons are injected into these trap states, causing extra depletion of the channel under the un-gated surfaces (see. Fig.2.24). At high frequencies, there is insufficient time during the gate voltage swing for these trap states to become fully

0 0.2 0.4 0.6 0.8 10

50

100

150

200

250

300

350

Time ( s )

Dra

in c

urre

nt (

mm

/mA

)

25°CVd = 10 VVg step from -15 V to 0 V at t = 0 s

Fig. 2.23 Experimental Id(t) transient in response of a Vg turn-on pulse at Vd = 10V, T = 25 °C, with strong light.

Source

Gate

Drain

N-channel

P-buffer

High purity semi-insulating substrate

N+-cap

Surface Traps

Induced Depletion

Traps Traps

Fig. 2.24 Cross-sectional schematic of SiC MESFET device structure showing surfacetrap-induced depletion.


28 28

neutralized so that the channel region under the un-gated surfaces remains partially depleted during the entire period of the RF cycle. This prevents the channel from becoming fully open (un-depleted) during the positive voltage portion of the gate swing, resulting in a reduced RF current, gain, and output power.

The change of the charge state can take place due to capture or emission of electrons. The characteristic time for emission of an electron (de-trapping) is [57]

NvckTEt te /)/exp(= (2-44)

where Et is the energy level of the trap in relation to the conduction band edge, N is the density of states in that band, v is the thermal velocity, and c is the capture cross section.

The mean capture time for electrons (trapping) is

nvctc /1= (2-45)

where n is the concentration of electrons in the vicinity of the traps.

The ratio between the emission and capture time constant is

( )[ ]kTeFtt tnce /exp/ −= (2-46)

where Fn is the electron Fermi level, et is the trap energy level.

Whether the traps are filled or empty depends on the position of trap level et relative to the electron Fermi level Fn. If et is above Fn, the capture time is larger than the emission time and the traps are empty. On the other hand, if et is below Fn, the traps are filled. When the gate voltage changes from a large negative value to zero, the electron Fermi level is bent downwards to a position below the trap level, the surface states change from filled to empty. However it takes time to empty the filled states at the surface.

The time for emptying the traps is related to the surface potential and the operating temperature of the device according to Eq. 2-46. This time constant at high temperatures (for example 300 °C) are much smaller than at room temperature. Therefore the trap-induced instabilities are less severe at elevated temperatures. Fig. 2-25a-b show the measured drain characteristics at 25 and 300 °C with sweeps of Vd upwards and downwards. Large hysteresis loops are observed at room temperature (see Fig. 2-25a), whereas at 300 °C the hysteresis is not obvious (see Fig. 2-25b).

0 10 20 30 400

50

100

150

200

250

300

350

400

Drain voltage ( V )

Dra

in c

urre

nt (

mA

/mm

)

25°CVd= 0 to 40 in 0.5 stepVg= -12 to 0 in 2 step

0 10 20 30 400

50

100

150

200

250

300

350

400

Drain voltage ( V )

Dra

in c

urre

nt (

mA

/mm

)

300°CVd= 0 to 40 in 0.5 stepVg= -12 to 0 in 2 step

( a ) ( b )

Fig. 2.25 Measured drain characteristics at 25 and 300 °C with double sweep of Vd.


29

Measured Id(t) with the gate pulsing from -15 V to 0 V at 25 and 300 °C in dark and light are shown in Fig. 2.26-2.27. It can be seen that there is a long time delay for the drain current to respond the shift of the gate voltage at 25 °C, while there is only a short time delay at 300 °C. The time constants for empting the traps at room temperature are found to be different with light on and off. It takes about 10 s for Id(t) to reach its steady state value with light, while it takes minutes without light (see Fig 2.26), which means light can accelerates the emission of electrons. It was also observed that at high temperature (300 °C), there is little influence of light on the device performance (see Fig 2.27).

Fig. 2.27 Experimental Id(t) transient in response of a Vg turn-on pulse at Vd = 10 V, T = 300 °C, with light on and off.

0 2 4 6 8 10 120

50

100

150

200

Time ( s )

Dra

in c

urre

nt (

mA

/mm

)

In lightIn dark

300°C Vd = 10 VVg step from -15 V to 0 V at t = 1 s

Fig. 2.26 Experimental Id(t) transient in response of a Vg turn-on pulse at Vd = 10 V, T = 25 °C, with light on and off.

0 2 4 6 8 10 120

50

100

150

200

250

300

350

Time ( s )

Dra

in c

urre

nt (

mA

/mm

)

In lightIn dark

25°C Vd = 10 VVg step from -15 V to 0 V at t = 1 s


30 30

2.8 Thermal issues for SiC MESFET design

The DC and RF performance of SiC MESFETs is temperature dependent. High operating temperature deteriorates the high power capability and RF signal response of the devices [53, 46, 47], especially for large gate periphery MESFETs. Thermal design is a key issue for such devices.

2.8.1 Comparison of thermal simulations and electro-thermal simulations

Electro-thermal simulation results for MESFETs with 1, 2, and 3 gate fingers are shown in section 2.4. In electro-thermal simulations using ISE [49] the heat transfer equation is solved with the Poisson’s equation and continuity equations. In thermal simulations using FEMLAB [58] only the heat transfer equation is solved.

Three-dimensional chip level heat transfer simulations were performed using FEMLAB [58] for MESFETs with 1, 2, and 3 gate fingers. The heat transfer equation (see Eq. 2-28) was numerically solved for specific boundary conditions and the temperature distribution within the chip was obtained.

Fig. 2.28 3D Temperature distribution of devices with 1, 2, and 3 gate fingers.

0 10 20 30 400

50

100

150

200

250

300

350

400

Dra

in c

urre

nt (m

A/m

m )

Drain characteristics of devices with multi-fingers

One figure Two figures Three figures

Drain voltage ( V )

Vg = -1 V300um*300umRth = 0

399.584

(K)

442.7402

(K)

425.635

300

(K)


31

The substrate size is 300x500x300 µm. The device is located on the top of the substrate. Each finger is treated as a heat source dissipating heat into the substrate. The heat flux is equal to the DC power generated by the device IdVd divided by the device active surface area A, i.e. qth = Id Vd / A. The Id was obtained from ISE simulations at Vg = -1 V and Vd = 40 V for these three MESFETs (see Fig. 2.28).

The simulated 3D temperature distribution for devices with 1, 2, and 3 gate fingers are shown in Fig. 2.28. The temperature profiles and the maximum temperatures for these three cases agree quite well with the values from ISE electro-thermal simulations (see section 2.4). The maximum temperatures are listed in Table 2.5.

Table 2.5 Maximum chip temperatures of 1-, 2-, and 3-gate-finger devices

FEMLAB ISE

One finger 400 K 405 K

Two fingers 426 K 430 K

Three fingers 443 K 446 K

The temperature profile along the cut line on the top surface of the device with 3 fingers (line marked in Fig. 2.28) is plotted in Fig. 2.29. The temperatures obtained from the two simulation methods are quite similar. Higher junction temperature and sharper peak were witnessed from ISE simulation. The main reason for the difference is that in electro-thermal simulations the active device was located on top of the substrate so that the heat generated by the device can only be dissipated through the backside of the device to the substrate. On the other hand, in FEMLAB simulations the device was embedded in the substrate so that there was a spread of heat from the device sidewalls to the substrate, which resulted in a little bit better heat dissipation.

-0.01 -0.005 0 0.005 0.01405

410

415

420

425

430

435

440

445

450

Distance (cm)

Tem

pera

ture

(K)

ISE-TCAD

FEMLAB

Fig. 2.29 Temperature profile along the cut line from ISE and FEMLAB Simulations.


32 32

2.8.2 Electro-thermal co-design issues for multi-fingered SiC MESFETs

For devices with a large gate periphery (many fingers) and operating at high power levels another big concern is that the temperature difference between the middle finger and the edge finger can be so large that linearity of the device and the response speed to signal are affected.

Fig. 2.30a-b show the simulated (using FEMLAB) 3D temperature distribution and temperature profile along a cut line on the top surface of a device (line marked in Fig. 2.30a) with ten fingers and a total DC power of 50 W. Only half of the device is simulated due to its

0 0.01 0.02 0.03 0.04340

360

380

400

420

440

460

Distance from the symmetry line ( cm )

Tem

pera

ture

( K

) ∆T = 30 K

Fig. 2.30b Temperature profile along a cut line on the top surface of aMESFET with 10 gate fingers.

Fig. 2.30a 3D temperature distribution of a MESFET with 10 gate fingers.


33

symmetry. The maximum temperature was observed to be 444 K and the maximum temperature difference reaches as high as 30 K.

Several useful methods can be applied to reduce the self-heating effects. One is to enlarge the gate pitch of the device in order to spread the heat more efficiently. That will of course cause increase of cost and decrease of yield due to the larger wafer area it takes. Fig. 2.31 and Table 2.6 illustrate the decrease in maximum temperature and the temperature difference (from 3D FEMLAB simulations) between the middle finger and the side finger when the gate pitch is enlarged for the 3-fingered MESFET shown in Fig 2.32b. There is a 60 K drop in device maximum temperature when the gate pitch is raised from 20 µm to 60 µm. The temperature difference between the middle finger and the side finger decreases almost linearly with increased gate pitch. With a gate pitch larger than 100 µm the temperature difference between fingers is negligible.

Table 2.6 Maximum device temperature and temperature difference between fingers for 3-fingerd devices with different gate pitches

Gate pitch (µm) Tmax (K) ∆T (K)

20 489 8

40 450 6

60 429 4

80 416 2

100 406 0

Fig. 2.31 Temperature profile along a cut line on the top surface of the 3-fingered MESFETshown in Fig 2.32 b with different gate pitches.

0 0.0025 0.005 0.0075 0.01 0.0125 0.015350

375

400

425

450

475

500

Distance to the symmetrical line ( cm )

Tem

pera

ture

( K

)

Gate pitch = 20 µmGate pitch = 40 µmGate pitch = 60 µmGate pitch = 80 µmGate pitch = 100 µm


34 34

An optimized finger layout will help to make best use of the wafer and to minimize the self-heating. Fig. 2.32a-d show the simulated 3D temperature distributions and maximum temperatures for four different finger layouts. Only 1/4 of the devices were simulated due to their symmetry. The chip surface area is 1.5·10-3 cm2, and the total power is 7.48 W for all four devices. The devices were designed to take the same chip surface area, 1.5·10-3 cm2, have the same finger length, 500 µm, and dissipate the same total amount of power, 7.48 W. The temperature difference between fingers was found to be negligible for all four cases due to the large gate pitches (>100 µm). Fig. 2.33 shows the largest variation in signal path for gate (referred as signal path later for simplicity), ds, via the maximum temperature, Tmax. The ten-fingered device shown in Fig. 2.32d (referred as layout d) gives the lowest maximum device temperature, which is beneficial, but the longest signal path, which is undesirable. Layout b gives the shortest signal path but the highest device temperature. Compare layout b and c, the two substrates are exactly the same size and shape, but there is a difference of 7K in maximum device temperature. The device shown in Fig. 2.32c suffers less self-heating but a little more signal delay. Both the maximum temperature and signal delay for the one-fingered device (layout a) are larger than the three-fingered device shown in Fig. 2.32c. Layout c seems to be better than the other three, but it should be mentioned that to optimized the layout design more thermal simulations needs to be done.

Fig. 2.32 3D temperature distributions of devices with different finger layouts.

a b

c d


35

The largest variation in signal path within the device should be smaller than 1/10 of the signal wave length, i.e. ds < λ /10. Otherwise the phase difference will lead to parts of the device operating in a different phase. This imposes a limitation on the frequency of input signal. The maximum signal frequency, fm, which can be handled by the devices with the four finger layouts (shown in Fig. 2.32a-d) are marked in the right side y-axis. For SiC MESFETs with a working frequency of 3GHz, the largest variation in signal path cannot be longer than 3.2 mm.

Fig. 2.33 Largest variation in signal path for gate, ds, and maximum allowedfrequency, fm, via the maximum temperature, Tmax.

385 390 395 400 405 410150

200

250

300

350

400

450

500

Tmax ( K )

d s ( µm

)

d

ca

b

f m (

GH

z )

38 41

52

20


36 36

2.8.3 Thermal design issues for commercial SiC MESFETs

In this study the self–heating effects on high power large area SiC MESFETs are investigated through thermal simulations. The junction temperature and temperature distribution are estimated. Different layouts of the active devices on the die are examined. Approaches to reduce the effects of self-heating on device performance are also suggested.

The layout drawing of the 1.5 mm power MESFET with twelve 125 µm gate fingers fabricated by CREE [23, 26] is illustrated in Fig. 2.34. It is a basic unit cell used as a building block for 3 mm, 6 mm, and 12 mm devices placed on a single die. At each corner of the cell, the source pad is grounded to the backside of the wafer with 100 µm diameter via holes to reduce feedback due to source bonding wires.

For the thermal simulations this unit cell with a power dissipation of 4.5 W (corresponding to a power density per unit gate periphery of 3 W/mm) is investigated. The surface area of the unit cell is 620Χ620 µm2 and the thickness is 200 µm. The gate pitch is 40 µm.

S D

S S

S

G

Fig. 2.34 X-band 1.5-mm power MESFET unit cell from CREE [26].


37

Fig.2.35 demonstrates a single-chip amplifier using 12 mm SiC power MESFETs with eight 1.5 mm unit cells

The equation to be solved in thermal simulations is the steady-state heat transfer equation

( )( ) 0=+∇⋅∇ HTTλ (2-47)

Because the channel is made within a very thin layer on top of the substrate, it is taken as a heat source at the boundary. The heat source term H in Eq. 2-49 is set to zero in the simulation domain. The thermal conductivity of the metal source via is assumed to be equal to that of silicon carbide for simplification of the simulation grids.

For the 1.5 mm MESFET unit cell, each finger was taken as a separate flat heat source generating heat in an area of 4Χ125 µm2 on top of the substrate. A fixed heat flux boundary condition was applied there. The heat flux is calculated by q = Qf/Af, where Qf is the heat generated by each finger (0.375 W) and Af is area of the heat source.

Fig. 2.35 Single-chip X-band hybrid amplifier using 12 mm SiC power MESFET from CREE [26].

Unit cell


38 38

For the 12 mm large transistor, it is not practical to take each finger as a separate heat source due to the dense mesh required near the finger region (see Fig. 2.36). Instead, we take the 12 fingers as one large flat heat source (white line marked in Fig. 2.36) with an area Ac equal to the total area occupied by the active device. The heat flux is calculated by q = Qc/Ac, where Qc is the heat generated by each unit cell (36 W).

A thermal resistance Rth, b was applied to the backside of the substrate. The backside heat flux is described as q = (1/rth, b)(Tamb-T), where the distributed thermal resistance rth, b is equal to the backside area Ab multiplied by the total backside to ambient thermal resistance Rth,b (approximately a sum of the thermal resistance between junction and case, and the thermal resistance between case and ambient).

Thermal isolation was applied to all other boundaries, since the heat transfer through free convection and thermal radiation at those boundaries is assumed to be negligible.

Thermal simulations were performed for the MESFET unit cell using FEMLAB [58]. The total junction to case thermal resistance Rth, jc = 3.6 K/W for the 8 unit cell device according to CREE datasheet for commercial SiC MESFETs. In the simulations the junction to ambient thermal resistance Rth, ja is assumed to be at least 3.6 K/W. For a unit cell a backside thermal resistance Rth = 8×3.6 = 28.8 K/W was applied.

Fig.2.36 Mesh and boundary condition of power MESFET unit cell.

q = const

Tamb

Rth

Fig. 2.37 Simulated temperature distribution for the MESFET unit cell (Wg=125 µm, gate pitch 40 µm).


39

The temperature distribution on the surface of the chip is shown in Fig. 2.37. A junction temperature of 456 K and a maximum temperature difference of 13 K within the active device area were obtained

Thermal simulations were also performed for two other gate finger layouts. One layout is with 6 fingers, double gate width Wg = 250 µm and gate pitch (80 µm). The other is with 24 fingers, half gate width Wg = 62.5 µm and gate pitch (20 µm). The total gate periphery and power dissipation are the same as for the unit cell. The temperature profiles along a cut line (marked in Fig. 2.37) on the chip surface for these three different finger layouts are illustrated in Fig. 2.38 for comparison.

The 6-fingered device layout gives better thermal solution, but needs larger wafer area for fabrication, thus causing higher cost and lower yield. The 24-fingered layout takes smaller wafer area, is helpful to reduce the cost and increase the yield, but higher junction temperature is reached.

Fig. 2.39 Simulated temperature distribution for the MESFET with two rows ofgate fingers (Wg = 125 µm, gate pitch 80 µm).

Fig. 2.38 Temperature profiles along the cut line on the chip surfaces ofthree different unit cells.


40 40

Other gate finger layouts were also checked. One of them is shown in Fig. 2.39. With two rows of gate fingers separately placed on the chip, the junction temperature and the maximum temperature difference within the active device area was reduced to 449 K and 8 K respectively. With this kind of layout more wafer area is need to locate the source vias. Besides it is tricky to fabricate devices with such layout because of the difficulty to arrange the source, gate and drain contacts. The improvement in heat dissipation is always at some costs. Trade-off must be done for a specific application.

In the thermal simulations for the 12 mm MESFET (with eight unit cells placed on a single die), a thermal resistance Rth of 3.6 K/W* was applied at the backside of the die (corresponding to an equally distributed thermal resistance rth as that for the unit cell). Three different ways to place the unit cell were investigated and the thermal simulation results are shown in Fig. 2.40.

It is observed that the same junction temperature of 452 K and minimum backside temperature of 428 K were obtained for all three cases. The reason is that there is little heat transfer between the neighboring cells. The heat generated by each cell spreads in the cell itself and is then dissipated through the backside of the die to the package. Therefore each unit cell is independent and the maximum temperature in each cell has the same value. This is a favorable feature since there will be no thermally related inhomogenity in device performance. A careful thermal design is helpful to achieve such independent cells.

Since it makes no difference in junction temperature how to place the unit cells in the die, the layout with eight cells lined in one row is the best choice because it makes it easy to arrange the gate and drain bond wires, and to connect the die to the amplifier circuit. The 12 mm MESFET mentioned in the following paragraphs has this layout.

Fig. 2.40 Simulated temperature distribution for three unit cell layouts.

452 K


41

Simulations were conducted for the 12 mm MESFET with different backside thermal resistance and the results are illustrated in Fig. 2.41. The maximum temperature difference within the die was estimated to be about 24 K with all backside resistance. The die thermal resistance is deduced based on the equation Tj-Tamb = Q (Rth, d+Rth, b) to be about 0.55 K/W, which is much smaller compared to the backside thermal resistance. In the equation Tamb = 300 K is the ambient temperature, Q = 36 W is the total power dissipation of the device, and Rth, d and Rth, b are the die thermal resistance and the backside thermal resistance respectively. A 6 K/W backside thermal resistance results in an average die temperature of about 250 °C, which is the soldering temperature of the die. Therefore the backside thermal resistance must not exceed this value.

Simulations for the 12 mm MESFET with different die thickness td and the same backside thermal resistance (3.6 K/W) show that it is not helpful to reduce the thickness of the die. Table 1 illustrates that the junction temperature started to increase when the die thickness is reduced to a certain value (referred to as critical thickness tc). This is due to the fact that the heat can not be spread efficiently in the lateral direction before being conducted into the heat sink. It is only useful to reduce the die thickness if it is much larger than tc.

Fig. 2.41 Maximum and minimum die temperature as a function of total thermalresistance.

Table 2.7 Die maximum temperatures for 12 mm MESFET with different

die thickness

td (µm) 50 75 100 125 150 200 300 400

Tj (K) 458 453 451 450 451 452 455 458


42 42

Due to the fact that the backside thermal resistance is dominating in the heat transfer process, the most efficient way to improve the heat dissipation is to reduce the thermal resistance from junction to case Rth, jc and from case to ambient Rth, ca. Wafer thinning may be performed anyway to make source vias easier to etch/deposit. There are two approaches currently being used to minimize the junction-to-case thermal resistance: decreasing the number and thickness of the layers between the chip and the heat spreader, and using more effective heat spreader substrate materials with high thermal conductivity, such as copper and aluminum nitride. In addition good attachment between layers is essential. The case-to-ambient thermal resistance depends on the surface area in contact with the fluid and the heat transfer coefficient between the contact surface and the fluid. A heat-sink is usually used to increase the surface area exposed to the fluid. The heat transfer coefficient can be raised by imposing forced air convection, liquid cooling, and even phase-change cooling.

43

3 Electro-Thermal Investigation of Silicon Carbide Power BJTs

The investigations of BJTs are summarized in this chapter and details can be found in paper V and VI.

First the device structure is described. Then the measurement results of the DC performance of the device are demonstrated. Finally the thermal simulation and measurement results are shown and discussed.

3.1 Device description

Silicon carbide bipolar junction transistors were processed on a four-epi-layer structure on 4H-SiC bulk material from CREE Research. A schematic structure of the SiC BJT is demonstrated in Fig. 3.1. The emitter and base contacts are on the top and the collector contact is on the backside. The substrate is n-doped to 8⋅1018 cm-3.

The dimensions and doping profiles of the device are described in Fig 3.2.

Fig. 3.1 Perspective of SiC BJT structure.

Emitter

Base

N+-emitter

P-base

N-collector

N-buffer

Substrate + backside contact

Emitter

BaseN+-emitter

P-base

N-collector

N-buffer

Substrate + backside contact

TEMITTER

TBASE

TCOLLECTOR

TBUFFER

TEMITTER = 0.5 um

TBASE = 0.3 um

TCOLLECTOR = 10 um

TBUFFER = 1 um

Nd (emitter) = 2⋅1019 cm-3

Na (base) = 6⋅1018 cm-3

Nd (collector) = 8⋅1015 cm-3

Fig. 3.2 Device structure and doping profile of 4H-SiC power BJT

Wei Liu 3 Electro-Thermal Investigation of Silicon Carbide Power BJTs

44 44

3.2 DC performance

Fig. 3.3 shows a diagram of the current gain, β, as a function of collector current, IC, measured at different temperatures. A strong decrease of current gain with increasing temperature was seen. The measured maximum current gain is 9.5 at room temperature, 6.2 at 100 °C and 4.3 at 300 °C. There are mainly two reasons for the decrease of current gain. One is that the hole concentration in the base area increases with temperature due to the more complete ionization, resulting in lower emitter injection efficiency. The other reason is that the base electron mobility decreases with temperature, which results in decreased current gain due to a lowered base transport factor. The lifetime variation with temperature may also affect the current gain. The self-heating effect on DC performance will be described in section 3.3.

3.3 Extraction of junction temperature

By assuming that the current gain is only a function of temperature the junction temperature, Tj, can be extracted from the collector current voltage diagram [59]. This diagram is shown in Fig. 3.4. A plot of the collector current, IC, as function of collector-emitter voltage, VCE, with a constant base current, IB, at three different ambient temperatures is needed. Here IC, and therefore also the current gain, β, decreases with increasing VCE voltages due to strong self-heating which causes the increase of the device temperature. The drop in β with increasing temperature is explained in section 3.2.

Fig. 3.3 Current gain measured at different temperatures

100 101 1020

2

4

6

8

10

IC [mA]

Cur

rent

gai

n

25 °C100 °C200 °C300 °C

100 A/cm2


45

The extraction of the junction temperature requires that intersections can be found between a line of constant IC and three VCE sweeps with the same IB at different ambient temperatures. As a result, the temperature interval usually has to be quite small. From measurements at temperatures of 25 °C, 50 °C, and 75 °C, this Tj extraction was possible.

The current gain, β = IC/IB, at the three intersections are identical because the collector current, IC, has the same value at these three points (IB is also the same). Assuming that the current gain is only a function of junction temperature, the junction temperature must also be identical at the intersections. We now have the three ambient temperatures, Tamb,i, and associated power dissipations, Pdiss,i, that produce the same mean temperature in the device.

idissithiambj PRTT ,,, += (3-1)

The subscript, i, represent the three intersections (i = 1, 2, 3), and Rth is the thermal resistance between the junction and the ambient. To solve the problem we need to reduce the number of unknown variables. It is proposed that the thermal resistance, for fixed junction temperature, is a linear function of the ambient temperature [59].

ambjth BTATR +=)( (3-2)

Substituting Eq. 3-2 into Eq. 3-1, we get three equations for the three unknowns Tj, A, and B.

The extracted Tj for two lines are shown on the right axis in the Fig. 3.4, where the maximum and minimum extracted value are 154 °C and 94 °C, respectively. The maximum value of 154 °C was obtained for a power level of 5.5 W. The extracted thermal resistance, Rth, at a junction temperature of 154 °C and at a room ambient temperature (25 °C) was 24 cm2.K/W.

0 20 40 60 80 1000

20

40

60

80

100

VCE (V)

I C (m

A)

25 °C50 °C75 °C

15494

Junc

tion

tem

pera

ture

( °C

)

Fig. 3.4 IC versus VCE for three ambient temperatures and constant

IB = 9


46 46

3.4 Chip level thermal simulations

3D thermal simulations were performed using FEMLAB [58] for a SiC BJT located on a 1.0x1.0x0.035 cm chip (see Fig. 3.5) cut from the wafer. The size of the BJT was 400x300x10 µm. There were 8x8 such BJTs fabricated on the same chip, but only one transistor was active.

The control equation for thermal simulation is the heat transfer equation

( )( ) 0=+∇⋅∇ HTTλ (3-3)

where λ is the thermal conductivity and H is the heat generated per unit volume.

The active device was modeled as a source of heat flux in the boundary condition for the top surface of the chip. The backside thermal resistance between the substrate and the chuck was estimated to 16 cm2·K/W based on the comparison of the measured maximum surface temperature and the simulated temperature for one power level. Good agreement was seen for the temperature profiles and the maximum temperatures for all other power dissipation levels applying this thermal resistance. The SiC thermal conductivity is 3-5 W/cm⋅K, and is dependent on the temperature and the doping of the material. The negative slope of the measured VCE diagrams can be used to model the thermal conductivity if the lifetime is assumed to be constant. The closest match was seen for a thermal conductivity of 4.3 W/cm⋅K at 300 K with a 1/T dependence on temperature. This conductivity was applied in the 3D simulations. The simulated temperature profile on the surface of the chip for a power level of 5.5 W is shown in Fig. 3.5. The junction temperature is 157 °C (430 K). This compares favorably to the junction temperature of 154 °C from the IV-extraction (see section 3.3). More simulation results are shown in section 3.6.

430.8929

Fig. 3.5 Surface temperature at a power level of 5.5 W. (K)


47

3.5 Chip temperature measurements

The thermal images of the chip surface with a device operating at five power levels were taken using an infrared camera [60]. An infrared camera is a non-contact device that detects infrared energy (heat) and converts it into an electronic signal, which is then processed to produce a thermal image on a video monitor and can be used to perform temperature calculations.

The results for two power dissipation levels 1.92, and 3.82 W are illustrated in Fig 3.6. The different power levels were achieved by changing the collector voltage and base current (P = IC × VCE). A temperature increase of 36 °C was observed when the power dissipation is raised from 1.92 W to 3.82 W. More measurement results can be found in section 3.6 for comparison with FEMLAB simulations.

1.92 W

(K)

3.82 W

(K)

Fig. 3.6 Captured temperature profiles at two power levels using infrared camera.


48 48

3.6 Comparison of simulations and measurements

The comparisons between the simulation and measurement are shown in Fig. 3.7-3.9. Fig. 3.7 shows the temperature profiles along a cut line on the top surface of the chip (line marked in Fig. 3.8-3.9) for five power levels. The smooth lines are from simulation and the rough lines are from the infrared camera. The five power values are 3.82, 3.40, 2.64, 2.27, 1.92 W from top to bottom. Good agreement exists between simulation and measurement for all five power-levels. The differences are probably caused by the temperature dependent backside thermal resistance and the errors from the measurement of the collector current. Increases in maximum temperature and temperature difference on the surface of the chip with increasing power were observed. Due to the interference of the metal layer, the measured temperature profiles from the infrared camera are not smooth, and at the maximum temperature location, there is a large dip due to the metal layer interference (the metal layer has a lower emissivity in infrared imaging). The thermal image from infrared camera (shown in Fig. 3.8) and the 3D simulation temperature contour (shown in Fig. 3.9) on the chip surface with a transistor operating at a power level of 3.82 W are compared. It is observed that the temperature difference within the device is not large even for high power dissipation due to the high thermal conductivity and the small size of the device. For a power level of 3.82 W the difference is less than 10 °C. The thermal resistance of the chip itself is much smaller than the backside thermal resistance.

Fig. 3.7 Comparison of temperature profile along the cut line on the surface at fivepower levels. The smooth lines are for simulations and the rough lines are for themeasurements. The power levels are 3.82, 3.40, 2.64, 2.27, 1.92 W from top to thebottom for each pair of curves.


49

For the cut chip (die), the lateral heat spreading is limited by the chip surface area, the junction temperature and the temperature difference in the device are all expected to be higher than for the larger chip shown in Fig. 3.10. Fig. 3.11 shows the cross section temperature for one die, assuming the active device size, the power dissipation and the total thermal resistance from the backside are all the same as for the larger chip. A junction temperature of 413 K (25 K higher than for the larger chip) and a temperature difference of 18 K (8 K higher than for the larger chip) were witnessed. This illustrates that thermal

Fig. 3.9 Simulated temperature profile at a power level of 3.82 W.

(K)

Fig. 3.8 Captured temperature profile at a power dissipation of 3.82 W using aninfrared camera.

(K)


50 50

analysis is necessary when designing the mask for fabrication of high power devices to make sure the die size for packaging is big enough to avoid severe self-heating. It is also notice that the thermal resistance of the chip itself is much smaller than the backside thermal resistance. Therefore in order to make full use of the high power-handling capability of SiC devices advanced packaging and bonding technology need to be developed to minimize the self-heating effects, although substrate thinning may still be considered [61].

Fig. 3.10 Cross section temperature at 3.82 W. Chip size 1.0x1.0x0.035 cm3.

Active device

(K)

Fig. 3.11 Cross section temperature at 3.82 W. Chip size 0.12x0.11x0.035 cm3.

(K)

51

4 Summary and Future Work

In this thesis the thermally related electrical behaviour of two types of high power silicon carbide transistors – 4H-SiC metal semiconductor field-effect transistors (MESFETs) and 4H-SiC bipolar junction transistors (BJTs) has been investigated by performing electro-thermal simulations and measurements. The junction temperatures of devices operating at high power levels have been estimated through electro-thermal simulations, thermal simulations, and temperature measurements using infrared camera. A couple of useful ways to reduce the junction temperature were discussed.

Two-dimensional electro-thermal simulations using commercial software MEDICI and ISE have been performed and DC and S-parameter measurements have been conducted to study the performance degradation of 4H-SiC RF Power MESFETs caused by self-heating and high operating temperature. Both the measurements and simulations showed that temperature is a very important factor, which has profound influence on device performance in term of breakdown voltage, saturation current, power density, high frequency current gain and power gain, cut-off frequency and maximum frequency of oscillation. Experimental results show a 38% reduction in drain saturation current, and 29% and 41% drops in fT and fmax respectively when the operating temperature was increased from 25 to 250 °C The predicted DC and HF performance from electro-thermal simulations is better to some extent than the measured DC and HF performance due to the simplification and idealization of the simulation models. Traps, for instance, which are believed to contribute to the instabilities of the devices performance, were not considered in the simulations. Thermal simulations were also applied to predict the junction temperatures and temperature distributions of devices on chips. The thermal simulation results agree well with the electro-thermal simulation results. Thermal related issues for design of finger layout and unit cell layout for large area multi-fingered SiC MESFETs were discussed. Trapping phenomena in the MESFETs were experimentally analyzed.

For SiC BJTs electrical measurements were performed to analyze the DC characteristics of devices undergoing self-heating or operating in a high temperature environment. A large decrease of current gain with increase of temperature was observed. Three different ways to predict the junction temperature were discussed: extraction from collector current voltage diagram, 3D thermal simulation, and thermal imaging. The junction temperature obtained using these three methods was found to agree well with each other.

For design and characterization of high power devices self-heating should be taken into consideration. However, simulation of devices with self-heating is time consuming and it is difficult to achieve convergence. For devices with short gate width (few fingers) the temperature difference in the active device region turned out to be small due to the high thermal conductivity of the SiC material. In this case the device can be regarded as having a uniform temperature (the junction temperature corresponding to the power level). Thermal simulation can be used to predict the junction temperature and isothermal electrical simulation can be applied to get the electrical characteristics at this temperature. For large area high power devices an optimized layout of fingers and unit cells are crucial to achieve high power and high frequency capabilities predicted in SiC materials.

Experimental results show that the traps in the MESFET device structure have large influence on the device performance. In order to get more realistic simulation results, traps on the

Wei Liu 4 Summary and Future Work

52 52

surface and in the substrate of the devices need to be taken into account in the simulation models. More experimental work is necessary to get further understanding of the trapping/de-trapping phenomena and to provide useful parameters for simulations with consideration of traps.

53

References

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59

Appendix Material properties and parameters used in device simulations

Dielectric permittivity ε

Electron affinity χ (eV)

Density (g/cm3)

Effective density of state

NC300 (#/cm3)

NV300 (#/cm3)

Bandgap

Eg300 (eV)

αEg (eV/K)

βEg (K)

Auger recombination

Cn (cm6/s)

Cp (cm6/s)

Incomplete ionization

GVB

GCB

EAB (eV)

EDB(eV)

Electron impact inonization

an0 (#/cm)

an1 [#/cm⋅K]

an2 [#/cm⋅K2]

ECN (V/cm)

αn,ii

Hole impact ionization

ap0 (#/cm)

ap1 [#/cm⋅K]

ap2 [#/cm⋅K2]

ECP (V/cm)

αp,ii

9.98

3.7

3.21e-3

1.66e19

3.30e19

3.25

3.3e-4

0

5.0e-31

2.0e-31

4

2

0.191

0.069

-4.184e6

1.506e6/300.0

7.628e6/9.0e4

2.58e7

1

3.1e7

-1.083e7/300.0

1.469e6/9.0e4

1.9e7

1

Wei Liu Appendix

60 60

Arora model for low field mobility

µs,nmin (cm2/V⋅s)

µs,n∆ (cm2/V⋅s)

Cn,ref (#/cm3)

an

αTn

µs,pmin (cm2/V⋅s)

µs,p∆ (cm2/V⋅s)

Cp,ref (#/cm3)

ap

αTp

Field dependant mobility

βn

βp

Vn (cm/s)

Vp (cm/s)

αn

αp

Thermal conductivity

αth(W/cm⋅K)

βth

Shottky barrier (eV)

Contact resistance (Ω⋅cm2)

0

947

1.94e17

0.61

-2.15

15.9

108.1

1.76e19

0.34

-2.15

2.0

1.0

2.2e7

2.2e7

0.5

0.5

4.3

1

1.08

10-4

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