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ELCT 501:
Digital System Design
Lecture 8: System Design
Dr. Mohamed Abd El Ghany,
Department of Electronics and Electrical Engineering
Algorithmic State Machine (ASM)
2 Dr. Mohamed Abd el Ghany
Department of Electronics and Electrical Engineering
ELCT 501: Digital System
Design
Winter 2011
For large machines, the designers often use
a different form of representation, called the
algorithmic state machine chart.
An ASM chart is a type of flowchart that can
be used to represent the state transitions
and generated outputs for an FSM.
Elements used in ASM Charts
3 Dr. Mohamed Abd el Ghany
Department of Electronics and Electrical Engineering
ELCT 501: Digital System
Design
Winter 2011
Output
signals or
actions
(Moore type)
Condition
expression
Conditional outputs or
actions (Mealy type)
State name
0 (false) 1 (true)
State box Decision box
Conditional output box
From FSM to ASM chart
4 Dr. Mohamed Abd el Ghany
Department of Electronics and Electrical Engineering
ELCT 501: Digital System
Design
Winter 2011
A
Reset
w 0
1 B
w 0
1
Z
C
w 0 1
From FSM to ASM chart
5 Dr. Mohamed Abd el Ghany
Department of Electronics and Electrical Engineering
ELCT 501: Digital System
Design
Winter 2011
A
Reset
w 0
1 B
w 0 1
z
Design Example
6 Dr. Mohamed Abd el Ghany
Department of Electronics and Electrical Engineering
ELCT 501: Digital System
Design
Winter 2011
Design A Bit-Counting Circuit to count the
number of bits in a register
B = 0;
While A ≠ 0 do
if a0 = 1 then
B= B+1;
end if;
Right-shift A;
End while;
Pseudo-
code for
the bit
counter
ASM chart for the
pseudo-code
7 Dr. Mohamed Abd el Ghany
Department of Electronics and Electrical Engineering
ELCT 501: Digital System
Design
Winter 2011
B = 0;
While A ≠ 0 do
if a0 = 1 then
B= B+1;
end if;
Right-shift A;
End while;
B <- 0
S1
Reset
s 0
1
S2
A=0?
0
1
Shift right A
Load A
a0 0
B<-B+1
Done
s
1
1
0
S3
Datapath for the ASM chart
8 Dr. Mohamed Abd el Ghany
Department of Electronics and Electrical Engineering
ELCT 501: Digital System
Design
Winter 2011
Shift register
Data
Counter
Clock
L
E
w
L
E
0
log2n n
log2n
LB
EB
0
LA
EA
A
n
B
a0 z
ASM chart for the
control circuit
9 Dr. Mohamed Abd el Ghany
Department of Electronics and Electrical Engineering
ELCT 501: Digital System
Design
Winter 2011
LB
S1
Reset
s 0
1
S2
z
0
1
EA
a0 0
EB
Done
s
1
1
0
S3
VHDL for the bit-
counting circuit
10 Dr. Mohamed Abd el Ghany
Department of Electronics and Electrical Engineering
ELCT 501: Digital System
Design
Winter 2011
Part 1
VHDL for the bit-
counting circuit
11 Dr. Mohamed Abd el Ghany
Department of Electronics and Electrical Engineering
ELCT 501: Digital System
Design
Winter 2011
Part 2
VHDL for the bit-
counting circuit
12 Dr. Mohamed Abd el Ghany
Department of Electronics and Electrical Engineering
ELCT 501: Digital System
Design
Winter 2011
Part 3
VHDL for the bit-
counting circuit
13 Dr. Mohamed Abd el Ghany
Department of Electronics and Electrical Engineering
ELCT 501: Digital System
Design
Winter 2011
Part 4
ASM chart for the
multiplier
16 Dr. Mohamed Abd el Ghany
Department of Electronics and Electrical Engineering
ELCT 501: Digital System
Design
Winter 2011
P <- 0
S1
Reset
s 0
1
S2
B=0?
0
1
Shift left A,
Shift right B
Load A
Load B
b0 0
P<-P+A
Done
s
1
1
0
S3
Binary
1101
x 1011
--------------
1101
1101
0000
1101
---------------
10001111
Datapath circuit for the multiplier
17 Dr. Mohamed Abd el Ghany
Department of Electronics and Electrical Engineering
ELCT 501: Digital System
Design
Winter 2011
Shift- left
register
Data A
Clock
L
E
n
LA
EA
B
n
b0 z
Shift-right
register
Data B
L
E
n
LB
EB
n
0
+
2n A
sum 2n 2n
0
1 0 Psel
register E EP
2n
P
2n DataP
ASM chart for the
multiplier control circuit
18 Dr. Mohamed Abd el Ghany
Department of Electronics and Electrical Engineering
ELCT 501: Digital System
Design
Winter 2011
Psel=0, EP
S1
Reset
s 0
1
S2
z
0
1
Psel=1,
EA, EB
b0 0
EP
Done
s
1
1
0
S3
VHDL for the
multiplier circuit
19 Dr. Mohamed Abd el Ghany
Department of Electronics and Electrical Engineering
ELCT 501: Digital System
Design
Winter 2011
Part 1
VHDL for the
multiplier circuit
20 Dr. Mohamed Abd el Ghany
Department of Electronics and Electrical Engineering
ELCT 501: Digital System
Design
Winter 2011
Part 2
VHDL for the
multiplier circuit
21 Dr. Mohamed Abd el Ghany
Department of Electronics and Electrical Engineering
ELCT 501: Digital System
Design
Winter 2011
Part 3
VHDL for the
multiplier circuit
22 Dr. Mohamed Abd el Ghany
Department of Electronics and Electrical Engineering
ELCT 501: Digital System
Design
Winter 2011
Part 4
Clock Synchronization
23 Dr. Mohamed Abd el Ghany
Department of Electronics and Electrical Engineering
ELCT 501: Digital System
Design
Winter 2011
Clock
enable
circuit
clock
Dat
a D Q
Q’ E
Clock Skew: If the circuit of clock enable is used,
then the flip-flops without the enable
input will observe changes in the
clock signal slightly earlier than the
flip-flops that have the enable input.
This situation , in which the clock
signal arrives at different times at
different flip-flops, is known as clock
skew.
Similar problems arise in a chip in
which the clock signal is distributed
to different flip-flops by wires whose
lengths vary appreciably.
Clock Synchronization
24 Dr. Mohamed Abd el Ghany
Department of Electronics and Electrical Engineering
ELCT 501: Digital System
Design
Winter 2011
Clock Skew: For proper operation of
synchronous sequential
circuits, it is essential to
minimize the clock skew as
much as possible.
The clock signal is
distributed to the flip-flops
such that the length of wire
between each flip-flop and
clock source is the same.
An H tree clock
distribution network