ELCT201: DIGITAL LOGIC DESIGN Dr. Eng. Haitham Omran, haitham.omran@guc.edu.eg

Dr. Eng. Wassim Alexan, wassim.joseph@guc.edu.eg

Lecture 9

هــ 1439محرم

Winter 2018

Following the slides of Dr. Ahmed H. Madian

COURSE OUTLINE

1. Introduction

2. Gate-Level Minimization

3. Combinational Logic

4. Synchronous Sequential Logic

5. Registers and Counters

6. Memories and Programmable Logic

2

LECTURE OUTLINE

• Registers

• Structure and Definition

• Serial Registers

• Parallel Registers

• Serial Adder

• Universal Shift Register

• Universal Shift Register: Applications

3

REGISTERS

4

• A register is a memory element that can be used to store more than a single bit of information

• A register is made up of several flip-flops with common control signals that control the movement of data to and from the registers

• An 𝑛-bit register consists of 𝑛 flip-flops and is capable of storing an 𝑛-bit word

• The main operations on a register are the same as for any storage element, namely: • load or store: input new data into the register

• Read: retrieve the stored data in the register

SERIAL I/P AND O/P REGISTERS

5

𝐶𝑙𝑘

𝑆𝑒𝑟𝑖𝑎𝑙 𝑖𝑛𝑝𝑢𝑡

𝑆𝑒𝑟𝑖𝑎𝑙 𝑜𝑢𝑡𝑝𝑢𝑡

𝐼𝑛 𝑄1 𝑄2 𝑄3 𝑄4

= 𝑜𝑢𝑡

𝑡0 1 0 0 0 0

𝑡1 0 1 0 0 0

𝑡2 1 0 1 0 0

𝑡3 1 1 0 1 0

𝑡4 1 1 1 0 1

𝑡5 0 1 1 1 0

𝑡6 0 0 1 1 1

𝑡7 0 0 0 1 1

𝑄1 𝑄2 𝑄3

PARALLEL I/P AND O/P REGISTERS

6 𝐶𝑙𝑘 𝐶𝑙𝑒𝑎𝑟

𝐼3

𝐼2

𝐼1

𝐼0

𝐴3

𝐴2

𝐴1

𝐴0

But what if we do not want to load new

data with every clock cycle? What if we

want to keep the same data in the

register?

• With every positive edge of the clock,

new data is loaded into the register, in a parallel fashion

PARALLEL I/P AND O/P REGISTERS

7 𝐶𝑙𝑘

𝐿𝑜𝑎𝑑

𝐼3

𝐼2

𝐼1

𝐼0

𝐴3

𝐴2

𝐴1

𝐴0

This design allows us to:

1. Either load new

data bits into the

register (Load is 1)

2. Or keep the old

outputs, by

recirculating them

back into the FF

inputs (Load is 0)

SERIAL ADDITION USING REGISTERS

8

𝐶𝑙𝑘

𝑆ℎ𝑖𝑓𝑡 𝑐𝑜𝑛𝑡𝑟𝑜𝑙

𝑆𝑒𝑟𝑖𝑎𝑙 𝑖𝑛𝑝𝑢𝑡

𝐶𝑙𝑒𝑎𝑟

Circuit implementation

using a FA and a 𝐷 FF

SERIAL ADDITION USING REGISTERS

9

• Initially, register 𝐴 holds the augend and register 𝐵 holds the addend, while the carry FF is cleared to 0

• The outputs 𝑆𝑂 of 𝐴 and 𝐵 provide a pair of significant bits for the full adder at 𝑥 and 𝑦. Output 𝑄 of the FF provides the input carry at 𝑧

• The 𝑠ℎ𝑖𝑓𝑡 𝑐𝑜𝑛𝑡𝑟𝑜𝑙 enables both registers and the carry FF, so that at the next clock pulse, both registers are shifted once to the right, the sum bit from 𝑆 enters the left-most FF of 𝐴, and the output carry is transferred into FF 𝑄

• The 𝑠ℎ𝑖𝑓𝑡 𝑐𝑜𝑛𝑡𝑟𝑜𝑙 enables the registers for a number of clock pulses equal to the number of bits in the registers

• For each succeeding clock pulse, a new sum bit is transferred to 𝐴, a new carry is transferred to 𝑄, and both registers are shifted once to the right

• This process continues until the 𝑠ℎ𝑖𝑓𝑡 𝑐𝑜𝑛𝑡𝑟𝑜𝑙 is disabled

SERIAL ADDITION USING REGISTERS

10

• Thus, the addition is accomplished by passing each pair of bits together with the previous carry through a single full adder circuit and transferring the sum, one bit at a time, into register 𝐴

• Initially, register 𝐴 and the carry FF are cleared to 0, and then the first number is added from 𝐵

• While 𝐵 is shifted through the full adder, a second number is transferred to it through its serial input

• The second number is then added to the contents of register 𝐴 while a third number is transferred to serially into register 𝐵

• This can be repeated to perform the addition of 2, 3 or more 4-bit numbers and accumulate their sum in register 𝐴 (assuming that register 𝐴 is built of 4 FFs only)

SERIAL ADDITION USING REGISTERS

11

𝐶𝑙𝑘

𝑆ℎ𝑖𝑓𝑡 𝑐𝑜𝑛𝑡𝑟𝑜𝑙

𝑆𝑒𝑟𝑖𝑎𝑙 𝑖𝑛𝑝𝑢𝑡

𝐶𝑙𝑒𝑎𝑟

Circuit implementation using a 𝐽𝐾 FF

𝐽𝑄 = 𝑥𝑦

𝐾𝑄 = 𝑥 + 𝑦 ′

𝑆 = 𝑥 ⊕ 𝑦 ⊕ 𝑄

FF input and output equations

SERIAL ADDITION USING REGISTERS

12

State table for the full adder implementation using a 𝐽𝐾 FF

UNIVERSAL SHIFT REGISTER

13

This is the most general case of a register and has the following capabilities:

1. A clear control to clear the register to 0

2. A Clk input to synchronize the operations

3. A shift-right control to enable the shift-right operation and the serial input and output lines associated with the shift right

4. A shift-left control to enable the shift-left operation and the serial input and output lines associated with the shift left

5. A parallel-load control to enable a parallel transfer and the n input lines associated with the parallel transfer

6. n parallel output lines

7. A control state that leaves the information in the register unchanged

UNIVERSAL SHIFT REGISTER

14

𝐹𝑢𝑛𝑐𝑡𝑖𝑜𝑛 𝑡𝑎𝑏𝑙𝑒

𝐺𝑟𝑎𝑝ℎ𝑖𝑐 𝑠𝑦𝑚𝑏𝑜𝑙

𝑠0 𝑠1

𝐶𝑙𝑘

𝐶𝑙𝑒𝑎𝑟

𝑃𝑎𝑟𝑎𝑙𝑙𝑒𝑙 𝐼 𝑖𝑛𝑝𝑢𝑡𝑠

𝑃𝑎𝑟𝑎𝑙𝑙𝑒𝑙 𝐴 𝑜𝑢𝑡𝑝𝑢𝑡𝑠

𝑀𝑆𝐵_𝑖𝑛 𝐿𝑆𝐵_𝑖𝑛

15

𝑠1

4 − 𝑏𝑖𝑡 𝑈𝑛𝑖𝑣𝑒𝑟𝑠𝑎𝑙 𝑆ℎ𝑖𝑓𝑡 𝑅𝑒𝑔𝑖𝑠𝑡𝑒𝑟

𝑠0

𝐴3 𝐴2 𝐴1 𝐴0

𝐼1 𝐼0 𝐼2 𝐼3

𝐶𝑙𝑘

𝐶𝑙𝑒𝑎𝑟

𝑆𝑒𝑟𝑖𝑎𝑙 𝑖𝑛𝑝𝑢𝑡 𝑓𝑜𝑟

𝑠ℎ𝑖𝑓𝑡 − 𝑙𝑒𝑓𝑡

𝑃𝑎𝑟𝑎𝑙𝑙𝑒𝑙 𝐼𝑛𝑝𝑢𝑡𝑠

𝑃𝑎𝑟𝑎𝑙𝑙𝑒𝑙 𝑂𝑢𝑡𝑝𝑢𝑡𝑠

𝑆𝑒𝑟𝑖𝑎𝑙 𝑖𝑛𝑝𝑢𝑡 𝑓𝑜𝑟

𝑠ℎ𝑖𝑓𝑡 − 𝑟𝑖𝑔ℎ𝑡

UNIVERSAL SHIFT REGISTER

16

• Each of the four multiplexers has two common selection inputs 𝑠1 and 𝑠0

• Input 0 in each mux is selected when 𝑠0𝑠1 = 00, input 1 is selected when 𝑠0𝑠1 = 01, and similarly for the other two inputs

• The selection inputs control the mode of operation of the shift register, according to the function table

• When 𝑠0𝑠1 = 00, the present value of the register is applied to the 𝐷 inputs of the FF, so that the output recirculates to the input

• The next clock edge transfers into each FF the binary value it held previously, and no change of state occurs

UNIVERSAL SHIFT REGISTER

17

• When 𝑠0𝑠1 = 01, terminal 1 of the mux inputs has a path to the 𝐷 inputs of the FFs. This causes a shift-right operation, with the serial input transferred into FF 𝐴3

• When 𝑠0𝑠1 = 10, a shift-left operation results, with the other serial input going into FF 𝐴0

• Finally, when 𝑠0𝑠1 = 11, the binary info on the parallel input lines is transferred into the register simultaneously during the next clock cycle

UNIVERSAL SHIFT REGISTER: APPLICATIONS

18

• Shift registers are often used to interface digital systems located remotely from each other

• For example, if we need to transmit an 𝑛 −bit message between two distant points, it will be expensive to use 𝑛 lines to transmit the 𝑛 bits in parallel

• It is more economical to use a single line and transmit the message serially, one bit at a time

• The transmitter accepts the 𝑛 −bit message in parallel into a shift register and then transmits the data serially along the common line

UNIVERSAL SHIFT REGISTER: APPLICATIONS

19

• The receiver accepts the message serially into a shift register

• When all 𝑛 bits are received, they can be taken from the outputs of the register in parallel

• Thus, the transmitter performs a parallel-to-serial conversion of the message and the receiver does a serial-to-parallel conversion