Integrated Circuit Design ELCT 701 - eee.guc.edu.egeee.guc.edu.eg/Courses/Electronics/ELCT701 Integrated Circuits... · Inverter Study of the transient response ... Calculating for

Integrated Circuit Design ELCT 701

(Winter 2017)

Lecture 3: CMOS InverterDr. Eman Azab

Assistant Professor

Office: C3.315

E-mail: [email protected]

Dr. Eman Azab

Electronics Dept., Faculty of IET

The German University in Cairo

1

CMOS InverterCircuit Structure and Static Characteristics

Dr. Eman Azab



2

CMOS Inverter

Dr. Eman Azab



3

General Circuit Structure:

Enhancement NMOS and

PMOS transistors are the

inverter driver Transistors

Drivers Bulks (Substrate) are

connected to their Sources

(VSB,driver=0,Constant VTo,driver)

Push-Pull Circuit Operation

Steady-state power

dissipation is almost zero

(due to leakage currents)

Very sharp VTC

Vin = VGS,n Vout = VDS,n

− VDD − Vin = VGS,𝑝 − VDD − Vout = VDS,𝑝

ID,n = ID,𝑝

CMOS Inverter

Dr. Eman Azab



4

CMOS Inverter VTC

Vin = VGS,n Vout = VDS,n

− VDD − Vin = VGS,𝑝 − VDD − Vout = VDS,𝑝

ID,n = ID,𝑝

CMOS Inverter

Dr. Eman Azab



5

CMOS Inverter VTC

Region A: NMOS off &

PMOS Linear (VOH)

Region B: NMOS Sat

and PMOS Linear (VIL)

Region C: Both are Sat

(Vth)

Region D: NMOS linear

and PMOS is sat (VIH)

Region E: NMOS linear

and PMOS off (VOL)

Vin = VGS,n Vout = VDS,n− VDD − Vin = VGS,𝑝 − VDD − Vout = VDS,𝑝

CMOS Inverter

Dr. Eman Azab



6

Summary of VTC :

Note that the term KR affects the

VTC of the inverter significantly

𝐕𝐎𝐇 = 𝐕𝐃𝐃

𝐕𝐈𝐇 =𝐕𝐃𝐃 + 𝐕𝐓𝐨,𝐩 + 𝐊𝐑 𝟐𝐕𝐨𝐮𝐭 + 𝐕𝐓𝐨,𝐧

𝟏 + 𝐊𝐑

𝐕𝐈𝐋 =𝟐𝐕𝐨𝐮𝐭 − 𝐕𝐃𝐃 + 𝐕𝐓𝐨,𝐩 + 𝐊𝐑𝐕𝐓𝐨,𝐧

𝟏 + 𝐊𝐑

𝐕𝐎𝐋 = 𝟎𝐊𝐑 =

𝐊𝐧

𝐊𝐩

𝐕𝐭𝐡 =𝐕𝐓𝐨,𝐧 +

𝟏𝐊𝐑

𝐕𝐃𝐃 + 𝐕𝐓𝐨,𝐩

𝟏 +𝟏𝐊𝐑

CMOS Inverter

Dr. Eman Azab



7

Power Dissipation:

Steady-state power is almost zero

The maximum drain Current is at Vth

where both transistors are sat

𝐊𝐑 =𝐊𝐧

𝐊𝐩

CMOS Inverter

Dr. Eman Azab



8

Design of CMOS Inverter

The important parameter of the

design of CMOS inverter is Vth

For ideal VTC: Vth should be half the

supply

𝐊𝐑 =𝐊𝐧

𝐊𝐩

𝐕𝐭𝐡 =𝐕𝐓𝐨,𝐧 +

𝟏𝐊𝐑

𝐕𝐃𝐃 + 𝐕𝐓𝐨,𝐩

𝟏 +𝟏𝐊𝐑

𝟏

𝐊𝐑=

𝐕𝐭𝐡 − 𝐕𝐓𝐨,𝐧𝐕𝐃𝐃 + 𝐕𝐓𝐨,𝐩 − 𝐕𝐭𝐡

𝐊𝐑 =𝐕𝐃𝐃 + 𝐕𝐓𝐨,𝐩 − 𝐕𝐭𝐡

𝐕𝐭𝐡 − 𝐕𝐓𝐨,𝐧

𝟐

CMOS Inverter

Dr. Eman Azab



9

Design of CMOS Inverter (Cont.)

For ideal VTC: Vth should be half the

supply

If we set the threshold voltages of

the NMOS and PMOS to be equal,

then:

𝐊𝐑 =𝐊𝐧

𝐊𝐩

𝐕𝐭𝐡 =𝐕𝐃𝐃𝟐

𝐊𝐑 =𝟎. 𝟓𝐕𝐃𝐃 + 𝐕𝐓𝐨,𝐩

𝟎. 𝟓𝐕𝐃𝐃 − 𝐕𝐓𝐨,𝐧

𝟐

𝐊𝐑 =𝐊𝐧

𝐊𝐩= 𝟏 Symmetric Inverter

CMOS Inverter

Dr. Eman Azab



10

Summary of VTC of Symmetric

Inverter:

𝐕𝐈𝐇 =𝟏

𝟖𝟓𝐕𝐃𝐃 − 𝟐𝐕𝐓𝐨,𝐩

𝐕𝐈𝐋 =𝟏

𝟖𝟑𝐕𝐃𝐃 + 𝟐𝐕𝐓𝐨,𝐩

𝐊𝐑 =𝐊𝐧

𝐊𝐩= 𝟏

𝐍𝐌𝐋 = 𝐕𝐈𝐋-𝐕𝐎𝐋 = 𝐕𝐈𝐋

𝐍𝐌𝐇 = 𝐕𝐎𝐇-𝐕𝐈𝐇 = 𝐕𝐃𝐃 − 𝐕𝐈𝐇=𝐕𝐈𝐋

CMOS InvertersDynamic Behavior

Dr. Eman Azab



11

Introduction

Dr. Eman Azab



12

Dynamic Behavior of CMOS

Inverter

Study of the transient response

of the CMOS Inverter

The Intrinsic capacitances of

the CMOS inverter takes time

to charge and discharge when

the input voltage change

This charging/discharging

process introduces delay in the

signal propagation through the

inverter

Our objective in this lecture is

to investigate the effect of

these capacitances on the

inverter functionality

Introduction

Dr. Eman Azab



13

Intrinsic Capacitances ofCMOS Inverter

Enh. MOS has intrinsicparasitic capacitances

They are mainlyoriginated from:

1. MOS physical structure(gate and OverlapCaps.)

2. Channel charge

3. Reverse biased PNjunctions (Bulk andDrain/Source)

Most of These Caps arenonlinear and voltagedependent

DS

G

B

CGDCGS

CSB CDBCGB

Introduction

Dr. Eman Azab



14

MOS Structure Caps

tox

n+ n+

Cross section

L

Gate oxide

xd xd

Ld

Polysilicon gate

Top view

Gate-bulkoverlap

Source

n+

Drain

n+W

Introduction

Dr. Eman Azab



15

Channel Charge Caps

Introduction

Dr. Eman Azab



16

Reverse biased Junction Caps

Bottom

Side wall

Side wall

Channel

SourceND

Channel-stop implantN A1

Substrate NA

W

xj

LS

Introduction

Dr. Eman Azab



17

Ex.: Intrinsic Capacitances of CMOS Inverter

In addition to the intrinsic MOS caps, interconnect wires also

add to the parasitic caps “Cload”

Connecting more than one gate in cascade introduces more

parasitic caps “Cg”

Introduction

Dr. Eman Azab



18

Ex.: Intrinsic Capacitances of CMOS Inverter (Cont.)

Note that: CSB is neglected as VSB=0 for NMOS and PMOS

We can combine all caps connected at the output node to

CLoad to reduce the analysis complexity

Now we need to calculate how long it will take Cload to

charge or discharge to reach a desired voltage

Introduction: Delay Definitions

Dr. Eman Azab



19

How to calculate the signal

propagation delay in the

inverter?

Assume that the input signal

voltage is a step function

with zero rise and fall time

We will define propagation

delays as:

the time taken forthe output voltage to dropfrom VOH to the averagevoltage (V50%)

the time taken forthe output voltage to risefrom VOL to the averagevoltage (V50%)

Introduction: Delay Definitions

Dr. Eman Azab



20

How to calculate the signal

propagation delay in the

inverter? (Cont.)

The average propagation

delay is defined as:

The rise and fall time are

defined as the time

difference between V10% to

V90% or Vice versa

Respectively

Calculation of Propagation

delays

Dr. Eman Azab



21

Calculation of and

is calculated as the time Cload takes to discharge when the

output drops from high to low

The output falls when the input changes from low to high

NMOS driver mode changes from cutoff to linear

We can estimate this time by calculating the average current

that the capacitor discharge from VOH to V50%

Note that the same concept can be applied in case of the

output voltage changing from VOL to V50% (Calculating )


delays

Dr. Eman Azab



22

Calculation of and (Cont.)

Note that: this method ignores the variation of the transistor’s

mode between the beginning and end of the

charging/discharging process

It is not very accurate


delays

Dr. Eman Azab



23

Calculation of and using Differential equation

We can use the basic differential equation of the capacitor I-V

characteristic to calculate the propagation delays

Calculating for CMOS Inverter using differential

eqn.

Once VOH is applied to the CMOS inverter input, NMOS is on andPMOS is off

The output voltage starts to drop from VOH to VOL, thus the capacitorwill discharge in NMOS transistor


delays

Dr. Eman Azab



24


eqn.

Initially the NMOS will be in saturation (Vout=Vin=VOH)


delays

Dr. Eman Azab



25


eqn. (Cont.)

Once Vout becomes less that VOH-VT,n, NMOS will become linear


delays

Dr. Eman Azab



26


eqn. (Cont.)

Once Vout becomes less that VOH-VT,n, NMOS will become linear

For CMOS Inverter: VOH=VDD and VOL=0


delays

Dr. Eman Azab



27


eqn.

Similarly we can calculate

For CMOS Inverter: VOH=VDD and VOL=0

We can have a balanced structure (equal delays) by making

the NMOS and PMOS with the same threshold voltage and

transconductance parameters

Documents

Integrated Circuit Design ELCT 701 - eee.guc.edu.egeee.guc.edu.eg/Courses/Electronics/ELCT701 Integrated Circuits... · Inverter Study of the transient response ... Calculating for