Efficient On-line Interconnect BIST in FPGAs with Provable Detectability for Multiple Faults

Efficient On-line Interconnect BIST Efficient On-line Interconnect BIST in FPGAs with Provablein FPGAs with Provable

Detectability for Multiple FaultsDetectability for Multiple Faults

Vishal Suthar and Shantanu DuttVishal Suthar and Shantanu DuttDept. of ECEDept. of ECE

University of Illinois at ChicagoUniversity of Illinois at Chicago

Suthar & Dutt, University of Illinois at Chicago

OutlineOutline

On-Line BIST – ConceptsOn-Line BIST – ConceptsPrevious Work in Interconnect BISTPrevious Work in Interconnect BISTNew Interconnect BIST: I-BISTNew Interconnect BIST: I-BIST– MotivationMotivation– Types of faultsTypes of faults– On-line issuesOn-line issues– Global TestingGlobal Testing– Detailed TestingDetailed Testing– Simulation resultsSimulation resultsConclusionsConclusions


On-line Built-In Self-Testing in FPGAs

CIRCUIT

ROTE (ROving TEster)

• Two column left spare for ROTE; one for fault reconfiguration• ROTE roves across the FPGA

SPAR

E C

OLU

MN

CIRCUIT CIRCUITSPA

RE

CO

LUM

N

TPG - Test Pattern GeneratorORA - Output Response

Analyser CUT - Cells Under Test

BISTer:

WUT - Wires Under Test

WUT

WUT

T C

C O

C T

O C

• In each session diff. PLBs act as CUTs, TPG and ORA.

TPG CUT

CUT ORA

Pass / fail

WUT

WUT


Interconnect BIST-- MotivationInterconnect BIST-- Motivation

Interconnects occupy ~ 90% of FPGA areaInterconnects occupy ~ 90% of FPGA area

Multiple faults can easily occur for current and Multiple faults can easily occur for current and emerging nano-meter FPGAs; no current work emerging nano-meter FPGAs; no current work detects all multiple faultsdetects all multiple faults

Many PLB BIST work, but much fewer on Many PLB BIST work, but much fewer on interconnect BISTinterconnect BIST


Interconnect BIST– Past WorkInterconnect BIST– Past Work

• Only few on-line interconnect BIST methods

• # configurations high for previous on-line interconnect BIST: 10 for [Liu et al., CICC’01]

• # of test vectors high for all previoys interconnect BIST

• No prev. method has guarantd. 100% fault detectability for multiple faults

• Fault diagnosability (% of faults correctly located) low for past methods

• Our interconnect BIST method I-BIST will address and improve on all these issues

many


I-BIST – Objectives & Flow

Objectives: 1. To maximize diagnosability, even in presence of multiple faults, by avoiding fault masking scenarios.

2. To reduce test time. Dominant component of test time = configuration time

Hence minimize # configurations. Secondary objective: minimize # test vectors.

Approach:1. First isolate the possible fault locations to a small set of interconnects in very few configurations -> Suspect Set,

2. Then diagnose interconnects of suspect set for faults.

-- Global testing

-- Detailed testing


I-BIST – Interconnect Faults• Testing wire-segments and switches• Faults considered: wire-segment -> stuck-at, stuck-open and bridged fault

switches -> stuck-open and stuck-closed.Vcc

Wire stuck-at 1

Wirestuck-at 0

Wirestuck-open

Wirebridge

Expected value = 1

0 1

Expected value = 0

CB = 0 => switch is openCB = 1 => switch is closed

Switch stuck-open fault

Switch stuck-closed fault

Configurationbit (CB)


• Typical FPGA contains single-length, double-length and long wires. whereas, a ROTE can occupy only two to three columns.• Hence, two types of ROTE are required: V-ROTE and H-ROTE

V-ROT

EH-ROTE

Roving Tester Positions for I-BIST


I-BIST – Tested Interconnects

V-Set: Interconnects tested under V-ROTE

V Z Y X W

ROTE position 1 ROTE position 2

Channel of wire segmentsSwitch-box

N

E

S

WnsSewS

nwS

swS

neS

seS

• Uncovered switches are covered in the next ROTE position or in the H-ROTE


• Multiple nets are formed

• Multiple ORAs each comparing adj. nets

• ORAs configured for 2-input XOR function

• Pass complementary vectors on each adj. net => 2 test vectors {0101..} & {1010…}

TPG 10

01 ORA

1

ORA2

ORA3

Pass

Pass

Fail

00

1n2n3n4n

2w

1w

Switchesclosed

I-BIST – Global Testing: Idea

Test vector 1: 1 0 1 0 Test vector 2: 0 1 0 1


• Consider ORA(n2, n3)

•Under fault-free conditions ORA (2-ip XOR) output = 1 1

• Wire stuck-at fault @ n2 ORA output = 0 1 (n2 stuck-at-0)

= 1 0 (n2 stuck-at-1)

• Multiple stuck-at fault on n2 is going to result in one type dominating at the ORA input

• Wires bridge fault ORA output = 0 0

Switchesclosed

TPG 10

01 ORA

1

ORA2

ORA3

00

1n2n3n4n

2w

1w

Fail

X X

bridge




• Under fault-free conditions ORA (2-ip XOR) output = 1 1 • Exception: one of the adjacent wire is s-a-0 and other is s-a-1.

output = 1 1 = fault-free output

one more test vector required {0000…} or {111…}

• Unexpected-comparison based test vectorsUnexpected-comparison based test vectors

Switchesclosed

TPG 10

01 ORA

1

ORA2

ORA3

00

1n2n3n4n

2w

1w

Fail

1 0

s-a-1

s-a-0

• Fault-free output = 0 1 1

• Faulty output = 1 1 1


Test vector 0: 0 0 0 0I-BIST – Global Testing: Idea


Stuck-open fault:


Test vector 0: 0 0 0 0

Switchesclosed

TPG 10

01 ORA

1

ORA2

ORA3

00

1n2n3n4n

2w

1w

Stuck-openFailpass

•Assunption: Stuck-open fault essentiallyresults in a s-a-0 fault in the affected part

• Only detected if present between TPG and ORA

• A second stage of global testing reqd.

• Switch stuck-open faults that are part of the nets are similarly detected

• All switches are included in some net across 5 configurations of net patterns



Stuck-open fault (contd):

Switchesclosed

TPG 10

01 ORA

1

ORA2

ORA3

00

1n2n3n4n

2w

1w

Stuck-openFail

Switchesclosed

TPG

10

01 ORA

1

ORA2

ORA3

00

1n2n3n4n

2w

1w

Stuck-openFail

Two stages of global testing phase needed – can be done simultaneously

I-BIST – Global Testing: Idea (contd)


Switchesclosed

TPG 10

01 ORA

1

ORA2

ORA3

00

1n2n3n4n

2w

1wStuck-closed

• Unlike other faults, switch stuck-closed fault cannot be detected by including the switch on a net


Switch stuck-closed fault:


Switch stuck-closed fault (contd):

• Unlike other faults, switch stuck-closed fault cannot be detected by including the switch on a net

Spanning switches of

1n

1l

1n and 1l• Form nets in such a way that a switch stuck-closed fault bridges thetwo nets.

• We refer to such switches asSpanning switches



Theorem: Any number of faults in each net tested will be detected by the multiple ORA technique of global testing. Furthermore, a stuck-closed fault in any spanning switch between every pair of nets compared by an ORA will also be detected.

Corollary: Fault masking cannot occur in global testing, even in presence of faults of the same type.

I-BIST – Global Testing: Properties


1n2n3n 1l2l3l

),( 21 nnA

),( 32 nnA ),( 11 lnO

),( 22 lnOSpanning

SwitchStuck-closed

),( 21 llA

Test vector 2:Test vector 3:

0 1 00 1 01 0 11 0 1Test vector 1:

0 0 00 0 0Dual-type multiple ORA technique

• multiple nets formed• similarly configured nets – net-set e.g. net-sets n & l

Global Testing


1n2n3n 1l2l3l

),( 21 nnA

),( 32 nnA ),( 11 lnO

),( 22 lnOSpanning

SwitchStuck-closed

),( 21 llA

Test vector 2:Test vector 3:

0 1 00 1 01 0 11 0 1Test vector 1:

0 0 00 0 0Dual-type multiple ORA technique

Two types of ORA comparison:

1. Intra-net-set comparison

Adjacent nets of same net-set compared

E.g., target: all faults other than switch stuck-closed fault

2. Inter-net-set comparison

Nets i of the two net-sets compared E.g. target: switch stuck-closed faults in spanning switches

A n n( , )1 2

O n l( , )1 1

Global Testing


(a)

(d)(c)

(b)

(e)

2nwS

3nwS

3swS

2swS

2nsS

1nsS 3

nsS

1seS

2seS

2ewS

2neS

1neS

Theorem: Any # of fault(s) in the V-set (interconnects tested in V-ROTE) will be detected by the 5 configurations of the global testing phase.

Global Testing – Five Configurations


• Diagnose faults on faulty nets of global testing phase.

• Simple approach: Flat intersection Suspect set = interconnects of failed nets found in global testing phase

Each interconnect element of suspect set compared with fault-free components.

TPG

ORA

Suspect interconnect

Fault-free interconnect

Drawback: Suspect set may be too large, even in presence of few fault.

Detailed Testing


Better approach:Divide & Conquer ( D & C)

• Failed nets divided into 2 sub-nets

• Failed configurations re-applied independently on both sets of sub-nets.

• Only the comparisons that failed in global testing phase are reqd.

• Switches between the two sub-nets tested using same configurations minimized to two rows

1n2n 1l2lan2

bn2

al2

bl2

A

O O

O

Detailed testing – Divide & Conquer (D&C)


Detailed Testing – D&C (contd):

1n2n 1l2lan2

bn2

al2

bl2

Global testing Detailed testing

Switch stuck-closed

A

O O

O

O

O


Simulation SetupSimulation Setup• Simulated a 32 x 32 FPGA with single-length segments Simulated a 32 x 32 FPGA with single-length segments

in Cin C• Fault injector injects faults in wire segments and Fault injector injects faults in wire segments and

switches randomly at the specified fault probability switches randomly at the specified fault probability (density/100)(density/100)


Fault latency ( # configurations) vs. Fault density

1000

1500

2000

2500

3000

3500

4000

4500

1 2 3 4 5 6 7 8 9 10

Fault density (%)

Faul

t lat

ency

(%)

Divide and Conquer Flat intersection

Simulation Setup and Fault Latency Results• Simulated a 32 x 32 FPGA with single-length segments in CSimulated a 32 x 32 FPGA with single-length segments in C• Fault injector injects faults in wire segments and switches Fault injector injects faults in wire segments and switches randomly at the specified fault probability (density/100)randomly at the specified fault probability (density/100)


Overall Fault Diagnosability Results

Fault coverage (diagnosability) versus fault density

Analytical Results & Comparison to Prev Work

many


ConclusionsConclusions

Presented a new interconnect BIST technique I-BIST for Presented a new interconnect BIST technique I-BIST for FPGAs—uses a FPGAs—uses a hierarchical, adaptive approach, unexpected-hierarchical, adaptive approach, unexpected-comparison based test vectorscomparison based test vectorsApplicable to Applicable to both on-line and off-line BISTboth on-line and off-line BISTI-BIST has I-BIST has 100% guaranteed fault detectability100% guaranteed fault detectability in the in the presence of multiple faults – presence of multiple faults – a firsta firstI-BIST has I-BIST has ~ 100% fault diagnosability~ 100% fault diagnosability (empirically) (empirically)I-BIST has the I-BIST has the fewest configurations—5—per WUT-setfewest configurations—5—per WUT-set in in global testingglobal testingI-BIST has the I-BIST has the fewest # of test vectors—3—per WUT-setfewest # of test vectors—3—per WUT-set testing phasetesting phaseI-BIST uses an I-BIST uses an adaptive D&C phase in detailed testingadaptive D&C phase in detailed testing to to home in to the offending faults quicklyhome in to the offending faults quicklyNew work: New work: Combined PLB and interconnect BIST w/o fault-Combined PLB and interconnect BIST w/o fault-free assumptionsfree assumptions about any components—to appear at about any components—to appear at VTS’06VTS’06

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Efficient On-line Interconnect BIST in FPGAs with Provable Detectability for Multiple Faults