Microelectronic Engineering 67–68 (2003) 629–634www.elsevier.com/ locate/mee

E ffects of annealing conditions on charge storage of Sinanocrystal memory devices obtained by low-energy ion beam

synthesisa , a a a a*P. Normand , E. Kapetanakis , P. Dimitrakis , D. Skarlatos , D. Tsoukalas ,

b c c c cK. Beltsios , A. Claverie , G. Benassayag , C. Bonafos , M. Carrada ,c d e e eN. Cherkashin , V. Soncini , A. Agarwal , Ch. Sohl , M. Ameen

aInstitute of Microelectronics, NCSR Demokritos, 15310Aghia Paraskevi, GreecebDepartment of Materials Science and Technology, University of Ioannina, Ioannina, Greece

cCEMES /CNRS, 29 rue Jeanne Marvig, BP 4347, 31055Toulouse Cedex 4, FrancedST Central R& D Agrate, Via Olivetti 2, 20041,Agrate, Brianza, Italy

eAxcelis Technologies, Inc., 55 Cherry Hill Drive, Beverly, MA 01915,USA

Abstract

The structural and electrical characteristics of thin silicon dioxide layers with embedded Si nanocrystals arereported fabricated by low-energy silicon implantation and with subsequent annealing in inert and dilutedoxygen. Thermal treatment in diluted oxygen increases the thickness of the control oxide, does not affectsignificantly the size of the nanocrystals, and improves the integrity of the oxide. As a result, strong chargestorage effects at low gate voltages and enhanced charge retention times are observed through electricalmeasurements of MOS capacitors. These results indicate that a combination of low-energy silicon implants andannealing in diluted oxygen permits the fabrication of low-voltage nonvolatile memory devices. 2003 Elsevier Science B.V. All rights reserved.

Keywords: Nanocrystals; Nanocrystal memory; Nonvolatile memory; Ion beam synthesis; Ion implantation

1 . Introduction

Nanocrystal-based memory devices have recently attracted much attention for high-density low-power memory applications [1,2]. Among the different techniques used in the course of fabricatingsilicon dioxide films with embedded nanocrystals, the low-energy ion beam synthesis approach offersa promising field of investigation. Previous studies demonstrated that this technique permits making

*Corresponding author. Tel.:1 30-1-650-3115; fax:1 30-1-651-1723.E-mail address: p.normand@imel.demokritos.gr(P. Normand).

0167-9317/03/$ – see front matter 2003 Elsevier Science B.V. All rights reserved.doi:10.1016/S0167-9317(03)00124-2

630 P. Normand et al. / Microelectronic Engineering 67–68 (2003) 629–634

ultra-thin layers of Si nanocrystals in thin SiO layers at relatively low doses and at a location2

smoothly controlled by the implantation energy [3–5]. Nanocrystal memories obtained using thistechnique have recently been reported [6,7]. This work gave attractive results but also revealed theneed for further experimental studies that will lead to a full exploration of the potential of thelow-energy ion beam synthesis technique for mainstream microelectronic technology. In particular, animportant issue to be resolved before the practical application of this technique is related to thedamage induced by implantation; such damage strongly affects the integrity of the oxide, and thus, thememory characteristics of the devices.

In this study, we report the effect of the annealing ambient on the structural characteristics andmemory properties of low-energy Si-implanted SiO films. The influence of the annealing ambient on2

charge injection and storage is examined through capacitance and current–voltage measurements ofMOS capacitors.

2 . Experimental

Silicon dioxide layers of thickness 7, 9 and 10 nm were thermally grown on 8-inch p-type28(100)-oriented Si wafers. These oxides were subsequently Si-implanted with an energy of 1 keV to a

16 1 2dose of 2310 Si /cm . Following the implantation step, all samples were furnace annealed underthe following conditions: (a) 9508C/30 min in inert ambient (N )—hereafter referred as A12

treatment; or (b) 9508C/15 min in N ambient followed by 9508C/15 min in diluted oxygen (mixture2

of N and O )—hereafter referred as A2 treatment. Fabrication of Al electrodes on both sides of the2 2

samples was followed and electrical characterization was carried out through capacitance andcurrent–voltage measurements.

3 . Results and discussion

Transmission electron microscopy (TEM) carried out on non-implanted and Si-implanted samples,both subsequently annealed following the A1 and A2 treatments, reveals the presence of a single layerof silicon nanocrystals in the Si-implanted SiO films. These nanocrystals are spherical in shape with2

a diameter of about 2 nm. No significant dependence of the nanocrystal size on the annealingtreatment was detected. A swelling of the oxide layer (ca. 3.5 nm, not including the nanocrystal bandwidth) was observed for the implanted and A1 annealed samples. Such an extent of oxide swellingcannot be attributed to oxidation of the substrate due to residual oxidizing species in the furnace as noswelling was detected for the non-implanted/annealed samples. Effects of oxide swelling forlow-energy Si-implanted oxides have been previously reported [3–5] and are discussed in detail inRef. [5]. In addition, TEM examination reveals that the thickness of the oxide increases by about 1 nmafter the A2 treatment compared to the A1 treatment for both implanted and non-implanted oxides.For Si-implanted oxides, it should be emphasized that A2 treatment does not increase the thickness ofthe injection oxide (distance between the Si /SiO interface and the nanocrystal layer) but causes an2

increase in the control oxide thickness (distance between the top of the nanocrystals and the gateelectrode). The effects of implantation and annealing treatment on the thickness of the oxide have also

P. Normand et al. / Microelectronic Engineering 67–68 (2003) 629–634 631

16 2Fig. 1. High-frequency (1 MHz)C–V measurements of non-implanted and 2310 Si /cm -implanted 10-nm-thick oxidelayers annealed following the A1 and A2 treatments. The indicated oxide thickness was deduced from the capacitancemeasurement in accumulation.

been deduced from capacitance–voltage (C–V ) measurements by assuming a gate insulator dielectricconstant of 3.9, and the extracted values are close to those measured by TEM.

Fig. 1 showsC–V curves for Si-implanted and non-implanted 10-nm-thick oxides after the A1 andA2 thermal treatments. After the A1 treatment, an oxide swelling of 44% (ca. 4 nm) was measured forthe Si-implanted sample while the oxide thickness appears close to the expected value (10 nm) for thenon Si-implanted sample. A2 treatment causes an increase in swelling of about 1 nm for thenon-implanted and Si-implanted oxides. Compared to the initial oxide thickness (10 nm), the

16 2introduction of Si atoms at a dose of 2310 Si /cm and a subsequent annealing in diluted oxygenconditions leads to an oxide swelling of around 5.5 nm. A similar extent of oxide swelling was alsomeasured for the non-implanted and Si-implanted 7- and 9-nm-thick oxides and subsequentlyannealed following the A1 and A2 thermal treatments.

The effect of annealing ambient on the electrical properties of Si-implanted oxides has beenexamined through high-frequency (1 MHz)C–V measurements under white light illuminationconditions. The gate voltage was swept from inversion to accumulation and back to inversion with a

2step of 0.5 V/s. The capacitor area was 1003 100mm . Although white light illumination was used toavoid deep depletion conditions that can occur at large positive gate voltages (for a p-type substrate),for many devices the supply of minority carriers (electrons here) was not large enough to ensure rapidformation of the inversion layer. Due to this limitation in electron injection efficiency from theSi /SiO interface into the oxide, the effect of large positive gate voltages on the flat band voltage shift2

reported here is somewhat reduced by comparison with what would be observed in the case oftransistors or capacitors with surrounding n-doped regions.

Fig. 2a shows high-frequencyC–V curves for a 9-nm-thick oxide layer annealed in inert ambient(A1). While no significant flat-band voltage shift (DV ) is detected when the gate voltage is sweptFB

from 12 V to 22 V and back to12 V, higher negative gate voltages lead to a positive voltage shift.This positive voltage shift is due to negative charge trapped in the oxide. Such a negative chargetrapping is due to electron injection from the gate into the oxide. If the annealing sequence uses a

632 P. Normand et al. / Microelectronic Engineering 67–68 (2003) 629–634

16 2Fig. 2. High-frequencyC–V curves for a 9-nm-thick oxide layer implanted with 23 10 Si /cm at 1 keV and subsequentlyannealed following (a) the A1 treatment and (b) the A2 treatment. (a) Negative gate voltage causes electron injection into theoxide from the gate (or hole extraction from the oxide) and a sweep of Vg from accumulation (2Vg) to inversion (1Vg)traces the curve indicated by the arrow pointing to the right. (b) High positive and negative gate voltages cause, respectively,electron and hole injection into the oxide from the substrate. A sweep of Vg from inversion to accumulation and fromaccumulation to inversion is shown by the arrow to the left and to the right, respectively.

thermal treatment in diluted oxygen (treatment A2), theC–V curves are shifted to higher positive1voltages (positive shift,V ) for a gate voltage sweep from inversion to accumulation, while theFB

2opposite effect (negative shiftV ) takes place when the gate voltage is swept from accumulation toFB1 2inversion (Fig. 2b). Charge trapping occurs through electron (V ) and hole (V ) injection from theFB FB

substrate into the oxide. We assume that as a result of implantation damage recovery and control oxideswelling during the A2 treatment, the integrity of the control oxide is significantly restored, chargingfrom the gate does not appear and effective charge injection from the substrate occurs. It should beremembered thatDV depends linearly on the thickness of the control oxide,d , according to:FB C

DV 5 d 3Q /´ where Q is the amount of charge stored in the floating gate made ofFB C FG C FG

nanocrystals and́ the dielectric constant of the control oxide.C

The effect of the A1 and A2 post-implantation thermal treatments on the memory window of7-nm-thick oxide layers is shown in Fig. 3. In comparison with the A1 treatment, the magnitude of theflat-band voltage shift as a function of the gate voltage sweep strongly increases after A2 thermaltreatment. It is believed that such an increase is mainly due to the improved quality and enhancedthickness of the control oxide after the A2 treatment. This assumption is further supported by theobserved gate current versus gate voltage characteristics under accumulation conditions of non-implanted and Si-implanted oxides subsequently annealed following the A1 and A2 treatments (Fig.4). For both thermal treatments, the gate current of the implanted samples is higher than thenon-implanted ones. The enhanced conduction at low gate bias in accumulation is mainly determinedby electron injection into the control oxide from the gate and/or hole injection into the injection oxidefrom the substrate. Both of these leakage current components are strongly dependent on the qualityand the thickness of the control and injection oxides. The improved quality and enhanced thickness ofthe control oxide caused by the A2 treatment, eliminate the relative leakage current component. As aresult, the total leakage current for the A2 case is expected to be lower than the A1 case in agreementwith our experimental results. Moreover, a higher concentration of trapped holes is achieved resultingin an effective screening of the applied electric field and thus to an increase in the breakdown voltage.

P. Normand et al. / Microelectronic Engineering 67–68 (2003) 629–634 633

Fig. 3. Flat band voltage shift as a function of the gate Fig. 4. Magnitude of the dark gate current density undervoltage round sweep for 7-nm-thick oxide layers implanted accumulation conditions as a function of negative ramped

16 2with 23 10 Si /cm at 1 keV and subsequently annealed gate voltage (1 V/s) on 7-nm-thick Si-implanted oxidesfollowing the A1 or A2 treatment. annealed following the A1 or the A2 treatment. The

leakage current for a 7-nm-thick non-implanted A2-an-nealed oxide is shown for comparison purposes.

Furthermore, it appears that the integrity of the injection oxide remains strongly affected by theimplantation process even after the A2 thermal treatment. It is believed that the presence of a largeexcess of silicon atoms in the injection oxide contribute substantially to the significant chargingobserved at small gate voltages despite the large injection oxide thickness as measured by TEM (ca. 6and 9 nm for 7- and 10-nm-thick implanted oxides, respectively). In the case of the Si-implanted

16 2Fig. 5. Data retention characteristics of 7-nm-thick oxide layers implanted with 23 10 Si /cm at 1 keV and subsequentlyA2 annealed.

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oxides reported herein, the excess of silicon atoms enhances the conductivity of the injection oxideand leads to a decrease in the barrier height for charging in the nanocrystals.

First investigations of the charge retention time at room temperature have been carried out for7-nm-thick A2-annealed oxide layers. The flat-band voltage after electron (write) or hole (erase)injection as a function of waiting time is shown in Fig. 5. The flat-band voltage window significantlynarrows within the first 10 min and subsequently decreases from 0.85 to 0.6 V through a waiting timeof about 3 h with a trend for stabilization.

4 . Conclusions

The effect of post-oxidation annealing on the structural characteristics and electrical properties ofthin SiO layers with embedded Si-nanocrystals obtained by low-energy ion beam synthesis have been2

examined. TEM investigations show a significant swelling of the oxide after implantation andsubsequent annealing. A thermal treatment in diluted oxygen causes an increase in the control oxideand improves the integrity of the oxide. As a result, large flat-band voltage shifts at low gate voltagesand increased breakdown voltages are observed inC–V and I–V characteristics of MOS capacitors.The magnitude of the programming windows and the window decay rates observed throughout themeasurements carried out so far suggest that these devices could be attractive candidates for thefurther development of low-voltage nonvolatile memory cells.

A cknowledgements

This work was partially supported by the European Union through the Growth project G5RD/2000/00320—NEON.

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