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EE544/AEEE561 – Advanced Digital Systems Design
Dr. Konstantinos Tatas
http://staff.fit.ac.cy/com.tk
Outcomes• Understand all steps in the digital system design and
implementation process.• design digital systems using Hardware Description
Languages• Identify the available design, synthesis and
implementation options and trade-offs between performance, area and power consumption
• develop testbenches to verify their designs• Identify and resolve possible metastability and
synchronization issues in digital design • Incorporate design reuse practices into their designs• Use EDA tools to implement digital systems in FPGA
technology• Keep up with current developments in digital design
methodologies and tools
Course Outline• Combinational and sequential design practices – State
machines, Synchronous and asynchronous design. • Synchronous Design Methodology – Clock skew –
Asynchronous inputs – Clock Gating - Metastability – Reliable Synchronization of high-speed data transfers
• Design for performance, design for area, design for low power consumption
• RTL design using Hardware Description Languages – Verilog
• Digital system verification – Simulation (event-based/cycle-based/transaction-based/emulation/AMS simulation) – Equivalence checking – Static timing verification – Rapid prototyping
• RTL Synthesis for ASIC and FPGAs - RTL coding practices for synthesis
• Hardware accelerators – IP block design for reuse• Testing and Design for Testability (DFT) fundamentals –
Built-In Self-Test (BIST)
Textbooks and References
• J. F. Wakerly, Digital Design: Principles and Practices, Prentice Hall, 2003.
• Michael D. Ciletti, “Advanced Digital Design with the Verilog HDL”, Prentice Hall, 2004
• Michael Keating, Russell John Rickford, Pierre Bricaud, “Reuse Methodology Manual for System-On-A-Chip Designs”, Springer, 2006
Assessment
• Exam: 40%
• Assignment 1: Paper writing/review (25%)
• Assignment 2: Group project (25%)
• Test: 10%
Weekly Breakdown• Week 1: Digital Revision• Week 2: Synchronous Design• Week 3: Design flow – Paper review assignment• Week 4: Verilog• Week 5: Verilog• Week 6: Verilog /paper review presentation• Week 7: Verification• Week 8: Test• Week 9: Logic Synthesis/Design for reuse• Week 10: Assignment/Group project specifications• Week 11: Assignment/Group project review – Case study
part 1• Week 12: Assignment/Group project review – Case study
part 2• Week 13: Assignment/Group project assessment - Revision
The Binary Numbering System
• Digital systems and computers use the Binary system because it has only two states (0 and 1)
• A number in the Binary system is expressed by the following expression:
Examples:• (1011)2 = (1X23 )+(0X22)+(1X21) +(1X20) = 8+0+2+1= (11)10
• (10110)2 = (1X24 )+(0X23)+(1X22) +(1X21) +(0X20) = 16+0+4+2+0= (22)10
• (101100)2=(1X25)+(0X24)+(1X23)+(1X22)+(0X21)+(0X20)=32+0+8+4+0+0=(44)10
(dndn-1…d1d0)2 = (dnX2n )+ (dn-1X2n-1) + …+ (d1X21) +( d0X20)
Where d = {0,1}
The Binary Numbering System (Cont.)
• A binary digit is called the BIT (BInary digiT).
• A group of eight bits is called the BYTE.
• The leftmost bit of a number is called the Most Significant Bit (MSB).
• The rightmost bit of a number is called the Least Significant Bit (LSB).
• A binary system with N bits can represent the numbers from 0 to 2N-1.
• In a binary system with N digits there are 2N different combinations.
• A binary number is multiplied by two, if we append a zero at the LSB.
• Prefixes in the binary system:
210
= 1,024 = 1K (Kilo)
220
= 1,024 X 1,024 = 1,048,576 = 1M (Mega)
230
= 1G (Giga)
240
= 1T (Tera)
Powers of 2:
20 = 1
21 = 2
22 = 4
23 = 8
24 = 16
25 = 32
26 = 64
27 = 128
28 = 256
29 = 512
210
=1024=1K
216
= 65536
Negative Number Representation: Two’s Complement
• If the number is positive then the two’s complement is the same as the SM. If the number is negative then the two’s complement is obtained by adding 1to the magnitude bits of the one’s complement. The sign bit is unchanged.
• The two’s complement is widely used in computers to represent signed integers. In most languages such as Pascal and C an integer variable is represented in a 16-bit two’s complement representation.
(+38) 10 = (00100110) SM:8 = (00100110) 2's C:8
Sign bit
Magnitude
(-38) 10 = (11011001) 1's C:8 = (11011010) 2's C:8
Sign bit
Magnitude +1
(00101011) 2's C:8 = (00101011) SM:8 = (+43) 10
Sign bit
Magnitude
(11010101) 2's C:8 = (10101011) SM:8 = (-43) 10
Sign bit
Magnitude +1
Basic Logic Gates
Buffer AND OR EX-OR
A X X X XA A A
BBB
X = A X = A B X = A + B X = A + B
A X0 0
11
A X0
0
1
10
001
1 1
0
0
B A X0
1
1
10
001
1 1
0
1
B A X0
1
0
10
001
1 1
0
1
B
Truth Table
Logic Expression
Gate Symbol
Logic Function
Basic Logic Gates with Inverted Outputs
NOT NAND NOR EX-NOR
A X X X XA A A
BBB
X = A X = A B X = A + B X = A + B
A X0
01
1
A X0
01
10
001
1 1 00
B A X0 1
1 10
001
1 1
01
B A X0 1
010
001
1 1
0
1
B
Circuit Implementation of a Logic Expression with Gates
X = A + BC
Logic Function A
B
C BC
BX
Logic Diagram with Gates
X = (A + B)C
Logic Function A
B
C
A+BB
X
Logic Diagram with Gates
Truth Tables
Truth table of a logic circuit is a table showing all the possible input combinations with
the corresponding value of the output. Examples:
A B C
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
X
0
0
0
1
1
1
1
0
(a) Show the truth table of a 3-input circuitthat gives at its output a logic 1 if the inputforms a number between 3 and 6.
Inputs Output
0
1
2
3
4
5
6
7
(b) Show the truth table of the logic expression:
A B C
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
AB C AB + C
0
0
0
0
1 1
0
1
1
0
1
1
0
1
0 0
0
00
1 1
1 0 1
X = (AB+C)(A+C)
1
1
1
1
0
0
0
1
1
1
1
1
0
0
1
1
A + C
X = (AB + C)(A + C)
Logic expression and truth table of a logic circuit
AB
CX
T1 =
T2 =
T3 =
T4 =
A B C
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
1
2
3
4
5
6
7
T1 T2 T3 T4 X
Logic Expression: X =
SoP Form: X =
PoS Form: X =
Analyzing a logic circuit using timing diagrams
A
B
CX
T1 =T2 =
T3 =
T4 =
A B C
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
1
2
3
4
5
6
7
T1 T2 T3 T4 X
A
B
C
X
Logic 0
Logic 1
Decoders• A decoder is a combinational digital circuit with a number of inputs ‘n’ and a number of outputs
‘m’, where m= 2n
• Only one of the outputs is enabled at a time. The output enabled is the one specified by the binary number formed at the inputs of the decoder.
• On the circuit below, the inputs of the decoder are connected on three switches, forming the number 5 [(101)2], thus only LED #5 will be ON
0
1
0
1
0
1 0 1 2 3 4 5 6 7
0 1 0 10 1
A2
Y2A0
Y0
Y1
Y3
3/8 DEC.
Y6
Y4
Y5
Y7
A1
2 to 4 Line Decoder:
A1
A0
Y0
Y1
Y2
Y3
Y = E A A0 1 0
Y = E A A1 1 0
Y = E A A2 1 0
Y = E A A3 1 0
2-to-4 Line Decoder with Enable Input
Logic Symbol Truth Table
LogicExpressions Logic Circuit
A1
Y2
A0
Y0
Y1
Y3
2/4 DEC
E
A1 Y0 Y1 Y2 Y3
0
0
0
0 0 0
0
000
0 0 0
001
1
1 1 1
1
1
1
A0E
0
1
1
1
1 0
X X 0 0 0 0
E
A1
Y2A0
Y0
Y1
Y3
2/4 DEC A1 Y0 Y1 Y2 Y3
0 0
0
0
0 0 0
0
000
0 0 0
001
1
1 1 1
1
1
1
A0
A1
A0
Y0
Y1
Y2
Y3
Y = A A0 1 0
Y = A A1 1 0
Y = A A2 1 0
Y = A A3 1 0
2-to-4 Line Decoder
Logic Symbol Truth Table
LogicExpressions
Logic Circuit
Internal structure of a 2-to-1 multiplexer.
• The design of a 2-to-1 multiplexer is shown below.• If S=0 then the output “Y” has the same value as the input “I0” • If S=1 then the output “Y” has the same value as the input “I1”
I1
I0Y
2/1 MUX
Y = S I + S I0 1
Logic Symbol
Truth TableLogic Expression
I1 Y
0
0
0 0
1
11
1
1 1
0
I0
0
0
0
0 1
1
01
1
1 1
00
S
0
0
0
0
1
1
1
1
I1I000
0
01
1
11 10S0 1 1 0
0 0 1 1S
I1
Y
I0
S
1
0
Logic Function
S
I1
I0
Y
Logic Circuit
1/2 Dec.
2-to-1 Multiplexer
4-to-1 Multiplexer (MUX)
4-to-1 MUX
O
I0
I1
I2
I3
S1 S0
S1 S0 O
0 0 I0
0 1 I1
1 0 I2
1 1 I3
2-to-1 MUX
O
I0
I1
I2
I3
S1
S0
2-to-1 MUX
2-to-1 MUX
1-bit Full AdderA B Cin Cout Sum
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
Y0A
B
C
3/8 Dec.
En
Y1
Y2
Y3
Y4
Y5
Y6
Y7
I08/1 Mux
Y
I1
I2
I3
S2 S1 S0
I4
I5
I6
I7
I0
8/1 Mux
Y
I1
I2
I3
S2 S1 S0
I4
I5
I6
I7
1-Bit F.A.
Cout Sum
A B Cin
Logic Symbol
Truth Table
1-Bit Full Adder using gates
1-Bit Full Adder using a decoder 1-Bit Full Adder using 8/1 multiplexers
I04/1 Mux
Y
S0S1
I1
I2
I3
Cout Sum
Cin
A
B
A
B
Cin
Sum
Cout
A
B
Cin
0
0
0
1
0
1
1
1
0
1
1
0
0
0
1
1
Sum
Cout
I0
4/1 Mux
Y
S0S1
I1
I2
I3
A
B
Cin
0
1
A
A
A'
A
A'Sum
Cout
1-Bit Full Adder using 4/1 multiplexers
4-bit Full Adder (Ripple-Carry Adder)
• To obtain a 4-bit full adder we cascade four 1-bit full adders, by connecting the Carry Out bit of bit column M to the Carry In of the bit column M+1, as shown below. The Carry In of the Least Significant column is set to zero.
1-Bit F.A.
Cout Sum
A B C in
1-Bit F.A.
Cout Sum
A B C in
1-Bit F.A.
Cout Sum
A B C in
1-Bit F.A.
Cout Sum
A B C in
A3 B3 A0 B0A2 B2 A1 B1
0
S3 S2 S1 S0
Cout
• Example: Find the bit values of the outputs {Cout,S3..S0} of the full adder shown below, if {A3..A0 = 1011} and {B3..B0 = 0111}.
Review questions• How many input/output signals are present in a
– 5-to-32 decoder?
– 32-to-1 MUX?
– 32-bit Ripple-Carry Adder (RCA)?
• How many 2-to-1 MUXs are required to build a 32-to-1 MUX?
• Design a logic unit with 2 data inputs (A, B), three select inputs (S2, S1, S0) and the following specifications:
S2 S1 S0 O
0 0 0 A AND B
0 0 1 A OR B
0 1 0 A XOR B
0 1 1 A NAND B
1 0 0 A NOR B
1 0 1 A XNOR B
1 1 0 A΄
1 1 1 B΄
The Toggle (T) Edge Triggered Flip Flop
The T edge triggered flip flop can be obtained by connecting the J with the K inputs of a JK flip directly. When T is zero then both J and K are zero and the Q output does not change. When T is one then both J and K are one and the Q output will change to the opposite state, or toggle.
Logic Symbol
Positive Edge T Flip Flop
T Q
Q
CLK
CLK
T Q
Q
J Q
QK
Logic Symbol
Negative Edge T Flip Flop
T Q
Q
CLK
CLK
T Q
Q
J Q
QK
CLK QN+1 FunctionT
X
0
1
CLK QN+1 FunctionT
X
0
1
Q Q
Q
Q΄
Q
Q΄
D and T Edge Triggered Flip Flops :- Example
Complete the timing diagrams for :(a) Positive Edge Triggered D Flip Flop(b) Positive Edge Triggered T Flip Flop(c) Negative Edge Triggered T Flip Flop(d) Negative Edge Triggered D Flip Flop
(b)(a)
D
Q
CLK
D
Q
CLK
(d)(c)
T
Q
CLK
T
Q
CLK
Finite state machine block diagram
• State memory: Set of n flip-flops that hold the state of the machine (up to 2^n distinct states)
• Next state logic: Combinational circuit that determines the next state as a function of the current state and the input
• Output logic: Combinational circuit that determines the output as a function of the current state and the input
NEXT STATELOGIC
Q
QSET
CLR
D
Q
QSET
CLR
D
...
STATE MEMORY
OUTPUT LOGIC
CLK
INPUTS
PREVIOUS STATE
NEXT STATE
OUTPUTS
Finite State Machine types
• Mealy machine: The output depends on the current state and input
• Moore machine: The output depends only on the current state– State = output state
machine: A Moore type FSM where the current state is the output
COMBINATIONAL LOGIC
Q
QSET
CLR
D
Q
QSET
CLR
D
...
STATE MEMORY
OUTPUT LOGIC
CLK
INPUTS
PREVIOUS STATE
NEXT STATE
OUTPUTS
COMBINATIONAL LOGIC
Q
QSET
CLR
D
Q
QSET
CLR
D
...
STATE MEMORY
OUTPUT LOGIC
CLK
INPUTS
PREVIOUS STATE
NEXT STATE
OUTPUTS
COMBINATIONAL LOGIC
Q
QSET
CLR
D
Q
QSET
CLR
D
...
STATE MEMORY
CLK
INPUTS
PREVIOUS STATE
NEXT STATE
OUTPUTS
State diagram
1000
01 11
0/1
0/10/1
1/0
1/0
1/0
1/0
0/0
A state diagram represents the states as circles and the transitions between them as arrows annotated with inputs and outputs
Analysis of FSMs with D flip-flops
• Determine the next state and output functions
• Use the functions to create a state/output table that specifies every possible next state and output for any combination of current state and input
EXAMPLE
Q
QSET
CLR
D
Q
QSET
CLR
D
X
A
A’
B
B’CP
Y
Next state equations and state table for example
• A+=Ax+Bx• B+=A΄x• Y=(A+B)x΄
A B x A+ B+ y
0 0 0 0 0 0
0 0 1 0 1 0
0 1 0 0 0 1
0 1 1 1 1 0
1 0 0 0 0 1
1 0 1 1 0 0
1 1 0 0 0 1
1 1 1 1 0 0
Q
QSET
CLR
D
Q
QSET
CLR
D
X
A
A’
B
B’CP
Y
• A+=Ax+Bx
• B+=A΄x
• Y=(A+B)x΄
A B x A+ B+ y
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Sequential circuit design methodology• From the description of the functionality or the
state/timing diagram find the state table• Encode the states if the state table contains letters• Find the necessary number of flip-flops• Select flip/flop type• From the state table, find the excitation tables and
output tables• Using Karnaugh maps find the flip-flop input logic
expressions• Draw the circuit logic diagram
• Often we have to implement an algorithm in hardware instead of software
• Algorithm is a well defined procedure consisting of a finite number of steps to the solution of a problem.
• It is often hard to translate the algorithm into an FSM.
• ASMs can serve as stand-alone sequential network model.
Algorithm Implementation
Algorithmic State Machine•Used to graphically describe the operations of an FSM more concisely
•Resembles conventional flowcharts – differs in
interpretation.
•Conventional flowchart – sequential way of
representing procedural steps and decision paths
for algorithm
-No time relations incorporated
•ASM chart – representation of sequence of
events together with timing relations between
states of sequential controller and events
occurring while moving between steps
ASM Chart•Three basic elements: state box, decision
box and conditional box
-State and decision boxes used in conventional
flowcharts
-Conditional box characteristic to ASM
•State box
-Used to indicate states in control sequence
•Register operations and output signals used to
control generation of next state written
State box
•Represents one state in the ASM.
•May have an optional state output list.
•Single entry.
•Single exit to state or decision boxes.
State Box
State name T3
•Binary code of T3 – 011
•Register operation R <- 0
•START – name of
outputs signal generated
in this stage
Decision box
• Provides for next alternatives and conditional outputs.
• Conditional output based on logic value of Boolean expression involving external input variables and status information.
• Single entry.• Dual exit, denoting if Boolean
expression is true or false.• Exits to decision, state or conditional
boxes.
Decision Box
•Input condition subject to
test inside diamond shape
box
•Two or more outputs
represent exit paths
dependant on value of
condition in decision box
•Two paths for binary based conditions
Conditional output box
• Provides a listing of output variables that are to have a value logic-1, i.e., those output variables being asserted.
• Single entry from decision box.• Single exit to decision or state box.
•In state T1
Output signal START
generated
Status of input E
checked
•If E = 1, R <- 0,
otherwise remains
unchanged
•Conditional
operation executed
depending on result
of coming from
decision box
Conditional Box
ASM Block
• Consists of the interconnection of a single state box along with one or more decision and/or conditional boxes.
• It has one entry path which leads directly to its state box, and one or more exit paths.
• Each exit path must lead directly to a state, including the state box in itself.
• A path through an ASM block from its state box to an exit path is called a link path.
Timing Considerations All sequential elements in datapath and control
path controlled by master-clock generator.
Does not necessarily imply single clock in design.
•Multiple clocks can be obtained through division of clock
signals from master-clock generator.
•Not only internal signals, but also inputs
synchronized with clock.
•Normally, inputs supplied by other devices working
with the same master clock.
•Some inputs can arrive asynchronously
Difficult to handle by synchronous designs, require
asynchronous glue-logic.
•In conventional flowchart, evaluation of each chart element takes one clock cycle
Step 1: Reg A incremented
Step 2: Condition E evaluated
Step 3: Based on evaluation results, state
T2, T3 or T4 entered
•In ASM the entire block considered
as one unit
•All operations within block occurring
during single edge transition
The next state evaluated during the same clock
System enters next state T2, T3 or T4 during transition of next clock
ASM Block
ASM Block
• An ASM block describes the operation of the system during the state time in which it is in the state associated with the block.
• The outputs listed in the state box are asserted.
• The conditions indicated in the decision boxes are evaluated simultaneously to determine which link path is to be followed.
• If a conditional box is found in the selected path then the outputs found in its output list are asserted.
• Boolean expression may be written for each link path. The selected link paths are those that evaluate to logic-1.
Example 2
• Extract the FSM diagram from the ASM diagram
T0
x
F
T1
T2
x
E
T4
T6
T3
T7
0
0
0
T5
1
0
1
1
