EE260: Digital Design, Spring 2018 6-Feb-18€¦ · EE260: Digital Design, Spring 2018 6-Feb-18 Verilog HDL 1: Introduction of FPGA and Verilog 1 Verilog –Module 1 Introduction

EE260: Digital Design, Spring 2018 6-Feb-18

Verilog HDL 1: Introduction of FPGA and Verilog 1

Verilog – Module 1 Introduction

Yao Zheng(Based on the slides of Prof. Jim Duckworth)

Topics

• Background to Verilog• Introduction to language• Programmable Logic Devices

– CPLDs and FPGAs– FPGA architecture– Nexys 3 Board (with Spartan 6 FPGA) [discontinued]– Basys 3 Board (with Artix-7 FPGA)– Nexys4DDR Board (with Artix-7 FPGA)

• Using Verilog to synthesize and implement a design• Verilog overview

Hardware Description Languages

• Example HDL's : ABEL, VERILOG, VHDL• Advantages:

– Documentation– Flexibility (easier to make design changes or mods)– Portability (if HDL is standard)– One language for modeling, simulation (test benches), and

synthesis– Let synthesis worry about gate generation

• Engineer productivity

• However: A different way of approaching design– engineers are used to thinking and designing using graphics

(schematics) instead of text.

Verilog background

• 1983: Gateway Design Automation released Verilog HDL “Verilog” and simulator

• 1985: Verilog enhanced version – “Verilog-XL”• 1987: Verilog-XL becoming more popular (same year

VHDL released as IEEE standard)• 1989: Cadence bought Gateway• 1995: Verilog adopted by IEEE as standard 1364

– Verilog HDL, Verilog 1995

• 2001: First major revision (cleanup and enhancements)– Standard 1364-2001 (or Verilog 2001)

• System Verilog under development– Better system simulation and verification support

Books

• “FPGA Prototyping by Verilog Examples”, 2008, Pong P. Chu, Wiley 978-0-470-18532-2

• “Starters Guide to Verilog 2001” by Ciletti, 2004, Prentice Hall 0-13-141556-5

• “Fundamentals of Digital Logic with Verilog Design” by Brown and Vranesic, 2003, McGraw-Hill, 0-07-282878-7

• “Advanced Digital Design with the Verilog HDL”, by Ciletti, 2003, Prentice-Hall, 0-13-089161-4

• “HDL Chip Design” by Smith, 1996, Doone Publications, 0-9651934-8

• “Verilog Styles for Synthesis of Digital Systems” by Smith and Franzon, 2000, Prentice Hall, 0-201-61860-5

• “Verilog HDL” by Palnitkar”, 2003, Prentice Hall, 0-13-044911-3• “Verilog for Digital Design” by Vhadi and Lysecky, 2007, Wiley, 978-

0-470-05262-4

Create Verilog Module



Module Created

• No separate entity and arch –just module

• Ports can be input, output, or inout

• Note: Verilog 2001 has alternative port style:– (input a, b, sel, output y);

– Also place in column:– (– input a,– input b,– input sel,– output y– );

Add assign statement

• Similar to VHDL conditional signal assignment – continuous assignment• Same hardware produced as with VHDL

Verilog - general comments

• VHDL is like ADA and Pascal in style• Strongly typed – more robust than Verilog• In Verilog it is easier to make mistakes

• Watch for signals of different widths• No default required for case statement, etc

• Verilog is more like the ‘c’ language• Verilog IS case sensitive• White space is OK• Statements terminated with semicolon (;)• Verilog statements between

• module and endmodule• Comments // single line and /* and */

Verilog

• Four-value logic system• 0 – logic zero, or false condition• 1 – logic 1, or true condition• x, X – unknown logic value• z, Z - high-impedance state

• Number formats• b, B binary• d, D decimal (default)• h, H hexadecimal• o, O octal

• 16’H789A – 16-bit number in hex format• 1’b0 – 1-bit

Example Synthesis Results (not Xilinx) Verilog Notes

• There is no explicit reference to actual hardware components– There are no D-type flip-flops, mux, etc– Required logic is inferred from the Verilog description– Same Verilog can target many different devices

• There are many alternative ways to describe the required behavior of the final system– Exactly the same hardware will be produced– Some ways are more intuitive and easier to read

• Remember that the synthesis tools must be able to deduce your intent and system requirements– For sequential circuits it is usually necessary to follow

recommended templates and style



Programmable Logic Devices

• Xilinx user programmable devices– FPGAs – Field Programmable Gate Array

• Virtex 4, 5, 6, Kintex-7

• Spartan 3, Spartan 6, Artix-7• Consist of configurable logic blocks

– Provides look-up tables to implement logic

– Storage devices to implement flip-flops and latches

– CPLDs – Complex Programmable Logic Devices• CoolRunner-II CPLDS (1.8 and 3.3 volt devices)

• XC9500 Series (3.3 and 5 volt devices)

• Consist of macrocells that contain programmable and-or matrix with flip-flops

• Altera has a similar range of devices

Electronic Components (Xilinx)

Source: Dataquest Logic

Standard Logic ASIC

ProgrammableLogic Devices(PLDs)

Gate Arrays

Cell-Based ICs

Full Custom ICs

CPLDsSPLDs (PALs) FPGAs

AcronymsSPLD = Simple Prog. Logic Device PAL = Prog. Array of Logic CPLD = Complex PLDFPGA = Field Prog. GateArray

Common ResourcesConfigurable Logic Blocks (CLB)

– Memory Look-Up Table– AND-OR planes– Simple gates

Input / Output Blocks (IOB)– Bidirectional, latches, inverters, pullup/pulldowns

Interconnect or Routing– Local, internal feedback, and global

Xilinx Products (Xilinx)

CPLDs and FPGAs

Architecture PAL/22V10-likeMore Combinational

Gate array-likeMore Registers + RAM

Density Low-to-medium 0.5-10K logic gates

Medium-to-high1K to 3.2M system gates

Performance Predictable timing Up to 250 MHz today

Application dependent Up to 200 MHz today

Interconnect “Crossbar Switch” Incremental

Complex Programmable Logic Device (CPLD)

Field-Programmable Gate Array (FPGA)

Overview of Xilinx FPGA Architecture (Xilinx)

Spartan-6/Artix-7 FPGA Family

• “Specifically designed to meet the needs of high volume, cost-sensitive consumer electronic applications.

• “Delivers an optimal balance of low risk, low cost, and low power for cost-sensitive applications”

• Offers advanced power management technology, up to 150K logic cells, PCI express blocks, memory support, DSP slices, and transceivers

• DSP48A slice contains 18 by 18 multiplier, adder and accumulator

Device CLBsslices

CLBflip-flops

DSP48Aslices

Block Ram

(18 Kb)

User IO

Price(1 off)

XC6LX16 2,278 18,224 32 32 232 $30XC7A35T 5,200 41,600 90 100 106 $39

XC7A100T 15,850 126,800 240 135 210 $123

Programmable Functional Elements

• Configurable Logic Blocks (CLBs)– RAM-based look-up tables to implement logic– Storage elements for flip-flops or latches

• Input/Output Blocks– Supports bidirectional data flow and 3-state operation– Supports different signal standards including LVDS– Double-data rate registers included– Digitally controlled impedance provides on-chip terminations

• Block RAM provides data storage– 18-Kbit dual-port blocks

• Multiplier blocks (accepts two 18-bit binary numbers)• Digital Clock Manager (DCM)

– Provides distribution, delaying, mult, div, phase shift of clocks



Slices and CLBs (Xilinx)

• Each Virtex�-II CLB containsfour slices– Local routing provides

feedback between slices in the same CLB, and it provides routing toneighboring CLBs

– A switch matrix provides accessto general routing resources

CIN

Switch Matrix

BUFT BUFT

COUTCOUT

SliceS0

SliceS1

LocalRouting

SliceS2

SliceS3

CIN

SHIFT

Slice 0

LUT Carry

LUT CarryPRE

D QCE

CLR

QD PRE CE

CLR

Simplified Slice Structure (Xilinx)

• Each slice has four outputs– Two registered outputs,

two non-registered outputs– Two BUFTs associated

with each CLB, accessible by all 16 CLB outputs

• Carry logic runs vertically, up only– Two independent

carry chains per CLB

Detailed Slice Structure (Xilinx)

Combinatorial Logic

A B

C D

Z

Look-Up Tables (Xilinx)

• Combinatorial logic is stored in Look-Up Tables (LUTs)– Also called Function Generators (FGs)– Capacity is limited by number of inputs,

• not complexity

• Delay through the LUT is constant

A B C D Z0 0 0 0 00 0 0 1 00 0 1 0 00 0 1 1 10 1 0 0 10 1 0 1 1

. . .1 1 0 0 01 1 0 1 01 1 1 0 01 1 1 1 1

Flexible Sequential Elements (Xilinx)

• Can be flip-flops or latches• Two in each slice; eight in each

CLB• Inputs can come from LUTs or

from an independent CLB input

• Separate set and reset controls– Can be synchronous or

asynchronous

• All controls are shared within a slice– Control signals can be inverted

locally within a slice

CE

CLR

D PRE Q

D PRE Q

CE

LDCPE

GCLR

FDRSE_1

D S Q

CE

R

FDCPE

IOB Element (Xilinx)

• Input path– Two DDR registers

• Output path– Two DDR registers– Two 3-state enable

DDR registers

• Separate clocks and clock enables for I and O

• Set and reset signals are shared

DDRMUX

3-state

RegOCK1

RegOCK2

DDRMUX

Output

RegOCK1

RegOCK2

PAD

Input

RegICK1

RegICK2

IOB



SelectIO Standard (Xilinx)

• Allows direct connections to external signals of varied voltages and thresholds– Optimizes the speed/noise tradeoff– Saves having to place interface components onto your board

• Differential signaling standards– LVDS, BLVDS, ULVDS– LDT– LVPECL

• Single-ended I/O standards– LVTTL, LVCMOS (3.3V, 2.5V, 1.8V, and 1.5V)– PCI-X at 133 MHz, PCI (3.3V at 33 MHz and 66 MHz)– GTL, GTLP– and more!

Digital Controlled Impedance (DCI)

• DCI provides– Output drivers that match the impedance of the traces– On-chip termination for receivers and transmitters

• DCI advantages– Improves signal integrity by eliminating stub reflections– Reduces board routing complexity and component count by

eliminating external resistors– Internal feedback circuit eliminates the effects of temperature,

voltage, and process variations

Block SelectRAM Resources (Xilinx)

• Up to 3.5 Mb of RAM in 18-kb blocks– Synchronous read and write

• True dual-port memory– Each port has synchronous read and

write capability– Different clocks for each port

• Supports initial values• Synchronous reset on output

latches• Supports parity bits

– One parity bit per eight data bits

Dedicated Multiplier Blocks (Xilinx)

• 18-bit twos complement signed operation• Optimized to implement multiply and accumulate

functions• Multipliers are physically located next to block

SelectRAM™ memory

18 x 18Multiplier

Output (36 bits)

Data_A (18 bits)

Data_B (18 bits)

4 x 4 signed8 x 8 signed

12 x 12 signed

18 x 18 signed

Nexys3 Board ($139 – now $189)

Note: The Nexys3 is no longer in production and is not recommended for new installations. When the current stock is depleted, it will be discontinued.

Nexys3 Board ($139 – now $189)

Note: The Nexys3 is no longer in production and is not recommended for new installations. When the current stock is depleted, it will be discontinued.

Basys 3 Artix-7 Board ($79)

• Based on latest Artix-7 FPGA (XC7A35T-1CPG236C)



Nexys 4 DDR Board ($159)

• Based on latest Artix-7 FPGA (XC7A100T-1CSG324C)

Xilinx Design Process (Xilinx)

• Step1: Design– Two design entry methods: HDL(Verilog or

VHDL) or schematic drawings• Step 2: Synthesize to create Netlist

– Translates V, VHD, SCH files into an industry standard format EDIF file

• Step 3: Implement design (netlist)– Translate, Map, Place & Route

• Step 4: Configure FPGA– Download BIT file into FPGA

HDL code Schematic

Netlist

Implement

Synthesize

BIT File

Synthesis CONSTRAINTS

Implementation CONSTRAINTS

Translate

Map

Place & Route

Xilinx Design Flow (Xilinx)

Plan & Budget HDL RTLSimulation

Synthesize to create netlist

Functional Simulation

Create Bit File

Attain Timing Closure

Timing Simulation

Implement

Create Code/ Schematic

Program the FPGA (Xilinx)

• There are three ways to program an FPGA

– Through a PROM device• You will need to generate a

file that the PROM programmer will understand

– Directly from the computer• Use the iMPACT

configuration tool• (need JTAG)

– Use USB connector• Digilent Adept tool

Decoder Tutorial Demo Example

led0

led1

led2

led3

led4

led5

led6

led7

sw0

sw1

sw2

Verilog Source Code



Synthesizing the Design

=========================================================================* HDL Synthesis *=========================================================================

Synthesizing Unit <decoder>.Related source file is "C:\ece3829\decoder\decoder.v". Found 8x8-bit Read Only RAM for signal <led>Summary:inferred 1 RAM(s).

Unit <decoder> synthesized.

View the Schematic Representation

Decoder Implemented on FPGA Zooming in on Logic Slice

Assigning Package Pins New Implementation to Match Target



Top-Down Design Hierarchy

• Instantiate module (counter example with decoder)module decoder(

count, seven_seg

input [3:0]output [6:0]);

// instantiate decoder module in counter// using position of ports (positional association) decoder d1 (count_val, seven_seg_val);

// or using formal and actual names (named association) decoder d1 (.count(count_val), .seven_seg(seven_seg_val));

Verilog and VHDL – Reminder

• VHDL - like Pascal and Ada programming languages• Verilog - more like ‘C’ programming language• But remember they are Hardware Description Languages -

They are NOT programming languages– FPGAs do NOT contain an hidden microprocessor or interpreter or

memory that executes the VHDL or Verilog code– Synthesis tools prepare a hardware design that is inferred from the

behavior described by the HDL– A bit stream is transferred to the programmable device to configure

the device– No shortcuts! Need to understand combinational/sequential logic

• Uses subset of language for synthesis• Check - could you design circuit from description?

Verilog – Basic Syntax

Verilog – logic and numbers

• Four-value logic system• 0 – logic zero, or false condition• 1 – logic 1, or true condition• x, X – unknown logic value• z, Z - high-impedance state

• Number formats• b, B binary• d, D decimal (default)• h, H hexadecimal• o, O octal

• 16’H789A – 16-bit number in hex format• 1’b0 – 1-bit

Verilog types

• Constants– parameter– parameter– parameter

DIME = 10;width = 32, nickel = 5; quarter = 8’b0010_0101;

• Nets– wire– wire[7:0]

clock, reset_n; a_bus;

• Registers– reg– reg[7:0]

clock, reset_n; a_bus;

• Integer– only for use as general purpose variables in loops– integer n;

Operators

• BitwiseVerilog VHDL– ~ negation

– & and– | inclusive– ^ exclusive––

y = a & b; y = a AND b; or y = a | b; y = A OR b; or y = a ^ b; y = a XOR b;

y = ~(a & b); y = A NAND b; y = ~ a; y = NOT a;

• Reduction (no direct equivalent in VHDL)– Accept single bus and return single bit result

y = & a_bus;• & and• ~& nand• | or• ^ exclusive

y = | a_bus; or



Operators (cont’d)

• Relational (return 1 for true, 0 for false)– < less than, <=– > greater than >=

• Equality– == logicalequality– != logicalinequality

• Logical Comparison Operators– ! logical negation– && logical and– || logical or

• Arithmetic Operators– +– -– *

Operators (cont’d)

• Shift– <<– >>

logical shift left, (<<< arithmetic) logical shift right (>>> arithmetic)

• Conditional– Only in Verilog - selects one of pair expressions– ?:– Logical expression before ? is evaluated– If true, the expression before : is assigned to output– If false, expression after : is assigned to output

• Y = (A > B) ? 1 : 0• Y = (A == B) ? A + B : A – B

Simple Combinational Example View Technology Schematic

Decoder Tutorial Demo Example

led0

led1

led2

led3

led4

led5

led6

led7

sw0

sw1

sw2

Verilog Source Code



Concurrent statements

• VHDL– Process– Signal assignments

• Verilog– always statement– Continuous assignment - assign

Verilog wire and register data objects

• Wire – net, connects two signals together– wire clk, en;– wire [15:0] a_bus;

• Reg – register, holds its value from one procedural assignment statement to the next– Does not imply a physical register – depends on use– reg [7:0] b_bus;

Index and Slice

• VHDL– Use to and downto to specify slice– Concatenation &

• c_bus(3 downto 0) <= b_bus(7 downto 4);• c_bus(5 downto 0) <= b_bus(7) & a_bus(6 downto 3) & ‘0’;

• Verilog– Use colon :– Concatenation {,}

• assign c_bus[3:0] = b_bus[7:4];• assign c_bus[5:0] = {b_bus[7], a_bus[6:3], 1’b0};

Internal wires

• Declare internal wires:

Sequential Statements

• VHDL– reside in process statement

• Verilog– reside in an always statement– if statements (no endif)– case statements (endcase)– for, repeat while loop statements

– Note: use begin and end to block sequential statements

Decoder – always statement

• 2 to 4 decoder with enable• Combinational logic using always statement with sensitivity list

– similar to VHDL process – for cyclic behavior– (@) event control operator– begin .. end block statement– note reg for y



Decoder (cont’d)

• Combinational logic using always statement with sensitivity list– similar to VHDL process – for cyclic behavior– (@) event control operator– begin .. end block statement

• Statements execute sequentially

– if statement– case statement

• Note: case expression can concatenate signals ({,})– Sensitivity list

• (a or b or c)• Verilog 2001 allows comma-separated list (a, b, c)

Decoder – CASE statement

• CASE is better for this type of design - no priority– Exactly same logic produced

Decoder – 3 to 8 with CASE MUX example

• Example multiplexer with conditional operator• Selects different values for the target signal

– priority associated with series of conditions– (similar to an IF statement)

q

i0i1i2i3

a.b.

Synthesis Results – Technology Schematic

O = ((I0 * I1 * I3) + (!I0 * I1 * I4) + (!I0 * !I1 * I5) + (I0 * !I1 *I2));

Mux – with CASE statement

• Include all inputs on sensitivity listElaborating module <mux_case>.WARNING:HDLCompiler:91 - "C:\ece3829\mux_case\mux_case.v" Line 34: Signal <i> missing in the sensitivity list is added for synthesis purposes. HDL and post-synthesis simulations may differ as a result.



Mux – fixed sensitivity list

• Exact same logic produced as using conditional operator

Priority Encoder

• Priority Encoder using conditional operator• Priority order determined by sequence

– similar to if-else statement

Encoder – Technology Schematic=========================================================================* HDL Synthesis *=========================================================================Synthesizing Unit <encoder>.

Related source file is "C:\ece3829\encoder\encoder.v".WARNING:Xst:647 - Input <i0> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Summary:inferred 2 Multiplexer(s).

Unit <encoder> synthesized.

==============================================HDL Synthesis Report

Macro Statistics# Multiplexers2-bit 2-to-1 multiplexer

: 2: 2

==============================================

=================

=================

Add ‘gs’ output

Synthesize - Design Summary=========================================================================* Design Summary *=========================================================================

Clock Information:------------------No clock signals found in this design

Asynchronous Control Signals Information:----------------------------------------No asynchronous control signals found in this design

Timing Summary:---------------Speed Grade: -3

Minimum period: No path foundMinimum input arrival time before clock: No path found Maximum output required time after clock: No path found Maximum combinational path delay: 5.456ns

=========================================================================

Implement DesignDevice Utilization Summary:

Slice Logic Utilization:Number of Slice Registers: 0 out of 18,224 0%Number of Slice LUTs: 2 out of 9,112 1%

Number used as logic: 2 out of 9,112 1%Number using O6 output only: 1Number using O5 output only: 0Number using O5 and O6: 1

Number used as ROM: Number used as Memory:

00 out of 2,176 0%

Slice LogicNumber of

Distribution:occupied Slices: 2 out of 2,278 1%

Number of MUXCYs used: 0 out of 4,556 0%Number of LUT Flip Flop pairs used: 2Number with an unused Flip Flop: 2 out of 2 100%Number with an unused LUT: 0 out of 2 0%Number of fully used LUT-FF pairs: 0 out of 2 0%Number of slice register sites lost

to control set restrictions: 0 out of 18,224 0%



Creating adder – using LUTs Technology Schematic

Example of simple mistake

• No errors or warnings!

Top-Down Design Hierarchy

• Instantiate module (counter example with decoder)

count, seven_seg

module decoder( input [3:0]output [6:0]);

// instantiate decoder module in counter// using position of portsdecoder d1 (count_val, seven_seg_val);

// or using formal and actual namesdecoder d1 (.count(count_val), .seven_seg(seven_seg_val));

Tri-state example

• Using conditional operator in continuous assignment

Documents

EE260: Digital Design, Spring 2018 6-Feb-18€¦ · EE260: Digital Design, Spring 2018 6-Feb-18 Verilog HDL 1: Introduction of FPGA and Verilog 1 Verilog –Module 1 Introduction