EE247 Lecture 11 - University of California, Berkeley

EECS 247 Lecture 11: SC Filters/ DACs © 2005 H. K. Page 1

EE247Lecture 11

• Switched-Capacitor Filters (continued)

– Effect of non-idealities– Bilinear switched-capacitor filters– Filter design summary

• Comparison of various filter topologies

• Data Converters


Summary Last Lecture

• Switched-capacitor filter design considerations– DDI & LDI Integrator characteristics– Bottom-plate LDI integrator à overcomes parasitic

sensitivity issues– Continuous-time and complex conjugate terminations

– Use of T-networks to implement high capacitor ratios

• Switched-capacitor filters utilizing double sampling technique

• Effect of non-idealities– Opamp finite gain– Opamp finite bandwidth (this lecture)– Finite slew rate of the opamp (this lecture)


Effect of Opamp Non-IdealitiesFinite Opamp Bandwidth

Input/Output z-transform

Vi+

Cs-

+ Vo

CIφ1 φ2

Vi-

Unity-gain-freq.

= ft

Vo

φ2

T=1/fs

settlingerror

time

Ref: K.Martin, A. Sedra, “Effect of the OPamp Finite Gain & Bandwidth on the Performance of Switched-Capacitor Filters," IEEE Trans. Circuits Syst., vol. CAS-28, no. 8, pp. 822-829, Aug 1981.

Assumption-

Opamp à does not slew (will be revisited)Opamp has only one pole à exponential settling


Effect of Opamp Non-IdealitiesFinite Opamp Bandwidth

actual idealIk k 1

I s

I t

I s s

t s

C1 e e ZH ( Z ) H ( Z )

C C

C fwhere k

C C ff Opamp unity gain frequency , f Clock frequency

π

− − − − + ×≈ +

= × ×+

→ − − →

Input/Output z-transform

Vi+

Cs-

+ Vo

CIφ1 φ2

Vi-

Unity-gain-freq.

= ft


Vo

φ2

T=1/fs

settlingerror

time


Effect of Opamp Finite Bandwidth on Filter Magnitude Response

Magnitude deviation due to finite opamp unity-gain-frequency

Example: 2nd

order bandpass with Q=25

fc /ft

|Τ|non-ideal /|Τ|ideal (dB)

fc /fs=1/32fc /fs=1/12

Active RC



Effect of Opamp Finite Bandwidth on Filter Magnitude Response

Example:For 1dB magnitude response deviation:1- fc/fs=1/12

fc/ft~0.04à ft>25fc

2- fc/fs=1/32fc/ft~0.022à ft>45fc

3- Cont.-Timefc/ft~1/700à ft >700fc fc /ft

|Τ|non-ideal /|Τ|ideal (dB)

fc /fs=1/32fc /fs=1/12

Active RC


Effect of Opamp Finite Bandwidth Maximum Achievable Q

fc /ft

Max. allowable biquad Q for peak gain change <10%

C.T. filters

Ref: K.Martin, A. Sedra, “Effect of the Opamp Finite Gain & Bandwidth on the Performance of SwitchedCapacitor Filters," IEEE Trans. Circuits Syst., vol. CAS-28, no. 8, pp. 822-829, Aug 1981.

Oversampling Ratio


Effect of Opamp Finite Bandwidth Maximum Achievable Q

fc /ft

C.T. filters

Example:For Q of 40 required Max. allowable biquad Q for peak gain change <10%

1- fc/fs=1/32fc/ft~0.02à ft>50fc

2- fc/fs=1/12fc/ft~0.035à ft>28fc

3- fc/fs=1/6fc/ft~0.05à ft >20fc



Effect of Opamp Finite Bandwidth on Filter Critical Frequency

Critical frequency deviation due to finite opamp unity-gain-frequency

Example: 2nd

order filterfc /ft

∆ωc /ωc

fc /fs=1/32

fc /fs=1/12

Active RC



Effect of Opamp Finite Bandwidth on Filter Critical Frequency

fc /ft

∆ωc /ωc

fc /fs=1/32

fc /fs=1/12

Active RC

Example:For maximum critical frequency shift of <1%

1- fc/fs=1/32fc/ft~0.028à ft>36fc

2- fc/fs=1/12fc/ft~0.046à ft>22fc

3- Active RCfc/ft~0.008à ft >125fc

C.T. filters



Double-Sampled Fully Differential 6th Order S.C. All-Pole Bandpass Filter

Ref: B.S. Song, P.R. Gray "Switched-Capacitor High-Q Bandpass Filters for IF Applications," IEEE Journal of Solid State Circuits, Vol. 21, No. 6, pp. 924-933, Dec. 1986.

-Cont. time termination (Q) implementation-Folded-Cascode opamp with fu = 100MHz used-Center freq. 3.1MHz, filter Q=55-Clock freq. 12.83MHz à effective oversampling ratio 8.27-Measured dynamic range 46dB (IM3=1%)


Sources of Distortion in Switched-Capacitor Filters

• Distortion induced by finite slew rate of the opamp

• Opamp output/input transfer function non-linearity

• Distortion incurred by finite setting time of the opamp

• Capacitor non-linearity• Distortion due to switch clock feed-through

and charge injection


What is Slewing?

oV

Vi+Vi-

φ2

Cs

-

+

Vin

Vo

φ2

CI

Cs

CI

CL

Assume opamp is of a simple differential-pair class A transconductance type

Iss


What is Slewing?Io

VinVmax

-Iss/2

Slope ~ gm

Vin <+-Vmax à Io=gmVin Vin >+-Vmax à Io=Imax

Class A amplifiers where the maximum output current is limited to Iss:

oV

Vi-

Iss

Vi+

Class A amplifier input stage

Iss/2

oI


What is Slewing?

oV

Vi+Vi-

φ2

Cs

CI

CL

If at the rising edge of φ2 : Vcs > Vmax à Output current constant Io=Iss/2à Slewing

After Vcs is discharged enough to have Vcs < Vmaxà Linear settling

Iss

Io

Io

VinVmax

-Iss/2

Slope ~ gmIss/2


Distortion Induced by Opamp Finite Slew Rate


Ideal Switched-Capacitor Integrator Output Waveform

φ1

φ2

Vin

Vo

Vcs

Clock-

+

Vin

Vo

φ1

CI

Cs

-

+

Vin

Vo

φ2

CI

Cs

φ2 High àCharge transferred from Cs to CI


Slew Limited Switched-Capacitor IntegratorOutput Settling

φ1

φ2

Vo-real

Vo-ideal

Clock

Slewing LinearSettling



Distortion Induced by Finite Slew Rate of the Opamp

Ref: K.L. Lee, “Low Distortion Switched-Capacitor Filters," U. C. Berkeley, Department of Electrical Engineering, Ph.D. Thesis, Feb. 1986 (ERL Memorandum No. UCB/ERL M86/12).


Distortion Induced by Opamp Finite Slew Rate

• Error due to exponential settling changes linearly with signal amplitude

• Error due to slew-limited settling changes non-linearly with signal amplitude (doubling signal amplitude X4 error)

àFor high-linearity need to have either high slew rate or non-slewing opamp

( )( )

( )

o s

o s

2T2ok 2r s

2T2o3

r s

8 sinVHD S T k k 4

8 sinVHD S T 15

ω

ω

π

π

=−

→ =



Example: Slew Related Harmonic Distortion


( )o s2T

2o3

r s

8 sinVHD S T 15

ω

π=

Switched-capacitor filter with 4kHz bandwidth, fs=128kHz, Sr=1V/µsec, Vo=3V


Distortion Induced by Opamp Finite Slew Rate Example

-120

-100

-80

-60

-40

-20

1 10 100 1000

HD

3 [d

B]

(Slew-rate / fs ) [V]

f / fs =1/32

f / fs =1/12

Vo =1V V

o =2V

Vo =1V V

o =2V


Distortion Induced by Finite Slew Rate of the Opamp

• Note that for a high order switched capacitor filter à only the last stage slewing will affect the output linearity (as longas the previous stages settle to the required accuracy)à Can reduce slew limited linearity by using an amplifier with a

higher slew rate only for the last stageà Can reduce slew limited linearity by using class A/B amplifiers

• Even though the output/input characteristics is non-linear the significantly higher slew rate compared to class A amplifiers helps improve slew rate induced distortion

• In cases where the output is sampled by another sampled data circuit (e.g. an ADC or a S/H) à no issue with the slewing of the output as long as the output settles to the required accuracy & is sampled at the right time


More Realistic Switched-Capacitor Circuit Slew Scenario

-

+

Vin

Vo

φ2

CI

Cs

At the instant Cs connects to input of opamp (t=0+)à Opamp not yet active at t=0+ due to finite opamp delayà Feedforward path from input to output generates a voltage spike at the

output spike magnitude function of CI, CL, Cs

à Spike increases slewing periodà Eventually, opamp becomes active & starts slewing

CL

Vo

φ2

CI

CsCL

t=0+


More Realistic SC Slew Scenario

Vo-realIncluding t=0+spike


Slewing

Spike generated at t=0+

Vo-real

Vo-ideal



Ref: R. Castello, “Low Voltage, Low Power Switched-Capacitor Signal Processing Techniques," U. C. Berkeley, Department of Electrical Engineering, Ph.D. Thesis, Aug. ‘84 (ERL Memorandum No. UCB/ERL M84/67).


Sources of Noise in Switched-Capacitor Filters

• Opamp Noise– Thermal noise– 1/f (flicker) noise

• Thermal noise associated with the switching process (kT/C)– Same as continuous-time filters

• Precaution regarding aliasing of noise required


Other z domain IntegratorsExample: Bilinear

• Bilinear integrator

( ) ( ) ( ) ( )

( )

1 1

1

1

1 ( ) 1 ( )

( ) 1( ) 1

o o i i

o i

o

i

v nT v nT T k v nT v nT T

z V z k z V z

V z zH z k

V z z

− −

−

−

= − + + − − = +

+= =

−


Bilinear Integrator

sI

j Tsj TI

sI s

1CC 1

CC 1

C sC Ts

2

1 ZH( Z )1 Z1 e

eT1

j T tan

ωω

ωω

ω

−+−

−−

−

+= − ×−

=− ×

=

Ideal Integrator Magnitude Error

No Phase Error! For signals at frequency <<sampling freq.

àMagnitude error negligible

Ref: R. Gregorian, G. Temes, “Analog CMOS Integrated Circuits," Wiley, 1986, pp 277 .

-Not implemented by “standard” SC integrators-Synthesis:

Biquads: direct coefficient comparisonExample: Bilinear S.C. integrator:


LDI & Bilinear TransformationFrequency Warping

LDI :

Bilinear

1/ 21 s

s

j Tj T s

s

sT

2T

2s

1 s1 T1

2T

2s

T 11 Z21 Z js in

2 js inT

T 11 e1 1 Z2e1 Z jtan

2 j tanT

s

s

s

s

ωω

ω

ω

ω

ω

−−

−+−

−

−− −

⇒ =

⇒

+⇒ = =−

⇒


Other z domain IntegratorsExample: Bilinear

• Frequency translation

( ) 2

2

1

tan

jf TSC

RC

SC z es jf

s SCRC

s

H zs

f ff

f

π

π

ππ

==

=

=

=

s

SCsRC f

fff π

πsin

Bilinear LDI


Bilinear Transform

• Entire jω axis maps onto the unit circle

• Mapping is nonlinear (tan distortion)à prewarp specifications of RC prototype Matlab filter design automates this (see, e.g. bilinear)

=

s

SCsRC f

fff π

πtan

0 0.5 1 1.5 2 2.5 3

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4

0.45

0.5

f sc /f

s

fRC /fs


Bilinear & LDI Transformation Frequency Warping

As long as f<<fs error negligible


“Bilinear” Bandpass

fs = 100kHzfc = fs/8Q = 10

Matlab:

0.0378 z^2 - 0.0378H(z) = ----------------------

z^2 - 1.362 z + 0.9244

zero at fs/2

Pole-Zero Map

Real Axis

Imag

Axi

s

-1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1-1

-0.8

-0.6

-0.4

-0.2

0

0.2

0.4

0.6

0.8

1


( )( )

( ) ( )( ) ( )656554

252352513

23

122

KKzKKKKzKKKzKKKKKzK

zVzV

i

o

−+++−+−+++−+

=

phi1phi1 phi1

phi2 phi2

K1 CA = 0F

-1M-1M

CA = 1pFCA = 1pFCA = 1pFCA = 1pF

phi1phi1 phi2

phi2 phi1

K5 CB = 500fF

-1M-1M-1M-1M

CB = 1pF

phi1phi1 phi1

phi2 phi2

K4 CA = 1.125pF

K3 CB = 37.8fF

K2 CA = 151.2fF

K6 CA = 151.2fF

VoVi

Martin-Sedra Biquad

Periodic AC Analysis PAC1log sweep from 1k to 50k (300 steps)

fs = 100kHzCLK1

V1ac = 1V

Ref: K. Martin and A. S. Sedra, “Strays-insensitive switched-capacitor filters based on the bilinear z transform,” Electron. Lett., vol. 19, pp. 365-6, June 1979.


Magnitude Response

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

x 105

-70

-60

-50

-40

-30

-20

-10

0

Frequency [Hz]

Mag

nitu

de [

dB]


LDI vs Bilinear Transform• LDI transform:

– Realized by “standard” switched-capacitor integrators– Some high frequency zeros may get lost– Simple filter synthesis:

• Replace RC integrators with SC integrators• Ensure clock phases chosen so that all integrators loops LDI type

• Bilinear transform– Not implemented by “standard” SC integrators– Synthesis:

• Biquads: direct coefficient comparison• Ladders: see

R. B. Datar and A. S. Sedra, “Exact design of strays-insensitive switched capacitor high-pass ladder filters”, Electron. Lett., vol. 19, no 29, pp. 1010-12, Nov. 1983.


Switched-Capacitor Filter ApplicationExample: Voice-Band Codec (Coder-Decoder) Chip

Ref: D. Senderowicz et. al, “A Family of Differential NMOS Analog Circuits for PCM Codec Filter Chip,” IEEE Journal of Solid-State Circuits, Vol.-SC-17, No. 6, pp.1014-1023, Dec. 1982.

fs= 1024kHz fs= 128kHz fs= 8kHz fs= 8kHz

fs= 8kHz fs= 128kHz fs= 128kHz

fs= 128kHz


CODEC Transmit Path Lowpass Filter Frequency Response

0 2000 4000 6000 8000-50

-40

-30

-20

-10

0

Frequency (Hz)

Mag

nit

ud

e (d

B)

Note: fs=128kHz


CODEC Transmit Path Highpass Filter

1000-50

-40

-30

-20

-10

0

Frequency (Hz)

Mag

nit

ud

e (d

B)

1000010010

Note: fs=8kHz


CODEC Transmit Path Filter Overall Frequency Response

1000-50

-40

-30

-20

-10

0

Frequency (Hz)

Mag

nit

ud

e (d

B)

1000010010

Low Q bandpass (Q<1) filter shapeà Implemented with lowpass followed by highpass


CODEC Transmit Path Clocking Scheme

First filter (1st order RC type) performs anti-aliasing for the next S.C. biquad

The first 2 stage filters form 3rd order elliptic with corner frequency @ 32kHz à Anti-aliasing for the next lowpass filter

The stages prior to the high-pass perform anti-aliasing for high-pass

Notice gradual lowering of clock frequencyà Ease of anti-aliasing


SC Filter Summary

ü Pole and zero frequencies proportional to – Sampling frequency fs– Capacitor ratiosØ High accuracy and stability in responseØ Long time constants realizable without large R, C

ü Compatible with transconductance amplifiers– Reduced circuit complexity, power dissipation

ü Amplifier bandwidth requirements less stringent compared to CT filters (low frequencies only)

L Issue: Sampled-data filters à require anti-aliasing prefiltering


Switched-Capacitor Filters versus Continuous-Time Filter Limitations

Considering overall effects:

•Opamp finite unity-gain-bandwidth

•Opamp settling issues

•Opamp finite slew rate

•Clock feedthru• Switch+ sampling cap. finite time-constant

Filter bandwidthAssuming constant opamp fu

MagnitudeError

5-10MHz

S.C. Filter

Cont. Time Filter

à Limited switched-capacitor filter performance frequency range


SummaryFilter Performance versus Filter Topology

_

1-5%

1-5%

1-5%

1-5%

Freq. tolerance+ tuning

<<1%40-90dB~ 10MHzSwitched Capacitor

+-40-60%40-70dB~ 100MHzGm-C

+-30-50%50-90dB~ 5MHzOpamp-MOSFET-RC

+-30-50%40-60dB~ 5MHzOpamp-MOSFET-C

+-30-50%60-90dB~10MHzOpamp-RC

Freq. tolerance w/o tuning

SNDRMax. Usable Bandwidth


Data Converters


Material Covered in EE247ü Filters

– Continuous-time filters• Biquads & ladder type filters• Opamp-RC, Opamp-MOSFET-C, gm-C filters• Automatic frequency tuning

– Switched capacitor (SC) filters• Data Converters

– D/A converter architectures– A/D converter

• Nyquist rate ADC- Flash, Pipeline ADCs,….• Oversampled converters• Self-calibration techniques

• Systems utilizing analog/digital interfaces– Wireline communication systems- ISDN, XDSL…– Wireless communication systems- Wireless LAN, Cellular

telephone,…– Disk drive electronics– Fiber-optics systems


Data Converter Topics• Basic Operation of Data Converters

– Uniform sampling and reconstruction

– Uniform amplitude quantization

• Characterization and Testing

• Common ADC/DAC Architectures

• Selected Topics in Converter Design– Practical Implementations

– Desensitization to Analog Circuit Non-Idealities

• Figures of Merit and Performance Trends


Suggested Reference Texts• R. v. d. Plassche, CMOS Integrated Analog-to-Digital and

Digital-to-Analog Converters, 2nd ed., Kluwer, 2003.

• B. Razavi, Data Conversion System Design, IEEE Press, 1995.

• S. Norsworthy et al (eds), Delta-Sigma Data Converters, IEEE Press, 1997.Extensive treatment of oversampled converters including stability, tones, bandpass converters.

• J. G. Proakis, D. G. Manolakis, Digital Signal Processing, Prentice Hall, 1995.


Converter Applications


Example: Typical Cell PhoneContains in integrated form:• 4 Rx filters• 4 Tx filters

• 4 Rx ADCs• 4 Tx DACs• 3 Auxiliary ADCs• 8 Auxiliary DACs

Total: Filters à 8

ADCs à 7

DACs à 12

Dual Standard, I/Q

Audio, Tx/Rx powercontrol, Battery chargecontrol, display, ...


Data Converter Basics

• DSP is wonderful, but...• Real world signals are analog:

– Continuous time– Continuous amplitude

• DSP can only process:– Discrete time– Discrete amplitudeà Need for data conversion from

analog to digital and digital to analog

Analog Postprocessing

D/AConversion

DSP

A/D Conversion

Analog Preprocessing

Analog Input

Analog Output

000...001...

110

Filters

Filters

?

?


A/D & D/A ConversionA/D Conversion

D/A Conversion


Data Converters

• Stand alone data converters– Used in variety of systems

– Example: Analog Devices AD9235 12bit/ 65Ms/s ADC- Applications:

• Ultrasound equipment

• IF sampling in wireless receivers

• Hand-held scopemeters

• Low cost digital oscilloscopes


Data Converters• Embedded data converters

– Cost, reliability, and performance à integration of data conversion interfaces along with DSPs

– Main issues• Feasibility of integrating sensitive analog functions in a

technology optimized for digital performance

• Down scaling of supply voltage

• Interference & spurious signal pick-up from on-chip digital circuitry

• Portable applications dictate low power consumption


D/A Converter Transfer Characteristics

• For an ideal digital-to-analog converter with uniform, binary digital encoding & a unipolar output range from 0 to VFS

N N

0 FSi 1 i 1

N ii

biV V bi 2 , bi 0 or 1

2= =

−= = ∆ × =∑ ∑D/A

……..…b1 b2 b3 bn

V0

( )0 FS

FS N

Note:V Vbi 1,a l l i1

1V2

= −∆= −=

MSB LSB

( )0 2 1 0

Example:N 3

V b1.2 b2.2 b3.2

=

= ∆ + +FS

FSN

where N # of bitsV ful l scale output

step sizeV

2

==

∆ =

∆ =


Ideal D/A Transfer Characteristic• Ideal DAC

introduces no error!

• One-to-one mapping from input to output

001 010 011 100 101 110 111

Step Height (1LSB=∆)

Ideal Response

Digital InputCode

Analog Output

VFS

VFS /2

VFS /8


A/D Converter Transfer Characteristic

• For an ideal analog-to-digital converter with uniform, binary digital encoding & a unipolar input range for 0 to VFS

……..…b1 b2 b3 bm

Vin

( ) FS

FS m

Note:D Vbi 1,a l l i1

1V2

→ −∆= −→

MSB LSB

A/D

FS

FSm

where m # of bitsV ful l scale output

s tep sizeV

2

==

∆ =

∆ =


Ideal A/D Transfer Characteristic• Ideal ADC

introduces error à(+-1/2∆)

∆= VFS /2m

m= # of bits

• This error is called ``quantization error``

111

110

101

100

011

010

001

000

1LSB

Digital Output

Analog input

∆ 2∆ 3∆ 4∆ 5∆ 6∆ 7∆


Data Converter Performance Metrics• Data Converters are typically characterized by static, time-domain,

& frequency domain performance metrics :– Static

• Monotonicity• Offset• Gain error• Differential nonlinearity (DNL)• Integral nonlinearity (INL)

– Dynamic• Delay, settling time• Aperture uncertainty• Distortion- harmonic content• Signal-to-noise ratio (SNR), Signal-to-(noise+distortion) ratio (SNDR)• Idle channel noise• Dynamic range & spurious-free dynamic range (SFDR)


What is a discrete time signal?qA signal that changes only at

discrete time instances?

qA continous time signal multiplied with a train of infinitely narrow unit pulses?

qA vector whose element indices correspond to discrete instances in time?

qAll of the above?

[1.2 2.0 2.5 0.1 ...]

time


Discrete Time Signals• A sequence of numbers (or vector) with

discrete index time instants• Intermediate signal values not defined

(not the same as equal to zero!)• Mathematically convenient, non-physical• We will use the term "sampled data" for

related signals that occur in real, physical interface circuits


Typical Sampling ProcessCT ⇒ SD ⇒ DT

ContinuousTime

Sampled Data(e.g. T/H signal)

Clock

Discrete Time

time

PhysicalSignals

"MemoryContent"


Uniform Sampling

• Samples spaced T seconds in time

• Sampling Period T ⇔ Sampling Frequency fs=1/T

• Problem: Multiple continuous time signals can yield exactly the same discrete time signal (aliasing)

y(kT)=y(k)

t= 1T 2T 3T 4T 5T 6T ...k= 1 2 3 4 5 6 ...


SummaryData Converters

• ADC/DACs need to sample/reconstruct to convert from continuous time to discrete time signals and back

• We distinguish between purely mathematical discrete time signals and "sampled data signals" that carry information in actual circuits

• Question: How do we ensure that sampling/reconstruction preserves information

Documents

EE247 Lecture 11 - University of California, Berkeley