EE247 Lecture 10 - EECS Instructional Support Group …ee247/fa05/lectures/L10_f05.pdf · EE247 Lecture 10 • Switched ... z-Transform Model 1 2 1 2 1 11 11 zz ... LDI Switched-Capacitor

EECS 247 Lecture 10: SC Filters © 2005 H. K. Page 1

EE247Lecture 10

• Switched-Capacitor Filters– Switched-capacitor integrators

• DDI integrators• LDI integrators• Effect of parasitic capacitance• Bottom-plate integrator topology

– Resonators– Bandpass filters– Lowpass filters

• Termination implementation• Transmission zero implementation

– Switched-capacitor filter design considerations– Switched-capacitor filters utilizing double sampling technique – Effect of non-idealities


Switched-Capacitor Integrator

-

+

Vin

Vo

φ1 φ2

CI

Cs

Vs

φ1 φ2 φ1 φ2φ1

Vin

Vo

Vs

Clock


DDI Switched-Capacitor Integrator

φ1 φ2 φ1 φ2φ1

Vin

Vo

Vs

Clock

Vo1

-

+

Vin

Vo1

φ1 φ2

CI

Cs

φ1

Vo


φ1 φ2 φ1 φ2φ1

Vin

Vo

Vs

Clock

DDI Switched-Capacitor Integrator(n-1)Ts nTs(n-1/2)Ts (n+1)Ts

Φ1 à Qs [(n-1)Ts]= Cs Vi [(n-1)Ts] , QI [(n-1)Ts] = QI[(n-3/2)Ts]

Φ2 à Qs [(n-1/2) Ts] = 0 , QI [(n-1/2) Ts] = QI [(n-3/2) Ts] + Qs [(n-1) Ts]

Φ1 _à Qs [nTs ] = Cs Vi [nTs ] , QI [nTs ] = QI[(n-1) Ts ] + Qs [(n-1) Ts]

Since Vo1= - QI /CI & Vi = Qs / Csà CI Vo1(nTs) = CI Vo1 [(n-1) Ts ] -Cs Vi [(n-1) Ts ]

(n-3/2)Ts (n+1/2)Ts

Vo1


DDI Switched-Capacitor IntegratorOutput Sampled on φ1

sIsI

1s1I

o s o ss sI I inCo s o s sinCC1 1o o inC

CC 1

in

C V (nT ) C V C V( n 1)T ( n 1)T

V (nT ) V V( n 1)T ( n 1)T

V ( Z ) Z V ( Z ) Z V ( Z )

Vo Z( Z )ZV

−−

− −

−

− = − +− −

= −− −

= −

= − ×

DDI (Direct-Transform Discrete Integrator)

-

+

Vin

Vo

φ1 φ2

CI

Cs

φ1


z-Domain Frequency Response• LHP singularities in s-plane map

into inside of unit-circle in Z domain• RHP singularities in s-plane map

into outside of unit-circle in Z domain

• The jω axis maps onto the unit circle• Particular values:

– f = 0 à z = 1– f = fs/2 à z = -1

• The frequency response is obtained by evaluating H(z) on the unit circle at z = ejωT = cos(ωT)+jsin(ωT)

• Once z=-1 (fs/2) is reached, the frequency response repeats, as expected

• The angle to the pole is equal to 360° (or 2π radians) times the ratio of the pole frequency to the sampling frequency

(cos(ωT),sin(ωT))

2πffS

f = 0

f = fs/2

LHP in s domain

imag. axis in s domain


Switched-Capacitor Direct-Transform Discrete Integrator

1s1I

s 1I

CC 1

inCC 1

Vo Z( Z )ZV

Z

−−−

= − ×

= − × −

-

+

Vin

Vo

φ1 φ2

CI

Cs

φ1


DDI IntegratorPole-Zero Map in z-Plane

Z-1=0 à Z=1on unit circle

Pole from fà0in s-plane mapped to z=+1

As frequency increases z domain pole moves on unit circle (CCW)

Once pole gets to (Z=-1 ),(f=fs /2), frequency response repeats

z-plane

f = fs/2

f

f1

1

(Z-1)increasing


DDI Switched-Capacitor IntegratorCI

Ideal Integrator) Magnitude Error Phase Error

( )

( )

1s1I

j T / 2s sj T j T / 2 j T / 2I I

sI

sI

C j TC 1

in

C CC C1

C j T / 2C

C j T / 2C j T

Vo Z( Z ) , Z eZV

e1e e e

1j e 2sin T / 2

T / 21 esin T / 2

ωω ω ω

ω

ω

ω

ω

ωω ω

−−

−−

−

− −

−

−

= − × =

= × = ×

= − × ×

= − × ×

-

+

Vin

Vo

φ1 φ2

CI

Cs

φ1


DDI Switched-Capacitor Integrator

Example: Mag. & phase error for:1- f / fs=1/12 àMag. Error = 1% or 0.1dB

Phase error=15 degreeQintg = -3.8

2- f / fs=1/32 àMag. Error=0.16% or 0.014dBPhase error=5.6 degreeQintg = -10.2

CI

-

+

Vin

Vo

φ1 φ2

CI

Cs

φ1

DDI Integratorà magnitude error no problem

phase error major problem


Switched Capacitor Filter Build with DDI Integrator

Example: 5th Order Elliptic FilterSingularities pushed towards RHP due to integrator excess phase

s-planeFine View

jω

σ

PoleZero

s-planeCoarse View

jω

σ

ωs

-ωs


Frequency (Hz)

Switched Capacitor Filter Build with DDI Integrator

( )ωjH

sf / 2 sf 2fs fContinuous-TimePrototype

SC DDI basedFilter

PassbandPeaking

Zeros lost!


Switched-Capacitor Integrator Output Sampled on φ2

CI

-

+

Vin

Vo2

φ1 φ2

CI

Cs

φ2

Sample output ½ clock cycle earlier

à Sample output on φ2

Vo


Φ1 à Qs [(n-1)Ts]= Cs Vi [(n-1)Ts] , QI [(n-1)Ts] = QI[(n-3/2)Ts]

Φ2 à Qs [(n-1/2) Ts] = 0 , QI [(n-1/2) Ts] = QI [(n-3/2) Ts] + Qs [(n-1) Ts]

Φ1 _à Qs [nTs ] = Cs Vi [nTs ] , QI [nTs ] = QI[(n-1) Ts ] + Qs [(n-1) Ts]

Φ2 à Qs [(n+1/2) Ts] = 0 , QI [(n+1/2) Ts] = QI [(n-1/2) Ts] + Qs [n Ts]

φ1 φ2 φ1 φ2φ1

Vin

Vo2

Vs

Clock

(n-1)Ts nTs(n-1/2)Ts (n+1)Ts(n-3/2)Ts


(n+1/2)Ts


QI [(n+1/2) Ts] = QI [(n-1/2) Ts] + Qs [n Ts]Vo2= - QI /CI & Vi = Qs / Csà CI Vo2 [(n+1/2) Ts] = CI Vo2 [(n-1/2) Ts ] -Cs Vi [n Ts ]Using the z operator rules:

à CI Vo2 Z1/2 = CI Vo2 Z-1/2 - Cs Vi

1/ 2s1I

CC 1

in

Vo2 Z( Z )ZV

−−−

= − ×


φ1 φ2 φ1 φ2φ1

Vin

Vo

Vs

Clock

(n-1)Ts nTs(n-1/2)Ts (n+1)Ts(n-3/2)Ts


LDI Switched-Capacitor Integrator

( )

( )

1/ 2s1I

j T / 2s e s 1j T j T / 2 j T / 2I I

sI

sI

C j TC 1

in

C CC C1

CC

CC j T

Vo2 Z( Z ) , Z eZV

e e e

1j 2sin T / 2

T / 21sin T / 2

ωω ω ω

ω

ω

ωω ω

−−

−− − +

−

− −

= − × =

= − × = ×

= − ×

= − ×

CI

Ideal Integrator Magnitude Error

No Phase Error! For signals at frequencies << sampling freq.

àMagnitude error negligible

-

+

Vin

Vo2

φ1 φ2

CI

Cs

φ2

LDI

LDI (Lossless Discrete Integrator) àsame as DDI but output is sampled ½clock cycle earlier


Frequency Warping

• Frequency response– Continuous time (s-plane): imaginary axis– Sampled time (z-plane): unit circle

• Continuous to sampled time transformation– Should map imaginary axis onto unit circle– How do SC integrators map frequencies?

fTjCC

zz

CC

zH

πsin21

1)(

int

s

1int

sSC

21

−=

−= −

−


CT – SC Integrator Comparison

CT Integrator SC Integrator

τπ

τ

RCjf

ssH

21

1)(RC

−=

−=

TfjCC

zz

CC

zH

SCπsin21

1)(

int

s

1int

sSC

21

−=

−= −

−

ssCfC

RC int==τ

Identical time constants:

Compare: HRC(fRC) = HSC(fSC) à

=

s

SCsRC f

fff π

πsin


LDI Integration

=

s

SCsRC f

fff π

πsin

• “RC” frequencies up to fs /πmap to physical (real) “SC”frequencies

• Frequencies above fs /π do not map to physical frequencies

• Mapping is symmetric about fs /2 (aliasing)

• “Accurate” only for fRC << fs0 0.05 0.1 0.15 0.2 0.25 0.3 0.350

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

fRC /fs

f SC/f s

1/π


Switched-Capacitor Filter Built with LDI Integrators

( )ωjH

Zeros Preserved

Frequency (Hz)sf / 2 sf 2fs f


Switched-Capacitor IntegratorParasitic Sensitivity

Effect of parasitic capacitors:

1- Cp1 - driven by opamp o.k.

2- Cp2 - at opamp virtual gnd o.k.

3- Cp3 – Charges to Vin & discharges into CI

à Problem parasitic sensitivity

-

+

VinVo

φ1 φ2

CI

CsCp3

Cp2

Cp1


Parasitic InsensitiveBottom-Plate Switched-Capacitor

IntegratorSensitive parasitic cap. à Cp1à rearrange circuit so that Cp1 does not charge/discharge

φ1=1à Cp1 grounded

φ2=1 à Cp1 at virtual ground

Solution: Bottom plate capacitor integrator

Vi+

Cs-

+ Vo

CI

Cp1

Cp2

φ1 φ2

Vi-


Bottom Plate Switched-Capacitor Integrator

12

12

1

1 1

1 1

z z1 z 1 z

z 11 z 1 z

−−

− −

−

− −

− −

− −− −

Input/Output z-transformNote: Delay from Vi+ and Vi- to

output is differentà Special attention needed to

input/output connections

Vi+

Cs-

+ Vo

CIφ1 φ2

Vi-

Vi+on φ1

Vi-on φ2

Vo1on φ1

Vo2on φ2

φ1

φ2

Vo2

Vo1


Bottom Plate Switched-Capacitor Integrator

z-Transform Model1

2

12

1

1 1

1 1

z z1 z 1 z

z 11 z 1 z

−−

− −

−

− −

− −

−− −

12

1z

1 z

−

−−

12z

−

Input/Output z-transform

Vi+

Cs-

+ Vo

CIφ1 φ2

Vi-

φ1

φ2

Vo2

Vo1

Vi+

Vi- 12z

+ Vo2

Vo1

LDI

s IC C

s IC C−


LDI Switched-Capacitor Ladder Filter

CsCI

12

1z

1 z

−

−−

-+

+ - + -3

1sτ 4

1sτ 5

1sτ

12z

−

12z

+

12z

+12z

+

12z

−

CsCI

−

CsCI

−CsCI

−CsCI

CsCI

Delay around integ. Loop is (Z-1/2 . Z+1/2 =1)è LDI function

12

1z

1 z

−

−−

12

1z

1 z

−

−−12z

−


Switched-Capacitor LDI Resonator

2s

ω

1s

ω−

C1 1f1 sR C Ceq1 2 2C1 3f2 sR C Ceq3 4 4

ω

ω

= = ×

= = ×

Resonator Signal Flowgraph

φ1 φ2

φ1 φ2


Fully Differential Switched-Capacitor Resonator

φ1 φ2

φ1 φ2


Switched-Capacitor LDI Bandpass FilterUtilizing Continuous-Time Termination

0s

ω

0s

ω−

C C3 1f0 s sC C4 2C2Q CQ

ω = × = ×

=

Bandpass FilterSignal Flowgraph

CQ

Vi

Vo-1/QVo2Vi

Vo2


s-Plane versus z-PlaneExample: 2nd Order LDI Bandpass Filter

σ

jωs-plane z-plane


Switched-Capacitor LDI Bandpass FilterContinuous-Time Termination

-20

-15

-10

-5

0

0.1 1 10f0

0

-3dB

∆f

Frequency

Mag

nitu

de (d

B)

C1 1f f0 s2 C2f0f Q

C C1 Q1 fs2 C C2 4

π

π

= ×

∆ =

= ×

Both accurately determined by cap ratios & clock frequency


Fifth Order All-Pole LDI Low-Pass Ladder FilterComplex Conjugate Terminations

•Complex conjugate terminations (alternate phase switching)

Termination Resistor

Termination Resistor

Ref: Tat C. Choi, "High-Frequency CMOS Switched-Capacitor Filters," U. C. Berkeley, Department of Electrical Engineering, Ph.D. Thesis, May 1983 (ERL Memorandum No. UCB/ERL M83/31).


Fifth-Order All-Pole Low-Pass Ladder FilterTermination Implementation



Sixth-Order Elliptic LDI Bandpass Filter

TransmissionZero



Use of T-Network

High Q filter à large cap. ratio for Q & transmission zero implementationTo reduce large ratios required à T-networks utilized



Sixth Order Elliptic Bandpass FilterUtilizing T-Network

•T-networks utilized for:• Q implemention• Transmission zero implementation

Q implementation

Zero



Switched-Capacitor Resonator

Regular samplingEach opamp busy settling only during one of the clock phasesà Idle during the other clock phase


Switched-Capacitor Resonator Using Double-Sampling

Double-sampling:

•2nd set of switches & sampling caps added to all integrators

•While one set of switches/caps sampling the other set transfers charge into the intg. cap

•Opamps busy during both clock phases

•Effective sampling freq. twice clock freq. while opamp bandwidth requirement remains the same


Double-Sampling Issues

fclockfs= 2fclock

Issues to be aware of:- Jitter in the clock - Unequal clock phases -Mismatch in sampling caps.

à parasitic passbands Ref: Tat C. Choi, "High-Frequency CMOS Switched-Capacitor Filters," U. C. Berkeley, Department of

Electrical Engineering, Ph.D. Thesis, May 1983 (ERL Memorandum No. UCB/ERL M83/31).


Double-Sampled Fully Differential S.C. 6th Order All-Pole Bandpass Filter



Sixth Order Bandpass Filter Signal Flowgraph

γ

1

Q− 0

s

ω

inV 1−

0s

ω−

1

Q−0

s

ω0s

ω−

0s

ω−0

s

ω

outV1γ−

γγ−


Double-Sampled Fully Differential 6th Order S.C. All-Pole Bandpass Filter

Ref: B.S. Song, P.R. Gray "Switched-Capacitor High-Q Bandpass Filters for IF Applications," IEEE Journal of Solid State Circuits, Vol. 21, No. 6, pp. 924-933, Dec. 1986.

-Cont. time termination (Q) implementation-Folded-Cascode opamp with fu = 100MHz used-Center freq. 3.1MHz, filter Q=55-Clock freq. 12.83MHz à effective oversampling ratio 8.27-Measured dynamic range 46dB (IM3=1%)


Effect of Opamp Nonidealities on Switched Capacitor Filter Behaviour

• Opamp finite gain• Opamp finite bandwidth• Finite slew rate of the opamp


Effect of Opamp Non-IdealitiesFinite DC Gain


Vi+

Cs-

+ Vo

CIφ1 φ2

Vi-

DC Gain = asI s 1

I

1

Cs C C

s C a

o

o a

o

1H( s ) f

s f

H( s )s

aQ

Q a

ω

ω

ω

ω

≈ −+ ×

−≈

+ ×

×≈

⇒ ≈ àFinite DC gain same effect in S.C. filtersas for C.T. filters


Effect of Opamp Non-IdealitiesFinite Opamp Bandwidth


Vi+

Cs-

+ Vo

CIφ1 φ2

Vi-

Unity-gain-freq.

= ft

Vo

φ2

T=1/fs

settlingerror

time

Ref: K.Martin, A. Sedra, “Effect of the OPamp Finite Gain & Bandwidth on the Performance of Switched-Capacitor Filters," IEEE Trans. Circuits Syst., vol. CAS-28, no. 8, pp. 822-829, Aug 1981.

Assumption-Opamp à does not slew (will be revisited)Opamp has only one pole à exponential settling


Effect of Opamp Non-IdealitiesFinite Opamp Bandwidth

actual idealIk k 1

I s

I t

I s s

t s

C1 e e ZH ( Z ) H ( Z )

C C

C fwhere k

C C ff Opamp unity gain frequency , f Clock frequency

π

− − − − + ×≈ +

= × ×+

→ − − →


Vi+

Cs-

+ Vo

CIφ1 φ2

Vi-

Unity-gain-freq.

= ft

Vo

φ2

T=1/fs

settlingerror

time



Effect of Opamp Finite Bandwidth on Filter Magnitude Response

Magnitude deviation due to finite opamp unity-gain-frequency

Example: 2nd

order bandpass with Q=25

fc /ft

|Τ|non-ideal /|Τ|ideal (dB)

fc /fs=1/32fc /fs=1/12

Active RC



Effect of Opamp Finite Bandwidth on Filter Magnitude Response

Example:For 1dB magnitude response deviation:1- fc/fs=1/12

fc/ft~0.04à ft>25fc

2- fc/fs=1/32fc/ft~0.022à ft>45fc

3- Cont.-Timefc/ft~1/700à ft >700fc fc /ft

|Τ|non-ideal /|Τ|ideal (dB)

fc /fs=1/32fc /fs=1/12

Active RC

Ref: K.Martin, A. Sedra, “Effect of the Opamp Finite Gain & Bandwidth on the Performance of Switched-Capacitor Filters," IEEE Trans. Circuits Syst., vol. CAS-28, no. 8, pp. 822-829, Aug 1981.


Effect of Opamp Finite Bandwidth Maximum Achievable Q

fc /ft

Max. allowable biquad Q for peak gain change <10%

C.T. filters


Oversampling Ratio


Effect of Opamp Finite Bandwidth Maximum Achievable Q

fc /ft


C.T. filters

Example:For Q of 40 required Max. allowable biquad Q for peak gain change <10%

1- fc/fs=1/32fc/ft~0.02à ft>50fc

2- fc/fs=1/12fc/ft~0.035à ft>28fc

3- fc/fs=1/6fc/ft~0.05à ft >20fc


Effect of Opamp Finite Bandwidth on Filter Critical Frequency

Critical frequency deviation due to finite opamp unity-gain-frequency

Example: 2nd

order filterfc /ft

∆ωc /ωc

fc /fs=1/32

fc /fs=1/12

Active RC



Effect of Opamp Finite Bandwidth on Filter Critical Frequency

fc /ft

∆ωc /ωc

fc /fs=1/32

fc /fs=1/12

Active RC

Example:For maximum critical frequency shift of <1%

1- fc/fs=1/32fc/ft~0.028à ft>36fc

2- fc/fs=1/12fc/ft~0.046à ft>22fc

3- Active RCfc/ft~0.008à ft >125fc


C.T. filters


Sources of Distortion in Switched-Capacitor Filters

• Distortion induced by finite slew rate of the opamp

• Opamp output/input transfer function non-linearity

• Capacitor non-linearity• Distortion incurred by finite setting time of the

opamp• Distortion due to switch clock feed-through

and charge injection


What is Slewing?

oV

Vi+Vi-

φ2

Cs

-

+

Vin

Vo

φ2

CI

CsCI

CL

Assume opamp is of a simple differential pairclass A transconductance type

Iss


What is Slewing?

oV

Vi+Vi-

φ2

Cs

CI

CL

Io

VinVmax

Imax =Iss

Slope ~ gm

Vcs> Vmax à Output current constant Io=Iss à Slewing

After Vcs is discharged enough to have Vcs <Vmaxà Linear settling

Iss

Io


Distortion Induced by Opamp Finite Slew Rate


Ideal Switched-Capacitor Output Waveform

φ1

φ2

Vin

Vo

Vcs

Clock-

+

Vin

Vo

φ1

CI

Cs

-

+

Vin

Vo

φ2

CI

Cs

φ2 High àCharge transferred from Cs to CI


Slew Limited Switched-CapacitorOutput Settling

φ1

φ2

Vo-real

Vo-ideal

Clock

Slewing LinearSettling



Distortion Induced by Finite Slew Rate of the Opamp

Ref: K.L. Lee, “Low Distortion Switched-Capacitor Filters," U. C. Berkeley, Department of Electrical Engineering, Ph.D. Thesis, Feb. 1986 (ERL Memorandum No. UCB/ERL M86/12).


Distortion Induced by Opamp Finite Slew Rate

• Error due to exponential settling changes linearly with signal amplitude

• Error due to slew-limited settling changes non-linearly with signal amplitude (doubling signal amplitude X4 error)

àFor high-linearity need to have either high slew rate or non-slewing opamp

( )( )

( )

o s

o s

2T2ok 2r s

2T2o3

r s

8 sinVHD S T k k 4

8 sinVHD S T 15

ω

ω

π

π

=−

→ =

Ref: K.L. Lee, “Low Distortion Switched-Capacitor Filters," U. C. Berkeley, Department of Electrical Engineering, Ph.D. Thesis, Feb. 1986 (ERL Memorandum No. UCB/ERL M86/12).


Distortion Induced by Opamp Finite Slew Rate Example

-120

-100

-80

-60

-40

-20

1 10 100 1000

HD

3 [d

B]

(Slew-rate / fs ) [V]

f / fs =1/32

f / fs =1/12

Vo =1V V

o =2V

Vo =1V V

o =2V


Distortion Induced by Finite Slew Rate of the Opamp

• Note that for a high order switched capacitor filter à only the last stage slewing will affect the output linearity (as longas the previous stages settle to the required accuracy)à Can reduce slew limited linearity by using an amplifier with a

higher slew rate only for the last stageà Can reduce slew limited linearity by using class A/B amplifiers

• Even though the output/input characteristics is non-linear the significantly higher slew rate compared to class A amplifiers helps improve slew rate induced distortion

• In cases where the output is sampled by another sampled data circuit (e.g. an ADC or a S/H) à no issue with the slewing of the output as long as the output settles to the required accuracy & is sampled at the right time


More Realistic Switched-Capacitor Circuit Slew Scenario

-

+

Vin

Vo

φ2

CI

Cs

At the instant Cs connects to input of opamp (t=0+)àOpamp not yet active at t=0+ due to finite opamp delayàFeedforward path from input to output generates a voltage spike at the outputàEventually, opamp becomes active & starts slewing

CL

Vo

φ2

CI

CsCL

t=0+


More Realistic SC Slew Scenario

Vo-realIncluding t=0+spike


Slewing

Spike generated at t=0+

Vo-real

Vo-ideal



Ref: R. Castello, “Low Voltage, Low Power Switched-Capacitor Signal Processing Techniques," U. C. Berkeley, Department of Electrical Engineering, Ph.D. Thesis, Aug. ‘84 (ERL Memorandum No. UCB/ERL M84/67).

Documents

EE247 Lecture 10 - EECS Instructional Support Group …ee247/fa05/lectures/L10_f05.pdf · EE247 Lecture 10 • Switched ... z-Transform Model 1 2 1 2 1 11 11 zz ... LDI Switched-Capacitor