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2EE 215B
Course Information
• Instructor– Office: 56-147A, EIV, 6-3665– Office hours: see website– E-mail: [email protected]
• Admin: Kyle Jung– Office: 56-127CC, EIV (5th floor cubicle)
• Course website:– Grades: http://eeweb.ee.ucla.edu– Lecture/HW/Project material:
http://icslwebs.ee.ucla.edu/yang/classwiki/index.php/EE215B• Username: ee215b 01, Password ckt2016
– Forum and discussion: https://www.piazza.com– You must have an EE account to use CAD tools.
3EE 215B
Logistics
• Textbooks for reference: – J.M. Rabaey, Digital Integrated Circuits, 3rd Edition. Prentice
Hall– N. Weste, D. Harris, CMOS VLSI Design, Addison Wesley – Notes: collated from a lot of people including Mark Horowitz,
Jan Rabaey, Shekhar Borkar, Vivek De, Norman Rohrer, Jo Ebergen, Tadahiro Kuroda, Dejan Markovic, Bora Nikolic, and Ingrid Verbauwhede
– A. Chandrakasan, et.al., Design of High Performance Microprocessor Circuits, IEEE Press 2001
– Journal Papers• CAD Tools
– Cadence (Virtuoso and Spectre)– We will use the same set of tools but slightly different library
4EE 215B
Assignments
There will be around 4 problem sets, and a project.• Homework will be to get experience with the design techniques
and simulation. There will occasionally be one, more open-ended design problem on a problem set.– There are no late homework accepted
• There is a library provided for the class– You must use the provided CMOS technology.
• If you convert the models to be used with another schematic editor or simulation tool, there will be no support.
• If you are an on-line student and want to use your own models, you may but there also will be no support.
• The project will be an open-ended topic.– 3-4 weeks
5EE 215B
Academic Honesty
• Do NOT cheat.– My obligation is that I will trust you and will not tempt you.– If you are found cheating it is very serious.
• I encourage discussion for homeworks.– You are required to do your own.
• The projects are in groups of 2.
• Exams are taken individually.
7EE 215B
Overview
• Reading– Rabaey 4.2.1
• Overview– This class will look at the design of ‘digital’ circuits in more
detail. Let’s review the issues facing digital design covered in EE216A.
8
Transistor Scaling
EE 215B Source: Intel
9EE 215B
10
Motivation for Scaling
• Increase the logic density for greater functionality• A major side benefit was:
– Improved speed performance.– Electrons had a shorter distance to travel and less C.
EE 215B
Nikolic 2008
11
International Technology Roadmap for Semiconductors (ITRS)
Node years: 2007/65nm, 2010/45nm, 2013/32nm, 2016/22nm
Year 2001 2003 2005 2007 2010 2013 2016
DRAM ½ pitch [nm] 130 100 80 65 45 32 22
MPU transistors/chip 97M 153M 243M 386M 773M 1.55G 3.09G
Wiring levels 8 8 10 10 10 11 11
High-perf. phys. gate [nm] 65 45 32 25 18 13 9
High-perf. VDD [V] 1.2 1.0 0.9 0.7 0.6 0.5 0.4
Local clock [GHz] 1.7 3.1 5.2 6.7 11.5 19.3 28.8
High-perf. power [W] 130 150 170 190 218 251 288
Low-power phys. gate [nm] 90 65 45 32 22 16 11
Low-power VDD [V] 1.2 1.1 1.0 0.9 0.8 0.7 0.6
Low-power power [W] 2.4 2.8 3.2 3.5 3.0 3.0 3.0
Technology Roadmap (2002)
12
The Big Problems
• Power– Dynamic and static– Active and passive
• Device performance– Worse charge transit, high electric fields– Higher parasitic capacitances
• S/D area• Interconnect
• Noise – poor control– Process variations and lithographical variations– Supply and temperature variations– Coupling
EE 215B
13
Problem: Active Power in Processors
Nikolic 2008
EE 215B
ApplicationDrivenPower
Envelop
14
RST
CounterLatch
Digital Loop Filter
L
CDD
VDDPENAB
NENABFERR
FMEAS
f1MHz
0110
100 FDES
+Register
fCLK
Ring Oscillator Processor
IDD
• Feedback loop sets VDD so that FERR 0.
• Ring oscillator delay-matched to CPU critical paths.
• Custom loop implementation Can optimize CDD.
7
Buck converter
Set by
O.S.
Burd ISSCC’00
Solution 1: Dynamic Voltage-Frequency Scaling (VDD, fCLK)
15
Dynamic operation can increase energy efficiency > 10x.
100
80
60
40
20
00 1 2 3 4 5 6
Dhrys
tone 2
.1 MI
PS
Energy (mW/MIPS)
85 MIPS @
5.6 mW/MIPS
(3.8V)
6 MIPS @
0.54 mW/MIPS
(1.2V)
x
Static VDD
Dynamic VDD
Burd ISSCC’00
Measured System Performance and Energy
Most system level techniques use SCMOS as the circuit style
16EE 215B
Solution 2: Sizing/Supply Power Optimization
• Sizing has major impact for small delay increments
• Supply reduction has more impact for large delay increment.– Using multiple-supplies is
marginally better.• Combined gives the best of both
worlds.– 5% delay improvement can lead to
30+% power reduction
17EE 215B
Problem: Leakage Power in Processors
0.1
1
10
100
1000
0.25u 0.18u 0.13u 90nm 65nm 45nm
Technology
SD L
eaka
ge (W
atts
)
2X Tr Growth1.5X Tr Growth
Subthreshold leakage
Courtesy of V. De
1.E-031.E-021.E-011.E+001.E+011.E+021.E+031.E+041.E+051.E+06
0.25u 0.18u 0.13u 90nm 65nm 45nm
Technology
Gat
e Le
akag
e (W
atts
)
30M Tr15mm Die
During Burn-in1.4X Vdd
Gate oxide leakage
18
ON: gateoverdrive
...
VCCVirtual VCC
VSS
Virtual VSS
ON: gateoverdrive
Noise on virtual supply
PMOS forward body bias
Dual-VTcore
Courtesy of J. Tschanz, Intel (ISSCC’03)
Solution 1: Power-Down Dynamically
19
Solution 2: Circuit-Level Approaches
• Transistor-level optimization– Multi-Vth designs
– Increasing length
• Stacking of devices
EE 215B
0
0.2
0.4
0.6
0.8
1
1.2
0 0.5 1 1.5Vint (V)
Nor
mal
ized
cur
rent
VX
Istack-lwl
Istack-uwu
Vint (V)
0
0.2
0.4
0.6
0.81
1.2
0 0.5 1 1.5Vint (V)
Nor
mal
ized
cur
rent
V
Istack-lwl
Istack-uwu
Vint (V)
0
0.2
0.4
0.6
0.8
1
1.2
0 0.5 1 1.5Vint (V)
Nor
mal
ized
cur
rent
0
0.2
0.4
0.6
0.8
1
1.2
0 0.5 1 1.5Vint (V)
Nor
mal
ized
cur
rent
VX
Istack-lwl
Istack-uwu
Vint (V)
0
0.2
0.4
0.6
0.81
1.2
0 0.5 1 1.5Vint (V)
Nor
mal
ized
cur
rent
V
Istack-lwl
Istack-uwu
Vint (V)
VddIdevice
w
VddIdevice
w
VddIstack-u
Vint
wu
wl Istack-l
VddIstack-u
Vint
wu
wl Istack-l
20EE 215B
Problem: Device Performance Limitations
• I-V Curve of a sub-micron device– 0.35um
technology!• Actual current deviates
substantially from square law “predictions”
Model Comparison
0 0.5 1 1.5 2 2.5 3 3.5 40
0.005
0.01
0.015
0.02
0.025
Vg=1 modelVg=1 spiceVg=2 modelVg=2 spiceVg=3.3 modelVg=3.3 spice
21
Solutions: New Structures/Materials/Devices
• Channel engineering– Material – Profile
• New devices
22nm45nm
65nm
32nm16nm
12nm
Bulk/SOI CMOS Multi-gate CMOS Post-Silicon
5 n m5 n m
5 nm
K. Cao (ASU)
22EE 215B
Problem: Interconnect Density
• Densely packed– >10 metal layers
• Conductors that are closer together causes problems.– More capacitance– More coupling
• Need to treat interconnect as a device.• Approaches
– Lower dielectric– Better circuits.
23
Problem: Process Variations
• Dopant variation• Etching roughness• Exposure and resolution limitation
EE 215B
24
Vt measurements on ~3500 identical SOI nFETs at each (W,L) dimension, all in a single experimental macro.
Vt sigma ~ 26mV
This includes:Dopant FluctuationLine Edge RoughnessDelta WidthOxide Thickness Variation
Simulated I-V shows order of magnitude changes in leakage at 0V.
175 200 225 250 275 300 325 350 3750
50
100
150
200
250
300
350# of devices = 3481
Vt= 25.58 mV
Count
Threshold Voltage (mV)
[Courtesy of D. Frank and B. Linder]
Example: Vth and Current Variability
VDS=0.7 VLeff=11 nm
25
Solution 1: Reduce Systematic Errors
• Optical proximity correction– Pre-distort the mask
• IBM Restrictive Design Rules (RDR)
Elaboration Step
M Lavin et al, “Backend CAD flows for restrictive design rules”, ICCAD, 10 Nov 2004
Courtesy: L. Pileggi
27
Understanding Digital Design Tradeoff
• For a given functionality• Speed –
– GOps/s, GHz, latency• Power
– Energy, power, energy-delay (Gops/s-W)• Area• Robustness
– Sensitivity to noise.– Failure rate
• The design process is balanced with design time.– The bottom line is $$.
EE 215B
28
Energy-Delay Design Space
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Nikolic 2008
29
Do Circuits Matter? (1)
• Optimizing a circuit alone makes small ED difference.– Typically <20%.
• A broader optimization can often lead to stronger ED tradeoffs. – Example of sizing with supply can
lead to 40% improvements.– Combining circuit changes with
architecture improvements can be more effective than circuits alone.
EE 215B
30
D. Markovic / Slide 30D. Markovic / Slide 30
Do Circuits Matter? (2)
• Some circuit styles enable a higher performance ceiling.– Good for specific application
spaces.• Processors
− Maximize performance− Highest VDD required
• Communications− Minimize energy & area− Typically, sensitivity ~ 1
• Neuroscience− Power density: 0.8mWmm2
− Aggressive VDD scaling
VDD scaling
0
Communications
Ene
rgy
Delay
Neural
Processors
31
This course revolves around circuits for
Models&
Memories
EE 215B
32EE 215B
33EE 215B
Why Models?
• Where does a designer spends her time?– The innovation is only part of the job.
• After coming up with an idea,– Functionality
• Making sure that the new network of transistors works!– Debugging
• The circuit only partially works… Why doesn’t it work?• Is there an inherent problem?• Can it be fixed?
• Need ways to reason about circuits…
34EE 215B
Models are Abstractions
• Need to use some kind of model to simulate anything
– 3-D device simulator• Needs a model for the properties of an electron/hole in a crystal• Maxwell’s equations (to model the fields in the crystal)
– Simulating complex designs• Means you need to use higher-level models• Model transistors, not carriers• Assume wires are equipotentials (quasistatic models)
• For you or a computer to reason about a system, one needs a model of it.
35EE 215B
The Complexity Problem
• ICs are very complicated, contain many millions of tiny 3D structures– Interleaving of conductors and insulators– Diffusions of impurities in a semiconductor
forming transistors
• Could talk about the system in terms of 3D electric fields, and carriers– But takes a long time for a computer to
simulate a single transistor
36
Goals for EE215B
• Understand how devices and circuits are modeled.– Devices are physically complex.– Not all the complexities are needed for digital design.
• Use models to help reason about circuits.– Different models can be used for different goals.– Understand why certain circuit topologies improve
performance.• Understand when models fail.
– Give some metrics for the impact of the error.• Use memories as the application for discussion.
– Explore different memory structures as well as logic styles.• Hopefully by using some existing models, you will be able to
create models for future devices and systems.
EE 215B
37EE 215B
Models
• Are an approximation of the real world– Must leave many details out– Must (to be useful) retain the important details– Appropriate level depends on questions you want to answer
• CAUTION:– Simulation and analysis do not tell you what the circuit does– They tell you what your MODEL of the circuit does– So remember:
• Garbage in, garbage out
• Some of the hardest work is figuring out the right model for a problem
38EE 215B
Modeling / Simulation Problem
• There are really two problems:– Need to generate the correct model of the circuit– Need to stimulate that circuit in ways that exercise the
problem• Add coupling noise at the critical time• Set initial conditions for the worst-case charge-sharing• Inject substrate noise
• SPICE (any simulation tool) limitation:– Only evaluates the model of the circuit that you give– Does the evaluation for the conditions you specify
• Answers the questions that you ask, • But does not tell you whether it was the right question
39EE 215B
What Model - The SPICE Approximation
• Use lumped element model:– Quasi-static
• Size is small compared to wavelength/4– Approximate devices by terminal characteristics– Connections (nodes) in the model are equipotentials
• Major equation:
– (also called charge control)
– So, devices on an IC are modeled by their terminal iV and CV behavior
• Figuring out the right model can be difficult.
– More recently, we start needing inductor equation as well.
iQ
iVC t
tV C i
40EE 215B
What Needs to be Modeled?
• Transistors– nMOS, pMOS
• Wires– They are not ideal connectors– How complex?
• Resistance effects, iR drops in lines?• Coupling, Inductance?
• Circuit Environment– Temperature, Power Supply, Substrate Voltage, Chip Gnd vs. Board
Gnd• Modeling of the package and power and ground distribution nets• Modeling of heat generation and flow
• Appropriate model depends on question being asked.– Often need to extract several models for a single design of a system.– Feedback the simulation results to modify the design
41EE 215B
Possible Modeling Approaches
• Empirical (collect lots of data, and fit model, most common)– Advantage
• Answer will fit simulation data• Simple models often work well
– Disadvantage• Don’t know the range of the model• Validity for regions not explicitly simulated is always a concern
• Analytical (use some physics, then fit data)– Advantage
• Model foundation understood, range known• Reason with model
– Disadvantage• Fit with data is worse• Can become complex
42EE 215B
Our Approach for Circuits and Devices
Analytical model• Will show you a set of analytical models for devices
– Range from simple to complex• For each model – show basis for the model
– The approximations that it makes– The kind of effects that it models– And what it leaves out
• Give you some idea of how to create your own modelEmpirical Model• Simulation setups for proper modeling of the circuits of a sub-
system.
43EE 215B
Example (Review): Linear RC Transistor Models
• Model transistor by linear resistor and linear diffusion and gate caps– Gate cap is proportional to W*L, diff cap proportional to W*Hdiff– Resistance is proportional to L/W, and inversely proportional to VGATE
Rtrans
Cdiff Cdiff
Cgate
drain
sourcegateRtrans
Cdiff Cdiff
Cgate
drain
sourcegate
V g V s V th V g V s V th
R trans R trans
V g V s V th V g V s V th
R transR sq L
W V g V s V th R transR sq L
W V g V s V th
44EE 215B
0.5 0.9 1.3 1.7 2.1 2.5
6 104
1.2 105
1.8 105
2.4 105
3 105 Resistance of Model
Simple Resistance Model
• This model is not correct; MOS transistors are not linear resistors– Gives bad results for finding most DC levels
• However, it is good for estimating timing– Therefore can be used to size transistors in gates
• Will review it and discuss why it works later
VGS
45EE 215B
Modeling Delay
• Delay is measured from input at VDD/2– To output at VDD/2– Assume VDD/2 is where the gate switches
• More on this later• Model delay by finding the delay of the RC model
Delay of this Gate
a b
a b
46EE 215B
Aside: Review of Static CMOS Logic
• Logic Gates – an abstraction for a block that perform logical functions.– Unidirectional– Regenerates logic levels
• Map into transistor in many ways. – The most common is Static CMOS.
• One of many logic families– Uses both NMOS and PMOS transistors
• Transistors are treated as switches.• Transistor Functional Characteristics
– NMOS – switch that connects when input is high.• Passes LOW values well.
– PMOS – switch that connects with input is low.• Passes HIGH values well.
S D
CGG
NAND Function
47EE 215B
Aside: Building Logic with Switches
• Logic can be represented as ANDs and ORs.• Switches can be combined to perform AND/OR
functions.– Parallel switches are OR– Series switches are AND
• Example:
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A
B
A + BOR
X Y
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A B
A * BAND
X Y
B
C
(A + B) C
A
B C
A D
(AD) + (BC)
48EE 215B
Aside: Building a Static CMOS Gate
• Rules:– Switches are either PMOS or NMOS,
switched by the inputs.– PMOS network connects to VDD and
output.– NMOS network connects to GND and
output.– Network must connect to either VDD or
GND (but not both) for all possible combination of inputs.• Otherwise output will either float or fight
Pull-up network
Pull-down network
49EE 215B
Aside: Example: NAND Gate
• NAND– Output is low when A and B are both high
• NMOS network– Output is high when either A or B is low
• PMOS network
A
B
NAND
Output
50EE 215B
Aside: Generalized CMOS Gates
• To build a logic gate g(x1, …, xn) = f’(x1, …, xn) , need to build two switch networks:
• Pull-down– (x1, …, xn) = f(x1, …, xn)
• Pull-up– (x1, …, xn) = f’(x1’, …, xn’) (since pMOS invert inputs)– Demorgan’s theorem says that f(x1, …, xn, *,+) = f’(x1’, …, xn’,+,*)– So is just the dual of .
nMOS only, since only passes 0
pMOS only, since only passes 1
Pull-up networkConnects the output to VDD when f is FALSE
Pull-down networkConnects the output to VGND when f is TRUE
51EE 215B
Aside: Example
• 3 input function, g = a(b+c) + bc– For pull-down, f = (a’+b’c’)(b’+c’)– For pull-up, f’ = a’’(b’’+c’’)+b’’c’’
c’ b’
c’
a’
b’
c’
b’ c’ b’
a’
52EE 215B
Aside: Properties of Static CMOS Gates
• Function is independent of sizing.• No DC current path.
– Charging and discharging capacitors only.• Output logic level is regenerated.
– Full swing.• Many possible implementation of the same function.
– Re-arranging the stack.– Sizing.
• The depth of the stacking is approximately the number of inputs.– Stack depth impacts delay and power.– Resistors in series make the delay slower.
53EE 215B
Result of RC Model
• End with a linear RC network that we need to estimate delay– In this model, only include capacitors that change values– We can calculate the delay from the R’s and C’s (more later)
• Dotted elements might (or might not) need to be included– Depends on whether M3 is on before transition.– Input dependence!
M3
M4
M1 or M2
M3
M2 M1
M3
M4
54EE 215B
Component Values
• Key issue is to estimate the component values correctly– D(M1) = diffusion cap of M1– G(M1) = gate capacitance of M1– Cload = External load capacitance
D(M1,M2,M3)Cload
M3
M4
D(M3,M4)G(M3)
M2 M1
M3
M4
55EE 215B
Power Model
• If logic (such as SCMOS) is just charging and discharging capacitance,– R dissipates the energy.– But the value of R does not matter in the energy
dissipation.• Q=C(VP-VN)• Energy = Q(VP-VN)
– Power = CV2/(2*Period)• =probability of switching in 1 Period.• Period is often the cycle time of the system.
• Easy equation but not easy to make accurate.– What is , V, and C?
Vp
Vn
56EE 215B
V, C, and
• What is V2?– Depends on the swing of the signal and
the supply voltage from which the charge is drawn/sunk.
– What happens to VA?• It does not swing from VDD to Gnd
because M3 turns off.• Input dependence.
• C (diffusion may not be charged)– Input dependence
• depends on the activity of the gate.– Test sequence dependence.
• Exact for a single test trace.– What is realistic?
M2 M1
M3
M4VA
57EE 215B
Area Model
• Different models at different design stages.– Floorplanning
• # gates * average area per gate + routing channel (2x cell size).– Logic Gates
• Standard cells: total transistor gate area * 25• Datapath cells: fixed height (100), width depends on number
of PMOS/NMOS transistors.– is defined as roughly ½ gate length or 1/8 contacted wire spacing.
– Memories• SRAM: approx 24x24
• Layout – for most accurate result.– Stick diagram – 8 approximation.– Layout Editor with DRC.
• Not part of this class.
58EE 215B
Summary: What Makes the Model Inaccurate
• Component values.• Equations of the Model
– Non-linear resistors and capacitors– Exclusion of small factors (that adds up)
• Signal dependence– Shape of the voltage waveforms.
• Input/output dependence– The result differs for different inputs and outputs.
• Different logic families and/or systems may have different requirements for accuracy.– This class will focus on Delay and Power
