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Electronic Circuits I Laboratory

7 JFET Characterist ics

7.1 Objectives

Understanding the basic characteristics of JFETs.

7.2 Basic Description

7.2.a Terminology

JFET : The abbreviation of Junction Field Effect Transistor.

G,D,S : Gate, Drain, Source.

Vp, Ggs(Cut-off) : Pinch-off voltage or cutoff voltage for G-S.

IDSS : The saturation current for D-S.

7.2.b Basic Principle

Transistor is a kind of current-control device, and its generating current includeselectron flow and hole flow. The transistor is therefore referred to as bipolar junctiontransistor.

FET is a unipolar device, in which the current of n-channel FET is formed byelectron flow and the current of p-channel is formed by hole flow. FET is a kind ofvoltage-control device. FET can also perform the functions that general transistors(BJT) do, with the only exception that the bias conditions and characteristics aredifferent. Their applications shall thus be chosen in accordance with relatedadvantages and drawbacks. I

The characteristics of FET are listed as follows:

FET has very high input impedance, typically around 100 M.

When FET is used as switch, there is no offset voltage.

FET is relatively independent of radiation, whereas BJT is very sensitive toradiation (value will be varied).

Intrinsic noise of FET is lower than BJT, which makes FET suitable for the inputstage of low-Ievel amplifier

During operation the thermal stability of FET is higher than that of BJT.

However, FET also has some drawbacks: comparing with BJT, its product ofgain and bandwidth is smaller and it is easier to be damaged by static electricity.

7.2.b.1 Structure and characterist ics of JFET

The internal structure of JFET is shown in Fig 7.1. The n-channel JFET isformed by difussing one pair of p-type region into a slab of n-type material. On thecontrary, the p-channel JFET is formed by difussing one pair of n-type region into a

slab of p-type material. In order to discuss the operation method of JFET, we herebydescribe the bias arrangement applied to n-channel JFET as shown in Fig 7.2. The

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voltage from power supply Vdd provides the voltage Vds across drain and source soas to generate a current Id from drain to source (in n-channel the electrons actuallyflow from source to drain, wherein the latter terminal is thus called drain and thedirection of conventional current is inverse to the electron flow). Under this situationthe drain current is formed by flowing through the channel surrounding the p-type

gates. The voltage across gate and source are provided by voltage source Vgg , asshown in Fig 7.2. Because the voltage across gate and source is a reverse bias to thejunction of gate-source, no gate current will be generated. The depletion regiongenerated by this gate voltage at sides of channel will narrow the width of this channel,which will increase the resistance between drain and source and further decrease thedrain current.

a-) n-channel b-) p-channel

Fig. 7.1 Internal Structure of JFET.

Fig. 7.2 Basic Operation Method of JFET.

When Vgs = OV, the operation status of FET is shown in Fig 7.3 (a). Thevoltage drop will be generated by Vdd when a current flows through the n-channelviewed as a small resistor, wherein the potential close to the drain-gate junction ishigher than of source-gate junction. The reverse bias applied to P-N junction will thusform the depletion region shown in Fig 7.3 (a). When the voltage source Vdd isincreased, the current Id will also be increased correspondingly, which will form theeven larger depletion region and will generate the larger resistance between drain andsource. If the voltage source Vdd is continuously increased, the depletion region will

eventually occupy the full channel, as shown in Fig 7.3 (b). At this time any furtherincrement of Vdd will not increase Id any more (I = V/R, V increases, R increases, I

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keeps constant). When Vgs = 0, the relation between Vds and Ids is shown in Fig 7.3(c). From this figure we can clearly view that Id will be increased with Vds until itmaintains at a constant value. This constant value is called Idss, wherein the footnoteds means the current from drain to source, and the last s means it is under thestatus that drain-gate are short-circuit (Vgs = 0).

a b

C

Fig. 7.3 The pinch-off effect caused by the channel

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7.2.b.2 Circuit Symbols

n-channel JFET p-channel JFET

7.2.b.3 Drain-Source Characterist ic Curve

Fig. 7.4 Drain-Source Characteristic Curve of JFET.

If Vgs is increased (it's more negative to n-channel), depletion will beimmediately generated in the channel so that the current required to pinch off thechannel will be decreased. The curve corresponding to Vgs = -1V is shown in Fig 7.4(a). From this result we can find out that the gate voltage functions as a controllercapable of decreasing the drain current (at a specific voltage Vds). If Vgs is morepositive for p-channel JFET, the drain current will be decreased from Idss (as shown inFig 7.4 (b)). If Vgs is continuously increased, the drain current will be decreasedcorrespondingly. When Vgs reaches a certain value, the drain current will bedecreased to zero and will be independent of the value of Vds. The gate-sourcevoltage at this time is called pinch-off voltage which is usually denoted as Vp or Vgs(cutoff). From Fig 7.4 we can find out that Vp is a negative voltage for n-channel FETand a positive voltage for p-channel FET.

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7.2.b.4 Transfer Characterist ic Curve

Fig. 7.5 Transfer and Drain-Source Characteristic Curve for JFET.

Another characteristic curve for JFET is transfer characteristic curve. This is avariation curve of drain current Id corresponding to gate-source voltage Vgs while thedrain-source voltage Vds is constant. Two points, Idss and Vp are the most importantpoints in this transfer characteristic curve. When these two points are fixed in thecoordinate axes, the remaining points can be looked up from this transfercharacteristic curve or can be solved from the formula

Id = Idss(1- Vgs/Vp)2.

From this formula,we can calculateVgs= 0, Id= Idss,

Id= 0, Vgs= Vp.

The design of JFET is typically designed in the middle between Vp and Idssofthe transfer curve.

7.3 Experiment Equipments

1. KL- 200 Linear Circuit Lab. Device

2. Experiment Module: KL-23004

3. Experiment Instruments: Oscilloscope, Analog and Digital Multimeter

4. Connection cables and short-circuit clips

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7.4 Procedures

Procedure 1: Measurement of IDSS

1 ) Locate the block marked block b on KL-23004.

2 ) Insert the short-circuit clips by referring to Fig 7.6.

D

SG

Fig. 7.6

3 ) For measurement of VDSuse digital voltmeter on KL-200 device and for

measurement of ID use Analog multimeter.

4 )Adjust VDS to values of in Table 7.1. Measure yielding ID for each step

and record them in Table 7.1.

Note that, since VGS= 0 V, IDequals to the characteristic IDSScurrent of the

JFET.

VDS 100(mV) 500(mV) 1V 2V 4V 6V 10V 15V

ID(IDSS)

Table 7.1

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Procedure 2: Derivation of Transfer Characteristic Curve ( ID vs VGS)

1 )Rearrange short-circuit clips by referring to Fig 7.7.

Fig. 7.7

2 ) Connect +12 and 12 V power supplies.

3 ) Use Multimeter to measure V.

4 ) Adjust 1M pot according to values of VGS(V2) in Table 7.2

5 ) For each step, measure VG (V1) and calculate yielding ID and record

them in Table 7.2.

VGS 0 - 0.25 -0.75 -1.00 -1.25 -1.50 -1.75 -2.00

ID

Table 7.2

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7.5 Laboratory Report Content

Plot the transfer curve using the results in Table 7.2(on milimetric paper)

Search the datasheet of JFET 2SK30, and find out

o IDSS.

o Vp at 250C ( inspect plotting for IDvs VDS, and curve for VGS=0 ).

o Max. Operating Temperature.

Compare the results of experiment and the datasheet (IDSS and Vp) whether

they are same or not.

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_EE 425_Exp_7