Edwin Vlsi Testing

8/13/2019 Edwin Vlsi Testing

1/23

VLSI TESTING


2/23

Discussion

Need for Testing

Manufacturing Test Principles

Design Strategies for Test

Chip Level Test Techniques

System Level Test Techniques


3/23

Why Testing?

Testing is one of the most expensive parts ofchips

Logic verification accounts for > 50% of

design effort for many chips

Debug time after fabrication has enormous

opportunity cost

Shipping defective parts can sink a company

By detecting a malfunctioning chip early, the

manufacturing cost can be kept low.


4/23

Why Testing?

Yield = Number of good die / Total number of die per

wafer. Because of the complexity of the manufacturing

process, not all die on a wafer function correctly.

Dust particles and small imperfectionsin startingmaterial or photo masking can result in a bridged

connections or missing features and theseimperfections are called faults.

Testing a chip can occur at

Wafer level

Packaged chip level

Board level

System level

Field level.


5/23

Testing at Various Levels


6/23

TestCategories

Functionality Tests

(Logical Verification)

Silicon Debug

Manufacturing Tests


7/23

Logical Verification

Does the chip simulate correctly? Usually done at HDL level

Verification engineers write test bench for HDL

Cant test all cases

Look for corner cases

Try to break logic design


8/23

Silicon Debug

Run on the first batch of the chips that return from the

fabrication.

If you are lucky, they work the first time, If not???

Much more extensive than the first one because the

chip can be tested at a full speed in a system.

Required to locate the cause of failuresbecause the

designer has less visibilityinto the fabricated chip

compared to during design verification.


9/23

Manufacturing Tests

Verify that every transistor, gate and storageelement in the chip functions correctly.

A speck of dust on a wafer is sufficient to kill

chip

Yield of any chip is < 100%

Must test chips after manufacturing before delivery

to customers to only ship good parts


10/23

Manufacturing Tests

Manufacturing testers

are very expensive Minimize time on tester

Careful selection of

test v ectors

Same tests can be used for all three steps

It is easier to use one set of tests to chase down thelogic bugs and another, separate set optimized for

manufacturing defects.


11/23

Types of Faults

FaultAny condition that causes a device to function

improperly. Solid or Permanent Fault

A faulty condition that does not change with time.

Intermittent Fault

A faulty condition that appears and disappears with time. Logical Faults

Faults that cause a given logical device to functionentirely different logic device.

Non Logical Faults

All faults other than logical faults


12/23

Stuck-at Fault Model

A popular and useful model

for representing faults inthe logic device.

Types of model

Stuck-at logic zero (s-a-0)

Stuck-at logic one (s-a-1)

These faults are due to

Gate oxide shorts

Metal-to-metal shorts


13/23

Short-Circuit Faults

Other Names: Stuck-closedfaults or Bridging faults

The short S1 results in an S-A-0 fault at input A

The short S2 modifies thefunction of the gate.

To ensure the most accuratemodeling, faults should bemodeled at the transistorlevel because the completecircuit structure is knownonly at this level.


14/23

Identifying Stuck-closedFaults

By observing static current (IDD) whileapplying test vectors

A 2-input NOR gate

FaultThe drain connection on apMOS transistor is shorted to VDD.

This fault occurs due to the

overlapping of stray metal on the VDDline and drain connections.

Identifying the faults

Apply the test vectors 01 or 10 to the Aand B inputs

Measure the static IDD

Notice that it rises to some valuedetermined by size of the nMOStransistors.


15/23

Open Circuit Faults

Convert a combinational

logic circuit into asequential logic circuit.

A 2-input NOR gate.

One of the transistorsrendered is ineffective. If

the nMOS transistor A isstuck open, then thefunction displayed by thegate will be

where Z is the previousstate of the gate.

Z = A + B + B Z'


16/23

Delay Fault Testing

Timing is also included.

Still works withincreased tpdf.

Fault become sequentialas the detection of thefault depends on theprevious state of thegate.

Occurs due to crosstalk.

Occurs in SOI due to

history effect.


17/23

To increase Testability

Increase Observability

Add more pins (?!)

Add small probe bus, selectively enable different values

onto bus

Use a hash function to compress a sequence of values

(e.g., the values of a bus over many clock cycles) into a

small number of bits for later read read-out

Cheap read read-out of all state information

Increase Controllability

Use muxes to isolate sub sub-modules and select sources

of test data as inputs

Provide easy setup of internal state


18/23

Fault Coverage A measure of goodness of a set of test vectors.

What percentage of the chips internal nodes were

checked?

Should be excess of 98.5% fault coverage.

Procedure

Take each circuit node in sequence.

Held to 0 (S-A-0)

Identify the faults

Held to 1 (S-A-1)

Identify the faults

Total nodes detected as faultyFault Coverage =

Test vectors applied

A t ti T t P tt G ti


19/23

Automatic Test Pattern Generation

(ATPG)

For given fault, determine excitation vector (called test

vector) that will propagate error to primary

(observable) output.

Majority of available tools: combinational networks

only

Sequential ATPG available from academic research.


20/23

Automatic Test Pattern Generation

(ATPG)

Most ATPG approaches have been based onsimulation.

A five vale logic is used to implement test generation

algorithms

1 Logic One

0 Logic Zero

X Unknown or Dont Care ConditionD Logic 1 in good machine. Logic 0 in faulty

machine

D Logic 0 in good machine. Logic 1 in faulty

machine


21/23

Built in Self Test (BIST)

BIST lets blocks test themselves.

Generate pseudo-random inputs to

combinational logic.

Combine outputs into a syndrome.

With high probability, block is fault-free if itproduces the expected syndrome

Rapidly becoming more important with

increasing chip-complexity and largermodules


22/23

Built in Self Test (BIST)


23/23

THANK YOU

Documents

Edwin Vlsi Testing