VLSI Testing Lecture 8: Memory Test

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VLSI Testing Lecture 8: Memory Test. Memory organization Memory test complexity Faults and fault models MATS+ march test Address Decoder faults Summary References. RAM Organization. Test Time in Seconds (Memory Cycle Time 60ns). Size Number of Test Algorithm Operations. n 2 - PowerPoint PPT Presentation

Text of VLSI Testing Lecture 8: Memory Test

  • Copyright 2005, Agrawal & BushnellLecture 8: Memory Test*Memory organizationMemory test complexityFaults and fault modelsMATS+ march testAddress Decoder faultsSummaryReferencesVLSI Testing

    Lecture 8: Memory Test

    Lecture 8: Memory Test

  • Copyright 2005, Agrawal & BushnellLecture 8: Memory Test*RAM Organization

    Lecture 8: Memory Test

  • Copyright 2005, Agrawal & BushnellLecture 8: Memory Test*Test Time in Seconds(Memory Cycle Time 60ns)n bits

    1 Mb4 Mb16 Mb64 Mb256 Mb1 Gb2 Gbn

    0.060.251.014.0316.1164.43128.9n log2n

    1.265.5424.16104.7451.01932.83994.4n3/2

    64.5515.41.2 hr9.2 hr73.3 hr586.4 hr1658.6 hrn2

    18.3 hr293.2 hr4691.3 hr75060.0 hr1200959.9 hr19215358.4 hr76861433.7 hrSize Number of Test Algorithm Operations

    Lecture 8: Memory Test

  • Copyright 2005, Agrawal & BushnellLecture 8: Memory Test*SRAM Fault Modeling ExamplesSA0AF+SAFSAFSCF

    SCF

    SA0SA0TF

    TF

    Lecture 8: Memory Test

  • Copyright 2005, Agrawal & BushnellLecture 8: Memory Test*DRAM Fault ModelingANDBridgingFault (ABF)SA1+SCFSA1ABFSCFSA0ABF

    Lecture 8: Memory Test

  • Copyright 2005, Agrawal & BushnellLecture 8: Memory Test*SRAM Only Fault ModelsFaults found only in SRAMOpen-circuited pull-up deviceExcessive bit line coupling capacitanceModelDRFCF

    Lecture 8: Memory Test

  • Copyright 2005, Agrawal & BushnellLecture 8: Memory Test*DRAM Only Fault ModelsFaults only in DRAMData retention fault (sleeping sickness)Refresh line stuck-at faultBit-line voltage imbalance faultCoupling between word and bit lineSingle-ended bit-line voltage shiftPrecharge and decoder clock overlapModelDRFSAFPSFCFPSFAF

    Lecture 8: Memory Test

  • Copyright 2005, Agrawal & BushnellLecture 8: Memory Test*Reduced Functional FaultsSAFTFCFNPSFFaultStuck-at faultTransition faultCoupling faultNeighborhood Pattern Sensitive fault** M. L. Bushnell and V. D. Agrawal, Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits, Springer, 2000, Chapter 9.

    Lecture 8: Memory Test

  • Copyright 2005, Agrawal & BushnellLecture 8: Memory Test*Stuck-at FaultsTest Condition: For each cell, read a 0 and a 1.< /0> (< /1>)AA

    Lecture 8: Memory Test

  • Copyright 2005, Agrawal & BushnellLecture 8: Memory Test*Transition FaultsCell fails to make a 0 1 or 1 0 transition.Test Condition: Each cell must have an transition and a transition, and be read each time before making any further transitions., transition fault

    Lecture 8: Memory Test

  • Copyright 2005, Agrawal & BushnellLecture 8: Memory Test*Coupling FaultsCoupling Fault (CF): Transition in bit j (aggressor) causes unwanted change in bit i (victim)2-Coupling Fault: Involves 2 cells, special case of k-Coupling FaultMust restrict k cells for practicalityInversion (CFin) and Idempotent (CFid) Coupling Faults -- special cases of 2-Coupling FaultsBridging and State Coupling Faults involve any # of cellsDynamic Coupling Fault (CFdyn) -- Read or write on j forces i to 0 or 1

    Lecture 8: Memory Test

  • Copyright 2005, Agrawal & BushnellLecture 8: Memory Test*State Transition Diagram of Two Good Cells, i and j

    Lecture 8: Memory Test

  • Copyright 2005, Agrawal & BushnellLecture 8: Memory Test*State Transition Diagram for CFin < ; >

    Lecture 8: Memory Test

  • Copyright 2005, Agrawal & BushnellLecture 8: Memory Test*State Coupling Faults (SCF)Aggressor cell or line j is in a given state y and that forces victim cell or line i into state x< 0;0 >, < 0;1 >, < 1;0 >, < 1;1 >

    Lecture 8: Memory Test

  • Copyright 2005, Agrawal & BushnellLecture 8: Memory Test*March Test ElementsM0: { March element (w0) }for cell := 0 to n - 1 (or any other order) dowrite 0 to A [cell];M1: { March element (r0, w1) }for cell := 0 to n - 1 doread A [cell]; { Expected value = 0}write 1 to A [cell];M2: { March element (r1, w0) }for cell := n 1 down to 0 doread A [cell]; { Expected value = 1 }write 0 to A [cell];

    Lecture 8: Memory Test

  • Copyright 2005, Agrawal & BushnellLecture 8: Memory Test*March TestsAlgorithmMATSMATS+MATS++MARCH X

    MARCH C-

    MARCH AMARCH Y

    MARCH B

    Description{ (w0); (r0, w1); (r1) }{ (w0); (r0, w1); (r1, w0) }{ (w0); (r0, w1); (r1, w0, r0) }{ (w0); (r0, w1); (r1, w0); (r0) }{ (w0); (r0, w1); (r1, w0); (r0, w1); (r1, w0); (r0) }{ (w0); (r0, w1, w0, w1); (r1, w0, w1); (r1, w0, w1, w0); (r0, w1, w0) }{ (w0); (r0, w1, r1); (r1, w0, r0); (r0) }{ (w0); (r0, w1, r1, w0, r0, w1); (r1, w0, w1); (r1, w0, w1, w0);(r0, w1, w0) }

    Lecture 8: Memory Test

  • Copyright 2005, Agrawal & BushnellLecture 8: Memory Test*Address Decoder Faults (ADFs)Address decoding error assumptions:Decoder does not become sequentialSame behavior during both read and writeMultiple ADFs must be tested forDecoders can have CMOS stuck-open faults

    Lecture 8: Memory Test

  • Copyright 2005, Agrawal & BushnellLecture 8: Memory Test*TheoremA March test satisfying conditions 1 & 2 detects all address decoder faults.... Means any # of read or write operationsBefore condition 1, must have wx elementx can be 0 or 1, but must be consistent in test

    Lecture 8: Memory Test

  • Copyright 2005, Agrawal & BushnellLecture 8: Memory Test*March Test Fault CoverageAlgorithm

    MATSMATS+MATS++MARCH XMARCH C-MARCH AMARCH YMARCH BSAF

    AllAllAllAllAllAllAllAllADF

    SomeAllAllAllAllAllAllAllTF

    AllAllAllAllAllAllCFin

    AllAllAllAllAllCFid

    AllCFdyn

    All

    SCF

    All

    Lecture 8: Memory Test

  • Copyright 2005, Agrawal & BushnellLecture 8: Memory Test*March Test ComplexityAlgorithmMATSMATS+MATS++MARCH XMARCH C-MARCH AMARCH YMARCH BComplexity4n5n6n6n10n15n8n17n

    Lecture 8: Memory Test

  • Copyright 2005, Agrawal & BushnellLecture 8: Memory Test*MATS+ ExampleCell (2,1) SA0 FaultMATS+: { M0: (w0); M1: (r0, w1); M2: (r1, w0) }

    Lecture 8: Memory Test

  • Copyright 2005, Agrawal & BushnellLecture 8: Memory Test*MATS+ ExampleCell (2, 1) SA1 FaultMATS+: { M0: (w0); M1: (r0, w1); M2: (r1, w0) }

    Lecture 8: Memory Test

  • Copyright 2005, Agrawal & BushnellLecture 8: Memory Test*MATS+ ExampleMultiple AF: Addressed Cell Not Accessed; Data Written to Wrong CellCell (2,1) is not addressableAddress (2,1) maps onto (3,1), and vice versaCannot write (2,1), read (2,1) gives random dataMATS+: { M0: (w0); M1: (r0, w1); M2: (r1), w0 }

    Lecture 8: Memory Test

  • Copyright 2005, Agrawal & BushnellLecture 8: Memory Test*Memory Test SummaryMultiple fault models are essentialCombination of tests is essential:March test SRAM and DRAMOther tests (see references on following slide):NPSF -- DRAMDC parametric SRAM and DRAMAC parametric SRAM and DRAM

    Lecture 8: Memory Test

  • Copyright 2005, Agrawal & BushnellLecture 8: Memory Test*References on Memory TestR. D. Adams, High Performance Memory Testing, Boston: Springer, 2002.M. L. Bushnell and V. D. Agrawal, Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits, Boston: Springer, 2000.K. Chakraborty and P. Mazumder, Fault Tolerance and Reliability Techniques for High-Density Random-Access Memories, Upper Saddle River, New Jersey: Prentice Hall PTR, 2002.K. Chakraborty and P. Mazumder, Testing and Testable Design of High-Density Random-Access Memories, Boston: Springer, 1996.B. Prince, High Performance Memories, Revised Edition, Wiley, 1999.A. K. Sharma, Semiconductor Memories: Testing Technology, and Reliability, Piscataway, New Jersey: IEEE Press, 1997.A. J. van de Goor, Testing Semiconductor Memories, Chichester, UK: Wiley Interscience, 1991, reprinted by ComTex, Gouda, The Netherlands (http://ce.et.tudelft.nl/vdgoor/).

    Lecture 8: Memory Test

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