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ECE 255: L31

CMOS Op Amps

Mark Lundstrom School of ECE

Purdue University West Lafayette, IN USA

Spring 2019 Purdue University

Announcements

2 Lundstrom: 2019

HW9 Due 5:00 PM Friday, April 12 in EE-209 dropbox

Outline

3 Lundstrom: 2019

1) Review 2) PMOS input version 3) Two-Stage Op Amps (PMOS input)

CM loaded differential pair

4

IO

−VSS

+VDD

+υid 2

M1 M2

M3 M4 υO

Gm ≡

ioυid

= gm

Short-circuit transconductance

Output resistance

Rout = ro2 || ro4

−υid 2

CM loaded differential pair: equivalent circuit

5

Gmυid Rout

+υo

−

+υid 2

−υid 2

Gm = gm Rout = ro2 || ro4

υo = Gmυid Rout = gmυid ro2 || ro4( )

CM loaded differential pair: With load

6

Gmυid Rout

+υo

−

+υid 2

−υid 2

Gm = gm Rout = ro2 || ro4

υo = Gmυid Rout || RL = gmυid ro2 || ro4( ) || RL

RL

CM loaded differential pair

IO

−VSS

+VDD

+υid 2

M1 M2

M3 M4

−υid 2

Adm = gm ro2 || ro4( )

Rout = ro2 || ro4( )

υo = Gmυid Rout

CM loaded differential pair: With load

IO

−VSS

+VDD

+υid 2

M1 M2

M3 M4

−υid 2

Adm = gm ro2 || ro4( ) || RL

Rout = ro2 || ro4( )

RL

+υo

−

Problem 9.85

9

IO

−VSS

+VDD

υG1M1 M2

M3 M4

υO

υG2

Gm = 2 mA/V

υo RL = 20 k( ) = υo RL = ∞( )

2

Rout = ?

Adm RL = ∞( ) = ?

Problem 9.86

10

IO

−VSS

+VDD

υG1M1 M2

M3 M4

υO

υG2

′VA = 5 V/µm

Adm RL = ∞( ) = ?

L = 0.5 µm

VGS −Vtn = 0.25 V

Problem 9.88

11

IO

−VSS

+VDD

υG1M1 M2

M3 M4

υO

υG2

VA = 5 V

I0 = ?

Adm = 20

′kn W L = kn = 4 mA/V2

Common mode gain and CMRR

IO

−VSS

+VDD

υic

M1 M2

M3 M4 υo = Acmυic

Adm = gm ro2 || ro4( )

CMRR = Adm Acm

υic Acm ≈ − 1

2gm3RSS

Sec. 9.5.5

CM loaded differential pair

IO

−VSS

+VDD

+υid 2

M1 M2

M3 M4

−υid 2

υo

Adm = gm ro2 || ro4( )

Rout = ro2 || ro4( )

CMRR = Adm Acm

Acm ≈ − 1

2gm3RSS

Outline

14 Lundstrom: 2019

1) Review 2) PMOS input version 3) Two-Stage Op Amps (PMOS input)

PMOS input differential pair

M3 M4

M1 M2

+VDD

IO

−VSS

+υid 2 −υid 2

υo

Adm = −gm ro2 || ro4( )

Rout = ro2 || ro4( )

2-stage CMOS Op Amp

M3 M4

M1 M2

+VDD

IO1

−VSS

+υid 2 −υid 2

M5

+VDD

IO2

−VSS

υo

Rin2 →∞

CMOS Op Amp

Adm = Adm1 × ACS

Adm = −gm ro2 || ro4( )× −gm5 ro5 || Rocs( )⎡⎣ ⎤⎦

Acm = Acm1 × ACS

Acm ≈ − 1

2gm3RSS

× −gm5 ro5 || Rocs( )⎡⎣ ⎤⎦

CMRR =

Adm

Acm

Two-stage CMOS Op Amp

Fig. 9.40 Sedra and Smith 7th Ed.

Two-stage CMOS Op Amp

M5

M6

M7 M8

M3 M4

M1 M2 CC

+VDD

−VSS

+υid 2

−υid 2

υo IREF

Two-stage CMOS Op Amp

Adm = Adm1 × ACS

Adm = −gm ro2 || ro4( )× −gm6 ro6 || r07( )⎡⎣ ⎤⎦ =

gmro

2⎛⎝⎜

⎞⎠⎟

2

Adm =

gmro

2⎛⎝⎜

⎞⎠⎟

2

Rout =

ro

2⎛⎝⎜

⎞⎠⎟

Two-stage CMOS Op Amp: DC coupling

M5

M6

M7 M8

M3 M4

M1 M2 CC

+VDD

−VSS

+υid 2

−υid 2

υo IREF

DC coupled – carries signal, plus DC bias

Input offset voltage

+VO ≠ 0

−

1

2

Input offset voltage

+VO = 0

−

1

2

+VO = −VO Adn

−

“random offset” and “systematic offset”

See Sec. 9.6.1 eqn. (9.172)

Two-stage CMOS Op Amp: DC coupling

M5

M6

M7 M8

M3 M4

M1 M2 CC

+VDD

−VSS

+υid 2

−υid 2

υo IREF

W L( )6

W L( )4

= 2W L( )7

W L( )5eqn. (9.172) p. 663

Two-stage CMOS Op Amp: Capacitor

M5

M6

M7 M8

M3 M4

M1 M2 CC

+VDD

−VSS

+υid 2

−υid 2

υo IREF

Included for freq. response

Two-stage CMOS Op Amp: Summary

M5

M6

M7 M8

M3 M4

M1 M2 CC

+VDD

−VSS

+υid 2

−υid 2

υo IREF

See Chapter 13 for more

discussion

Two-stage CMOS Op Amp

You are encouraged to read through Example 9.6, pp. 661, 662

Two-stage CMOS Op Amp: Summary

Adm =

gmro

2⎛⎝⎜

⎞⎠⎟

2

Rout =

ro

2⎛⎝⎜

⎞⎠⎟

1000’s but not millions

relatively large, suitable for driving MOS ckts.

DC coupled – works all the way to DC

General purpose op amp requires more gain and a low output resistance.

741 Op Amp

29 Sedra and Smith, Section 13.3, 7th Ed.

LTSpice Project 3

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