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DESIGN AND ANALYSIS OF CMOS TELESCOPIC OPERATIONAL
AMPLIFIER
Thesis Report Submitted towards the Partial Fulfillment of Requirement
For the Award of the Degree of
Master of Engineering in Electronics and Communication
By
Jasmine
(Roll No. 8024108)
Under the guidance of
Mrs. ALPANA AGARWAL
Department of Electronics Communication Engineering
Thapar Institute Of Engineering Technology (Deemed University), Patiala
Certificate
This is to certify that the Thesis report entitled “ Design and analysis of
CMOS Telescopic Operational Amplifier ” which is being submitted
herewith by Ms. Jasmine (Roll No. 8024108) towards the partial fulfillment
for the award of the degree of Master of Engineering (Electronics &
Communication) of Thapar Institute of Engineering & Technology (Deemed
University), Patiala is a bonafide work carried by her under my supervision
and guidance during the session 2003-2004.
It is further certified that the research work
embodied in this thesis has not been
submitted to any other University/Institute
for the award of any degree/diploma.
Mrs. Alpana Agarwal
Asstt. Prof. ECED
TIET, Patiala (Supervisor)
Counter Signed by:
Dr. R.S. Kaler Prof. and HOD, ECED, TIET, Patiala
Dr. D.S. Bawa Dean of Academic Affairs
TIET, Patiala
Acknowledgement
To discover, analyse and to present something new is to venture on an
untrodden path towards an unexplored destination is an arduous adventure
unless one gets a true torchbearer to show the way. This enlightening
guidance, I found in my revered guide Mrs. Alpana Agarwal, Asstt. Prof. in
Deptt. Of Electronics & Communication Engineering, Thapar Institute of
Engineering & Technology (Deemed University), Patiala, without whose
patronisation it was never possible to give final shape to this thesis. I express
my heartfelt gratitude towards her for her valuable guidance, encouragement,
constant involvement, inspiration and the enthusiasm with which she solved
my difficulties.
I shall be failing in my duties if I do not express my
deep sense of gratitude towards Dr. R.S. Kaler Prof. & Head of the
Deptt. Of Electronics & Communication Engineering Technology
(Deemed University), Patiala who has been a constant source of
inspiration for me throughout the thesis semester.
I am also thankful to Mr. Sanjay Batish and Mrs. Sushma
Jain for extending their help in the VLSI Laboratory.
Last but not the least, I express my heartfelt thanks to my
parents, other members of the staff, my friends and well – wishers
for co-operation, which they were always ready to extend.
Jasmine
(RollNo.8024108)
Table of Contents
Certificate
Acknowledgement
Abstract
List of Figures
1. INTRODUCTION 1
1.1 Operational Amplifier 1
1.2 General issues 1
1.3 Performance Parameters 2
1.4 Basic architecture of op-amp
7
1.5 Objective of the work 9
1.6 Organization of the Thesis 10
2. COMMONLY USED TOPOLOGIES 12
2.1 Evolution 12
2.2 CMOS operational amplifier 12
2.3 Design of CMOS op-amp 13
2.4 Single stage vs Multistage 14
2.5 Other topologies 14
2.5.1 Two Stage Amplifier 14
2.5.2 Folded cascode amplifier 16
2.5.3 Telescopic cascode amplifier 17
3. TELESCOPIC CASCODE AMPLIFIER 19
3.1 Introduction 19
3.2 Differential Stage 22
3.3 High Compliance current mirror 23
3.4 Design Procedure 24
3.4.1 Design steps 24
3.4.2 An example 26
4. HIGH SWING OPERATIONAL AMPLIFIER 30
4.1 Importance of High Swing in operational amplifiers 30
4.2 Methodology for improved swing 31
4.3 Design Procedure 32
4.3.1 Design steps 32
4.4 An example 35
5. INTRODUCTION TO TANNER TOOL 40
5.1 Schematic Edit Tool (S-Edit) 40
5.2 T-SPICE Pro Circuit ANALYSIS 41
5.3 Circuit Simulator (T-Spice) 42
5.4 Waveform-Edit 45
5.5 Lay-Out (L-Edit) 46
6. NOISE ANALYSIS OF TELESCOPIC CASCODE 51
6.1 Types of noise 52
6.1.1 Thermal noise 52
6.1.2 Flicker noise 53
7. ANALOG LAYOUT DESIGN 55
7.1 Layout Design Rules 55
7.2 Layout of Transistors 57
7.3 Stacked Layout 61
7.4 Layout of Telescopic cascode amplifier 62
8. RESULTS AND DISCUSSIONS 64
8.1 Telescopic Operational Amplifier 64
8.2 High-Swing Telescopic Operational Amplifier 65
8.3 Layout 66
9. CONCLUSION 67
9.1 Work Done 67
9.2 Future Scope 68
REFERENCES
69
APPENDIX
LIST OF FIGURES 1.1: Symbol and equivalent circuit of the ideal op-amp 2
1.2: Schematic arrangement useful for simulating the differential
gain
3
1.3: Block diagram of Op-Amp 7
2.1: Two-stage amplifier 15
2.2: Folded Cascode amplifier 16
2.3: (a) Telescopic amplifier 18
2.3: (b) No-tail telescopic amplifier 18
3.1: Telescopic Cascode single stage OTA 20 3.2: Simplified equivalent circuit of a single stage OTA and its Bode
diagram 21
3.3: Differential Input Pair 22
3.4: High Compliance Current Mirror 23
3.5: Telescopic Cascode with their W/L’s 29
4.1: Methodology for enhancing swing 32
4.2: Telescopic cascode with enhanced swing and their W/L’s 39
6.1: Thermal noise of a resistor 52
6.2:Dangling bonds at the oxide silicon surface 53
7.1: The two layers that achieve a transistor 57
7.2: Layout of a p-channel transistor (inside an n-well) 58
7.3: Interdigitized transistor 59
7.4: Badly matching transistors: a) bad orientation b) with opposite current flow60
7.5: Layout of a matched transistor pair 61
7.6: Layout of current mirror 62
7.7: Telescopic Cascode single stage OTA 62
ABSTRACT
We are witnessing the dominance of microelectronics (VLSI) in every sphere of electronics and communications forming the backbone of modern electronics industry in mobile communications, computers, state-of-art processors etc. All efforts eventually converge on decreasing the power consumption entailed by ever shrinking size of the circuits enabling the portable gadgets. Designing high – performance analog circuits is becoming increasingly challenging with the persistent trend towards reduced supply voltages .The main bottleneck in an analog circuit is the operational – amplifier. At large supply voltages, there is a trade – off among speed, power and gain. The main characteristics under consideration are high gain, high PSRR, low offset voltage, high output swing. Performance of any circuit depends upon these characteristics. At reduced supply voltages, output swing becomes an important parameter. Due to the consistent efforts the Op-amp architectures have evolved from a simple Two-Stage architecture to the high performance Telescopic amplifier involving less power consumption, low noise, high gain etc. The design procedure for a Single Stage Telescopic op-amp is developed using design equations .The designed circuit is simulated using Tanner Tools. On the basis of simulation results the performance analysis has been done. The designed specifications are validated and the graphical analysis has been done. The simulated results are validating our designed values. The Telescopic op-amp has the inherent disadvantage of low output swing. A high-swing, high performance Single Stage CMOS Telescopic operational amplifier is analyzed and the results are presented in the form of design equations and procedure. The high swing of the op-amp is achieved by employing the tail and current source transistors in the deep linear region. Trade - off among such factors as bandwidth, Gain, Phase margin, bias voltages, output swing, slew rate, CMRR, PSRR, power are made evident. The results of SPICE simulation are shown to agree very well with the use of our design equations.
Noise limits the minimum signal level that a circuit can process with acceptable quality. Today’s analog designers constantly deal with the problem of noise because it trades with power dissipation, speed and linearity. Real circuits, of course, are never immune from small," random" fluctuations in voltage and current levels. In T-Spice, the influence of noise in a circuit can be simulated and reported in conjunction with AC analysis The physical mask layout of any circuit to be
manufactured using a particular process must confirm
to a set of geometric constraints or rules, which are
generally called layout design rules. Using the analog
layout techniques of matching transistors and stacked
layout one can develop the layout of any analog circuit.
A layout of Single stage CMOS Telescopic op-amp is
developed which works satisfactorily.
REFERENCES
[1] Allen Philip E., Holberg Douglas R., ‘‘CMOS Analog Circuit Design”
Oxford University Press, London, 2003, Second Edition.
[2] Allstot David J., “A Family of High-Swing CMOS Operational
Amplifiers”, IEEE Journal of Solid State Circuits, Vol. 24, No. 6, Dec.
1989.
[3] Babanezad J. N., “A low-output-impedance fully differential op amp with
large output swing and continuous-time common-mode feedback,” IEEE
J. Solid-State Circuits, Vol. 26, pp. 1825–1833, December 1991.
[4] Baker R.J, Li H.W, and Boyce D.E., “CMOS Circuit Design, Layout, and
Simulation”. Piscataway, NJ: IEEE Press, 1998, Chap, 26.
[5] Brown William C. and Szeto Andrew Y.J., “ Reconciling Spice Results and
Hand Calculations: Unexpected Problems” , IEEE Transaction on
Education, Vol.43, No.1, Feb. 2000.
[6] Bult K. and. Geelen G.J.G.M, “ A fast-settling CMOS op amp for SC
circuits with 90-dB DC gain,” IEEE J. Solid-State Circuits, Vol. 25,
pp.1379–1384, Dec. 1990.
[7] Chen Fred and Yang Kevin, EECS240 Term Project Report, “A Fully
Differential CMOS Telescopic operational amplifier with class AB output
stage”, Prof. B.E. Boser, spring 1999.
[8] Das Mrinal and Hellums Jim, Texas Instruments India Ltd., “ Improved
Design Criteria of Gain Boosted CMOS OTA with high speed
optimization” , IEEE J.Solid State Circuits, Vol.24, pp.553-559, June
1986.
[9] EE240 Final Project Report, “ High- Gain, 3V CMOS Fully Differential
Transconductance Amplifier ’ ’ , spring 1999, Department of Electrical and
Computer Sciences, University of California, Berkeley
[10] Fiez Terri S., Yang Howard C., Yang John J., Yu Choung, Allstot David
J., “ A Family of High-Swing CMOS Operational Amplifiers” , IEEE J.
Solid-State Circuits, Vol. 26, NO. 6, Dec. 1989.
[11] Geiger R.L., Allen P. E and Strader N. R., “ VLSI Design Techniques for
Analog and Digital Circuits”, McGraw-Hill Publishing Company, 1990.
[12] Gray P.R., Hurst P.J., Lewis S.H. and Meyer R.G., “ Analysis and Design
of Analog Integrated Circuits”, Fourth Edition, John Wiley & Sons,
2001.
[13] Gulati Kush and Lee Hae-Seung, ‘‘High – Swing CMOS Telescopic Operational Amplifier ’ ’ , IEEE Journal of Solid State Circuits, Vol. 33, No. 12, Dec. 1998.
[14] Kang Sung-Mo, Leblebici Yusuf, “CMOS Digital Integrated Circuits,
Analysis and design”, Tata McGraw-Hill Edition 2003, Third Edition
[15] Krenik W., Hellums J., Hsu W.C., Nail R., and Izzi L., “ High dynamic
range CMOS amplifier design in reduced supply voltage
environment,” Tech. Dig. Midwest Symp. Circuits and Systems, 1988, pp.
368–370.
[16] Li P.W., Chin M.J., Gray P. R and Castello R., “ A ratio-independent
algorithmic analog-to-digital conversion technique,” IEEE J. Solid-State.
Circuits, Vol. SC-19, pp. 1138–1143, Dec. 1984.
[17] Maloberti Franco, “ Analog Design for CMOS VLSI Systems” KLUWER
academic Publisher, Boston/ Dordrecht/ London.
[18] Nicollini G., Moretti F., and Conti M., “ High-frequency fully differential
filter using operational amplifiers without common-mode feedback,” IEEE
J.Solid State Circuits, Vol.24, pp.803-813, June 1989.
[19] Razavi Behzad, “ Design of Analog CMOS Integrated Circuits” , Tata
McGraw-Hill Publishing Company Limited.
[20] Ribner David B., Copeland Miles A, “ Design Techniques for Cascode
CMOS Op Amps with Improved PSRR and Common-Mode Input Range” ,
IEEE Journal of Solid State Circuits, Vol. 19, No. 6, Dec. 1984.
[21] Roewar Falk and Kleine Ulrich “ A Novel Class of Complementary
Folded-Cascode op-amps for low voltage” , IEEE J. Solid-State Circuits,
Vol. 37, No. 8, Aug. 2002.
[22] Steyaert Michel and Sansen Willy, “ A High-Dynamic-Range CMOS Op
Amp with Low-Distortion Output Structure” , IEEE Journal of Solid-
State Circuits, pp. 1204-1207, Vol. SC-22, No. 6, Dec. 1987.
[23] Steyaert M. and Sansen W., “ Power Supply Rejection Ratio in
Operational Transconductance Amplifiers” , IEEE Transactions on
Circuits and Systems, Vol. CAS-37, No. 9, pp. 1077-1084, 1990.
[24] Tsividis Y., “ Operation and Modeling of the MOS Transistors”, Second
Ed., Boston: McGraw-Hill, 1999.
[25] Tsividis Yannis P., “ Design Considerations in Single-Channel MOS
Analog Integrated Circuits – A Tutorial” , IEEE Journal of Solid-State
Circuits, pp. 383-391, Vol. SC-13, No. 3, June 1978.
[26] Yang J. and Lee H.S,“ A CMOS 12-bit 4 MHz pipelined A/D converter
with commutative feedback capacitor,” in Proc.IEEE Custom Integrated
Circuits Conf., pp. 427-430,1996.
[27] Zeki A. and Kuntman H., “ Accurate and High output impedance current
mirror suitable for CMOS current output stages” , IEE 1997 Electronics
letters online NO. 19970700.
.
Chapter 1
OPERATIONAL AMPLIFIER
1.1 INTRODUCTION Operational amplifiers (usually referred to as op-amps) are key
elements in analogue processing systems. Ideally they perform the function of
a voltage controlled current source, with an infinite voltage gain. Operational
amplifiers are an integral part of many analog and mixed-signal systems .Op
amps with vastly different levels of complexity are used to realize functions
ranging from dc bias generation to high-speed amplification or filtering. The
design of op amps continues to pose a challenge as the supply voltage and
transistor channel lengths scale down with each generation of CMOS
technologies [19].
1.2 GENERAL ISSUES The basic schematic of op-amp is shown in Fig.1.1. It is a four terminal
block with two inputs and two outputs. One of the outputs is the analog
ground. The key function of the op-amp is to generate at the output an
amplified replica of the voltage across the input terminals. Ideally, the voltage
gain is infinite. Moreover, the input impedance is infinite as well and the
output impedance is zero. Thus, the op-amp measures the input voltage in a
voltmetric fashion and generates the output in the same fashion as a voltage
controlled voltage source (VCVS) [19].
Fig.1.1 Symbol and equivalent circuit of the ideal op-amp
We normally define an op amp as a “ high-gain differential amplifier” . By
“ high” , we mean a value in the range of 110 to 510 . Since op amp are usually
employed to implement a feedback system, their open-loop gain is chosen
according to the precision required of the closed-loop circuit.
Up to two decades ago, most op amps were designed to serve as “ general –
purpose” building blocks, satisfying the requirements of many different
applications. Such efforts sought to create an “ ideal” op amp, e.g., with very
high voltage gain (several hundred thousand), high input impedance and low
output impedance, but at the cost of many other aspects of the performance,
e.g., speed, output voltage swing and power dissipation.
By contrast, today’ s op amp design proceeds with the recognition that the
trade-offs between the parameters eventually require a multidimensional
compromise in the overall implementation, making it necessary to know the
adequate value that must be achieved for each parameter. For example, if the
speed is critical while the gain error is not, a topology is chosen that favors the
former, possibly sacrificing the latter.
1.3 PERFORMANCE PARAMETERS The optimal selection of op-amp to be used in a particular application
is often the key factor, which determines the success or failure of the circuit.
There is a wide variety of op-amps available, from those requiring only 1 Volt
supply with bias currents of the 10-15 Amp range, to those that will output
hundreds of Volts at tens of Amps. There are many more parameters of op-
amps, which should be taken into consideration. Let’ s have a glance at few of
them: [1,17,19]
• DIFFERENTIAL GAIN (Ad)
This is the open loop differential gain measured as a function of
frequency. To estimate the differential gain the offset must be compensated.
Fig.1.2 shows a configuration for the SPICE estimation of the dc differential
gain. The small signal input generator is connected between the two input
terminals through a big capacitor C, while a T network made of two resistors
and capacitor establishes a feedback path around the op amp. A typical value
of the differential gain, Ad, ranges from 70 to 90 dB. For very precise
functions (like high-resolution data converters), the designer need higher gains
in the 100 to 140 dB range.
Fig.1.2 Schematic arrangement useful for simulating the differential gain
• COMMAN MODE GAIN (ACM)
This is the open loop gain obtained by applying a small signal to both inputs.
To measure it, the configuration discussed above can be used with a slight
modification .A signal generator is directly connected at the positive input and
short the positive and negative terminal with a big capacitor C. Ideally an op
amp should amplify the differential signal only. Thus, a low common mode
gain over a wide frequency is desired. A typical value of Acm at low frequency
is 10-30dB.
• COMMON MODE REJECTION RATIO
The common mode rejection ratio (CMRR) of an operational amplifier is the
ratio between the differential gain and the common mode gain. Where AD is
ba
D VVV
A−
= 0
The CMRR is defined as AD/AC or (in logarithmic units)
CMRR=20 log10 (AD/AC) in decibel
Typical CMRR values for CMOS
amplifiers are in the range 60 to 80 dB.
The CMRR measures how much the op-
amp can suppress noise, and hence a large
CMRR is an important requirement.
• POWER SUPPLY REJECTION RATIO (PSRR)
If we apply a small signal in series with the positive or the negative power
supply we obtain a corresponding signal at the output with a given
amplification (APS+ or APS-). The ratio between the differential gain and the
power supply gain leads to two PSRRs. These are two merit factors showing
the ability of the op-amp to reject spur signals coming from the power supply.
Having a good PSRR is an important merit. Unfortunately, especially at high
frequencies, the PSRR achieved is quite poor .A typical value of PSRR is
60dB at low frequencies that decreases to 20-40dB at high frequencies.
• OFFSET VOLTAGE (VOS)
If the differential input voltage of an ideal
op-amp is zero the output voltage is also
zero. This is not true in real circuits:
various reasons determine some
imbalancement that in turn lead to a non-
zero output. In order to bring the output to
zero it is therefore required to apply a
proper voltage at the input terminals. Such
a voltage is the offset.
• INPUT COMMON MODE RANGE (ICMR)
This is the voltage range that we can use at
input terminal without producing a
significant degradation in op-amp
performance. Since the typical input stage
of an op-amp is a differential pair, the
voltage required for the proper operation
of the current source and the input
transistors limit the input swing. A large
input common mode range is important
when the op-amp is used in the unity gain
configuration. In this case the input must
follow the output.
• OUTPUT VOLTAGE SWING
This is the maximum swing of the output node without producing a
significant degradation of op-amp performance. Since we have to leave
some room for the operation of the devices connected between the output
node and the supply nodes, the output swing is only a fraction of (VDD-
VSS). Typically it ranges between 60% and 80% of (VDD-VSS). Within the
output swing range the response of the op-amp should conform to given
specifications and in particular the harmonic distortion should remain
below the required level.
• UNITY GAIN BANDWIDTH
The speed performance of the op-amp is described by small and large signal
parameters .The small signal analysis determines the frequency response
sketched by a set of zeros and poles. Since we have to ensure stability, one of
the poles (f1) must be dominant. The amplitude Bode diagram will display a
20dB/decade roll-off until the gain reaches 0dB .The frequency at which the
gain becomes 0dB is called unity gain frequency fT . With a constant roll-off
20dB/decade of the achieved unity gain frequency equal to the product of gain
and bandwidth f1A0 . Therefore, fT is also known as the gain-bandwidth
product, GBW. Other poles, f2, f3…exceeding fT are named non-dominant
poles.
• PHASE MARGIN
This is the phase shift of the small –signal differential gain measured at the
unity gain frequency. In order to ensure stability when using the unity gain
configuration it is necessary to achieve a phase margin better than 60 degree.
A lower phase margin (like 45 degree or less) will cause ringing in the output
response. However, for integrated implementation it is not strictly necessary
to ensure absolute stability. The use of an op-amp in specific configurations
permits to know the value of the feedback factor�� ��,I� �LV�ORZHU�WKDQ���DV�LW�often happens) the 60-degree phase margin should be fulfilled not at the unity
JDLQ�IUHTXHQF\�EXW�DW�WKH�IUHTXHQF\�DW�ZKLFK�WKH�JDLQ�LV��� �
• SLEW RATE
This is the maximum achievable time derivative of the output voltage. It is
measured using the op-amp in the open loop or the unity gain configuration. A
large input step voltage fully imbalances the input differential stage and brings
the op-amp output response into the slewing conditions .The positive slew rate
can be different from the negative slew rate, depending on the specific design.
Typical values ranges between 40 and 80V/ VHF�� EXW�PLFUR�–power circuits
can show much lower figures.
• POWER CONSUMPTION
This is the power consumed under stand-
by conditions. The power used in the
presence of a large signal can significantly
exceed the one required in the quiescent
conditions. Moreover, the consumed
power depends on the speed
specifications. Typically, higher
bandwidth leads to higher power
consumption .Low power operation is a
very important quality factor: batteries that
should supply the system for hours or days
power more and more electronic systems.
Thus, a key design task is to achieve the
minimum power consumption for a given
required speed.
• SILICON AREA
Specific values of performances discussed above establish a given circuit configuration that, in turn leads to a corresponding silicon area. Typically the layout of an op-amp has a rectangular shape and includes substrate and well biases. For op-amp schemes of medium or low complexity it is possible to accommodate the entire layout within ������� � 2
.
1.4 BASIC ARCHITECTURE OF OP-AMP The typical gain that an op-amp (or for an OTA) should achieve is
around 80 dB. A simple gain stage has, a gain of the order of 40 db. Therefore,
the cascade of two stages is normally enough. Alternatively, we can use a
cascode with a cascode load configuration that alone obtains around 80 dB.
The choice between a single stage and a two stage architecture depends upon a
number of design issues like dynamic range, bandwidth and power
consumption.
The generic circuit schematic of an op-amp can be represented as shown in
Fig.1.3
Fig 1.3. Block diagram of Op-Amp
INPUT
STAGE
INTERMEDIATE
STAGE
LEVEL SHIFTING
STAGE
OUTPUT
STAGE
Dual-input, Balanced-output Differential Amplifier
Dual-input, Unbalanced-output Differential Amplifier
Such as emitter follower using constant current source
Complementary symmetry push-pull amplifier
The first block is a differential amplifier. It provides at the output a differential
voltage or a differential current that, essentially, depends on the differential
input only. The next block is a differential to single-ended converter. It is used
to transform the differential signal generated by the first block into a single
ended version. Some architecture doesn’ t require the differential to single
ended function; therefore the block can be excluded. Possibly, a second gain
stage enhances the differential gain. Finally, we have the output stage. It
typically provides a low output impedance or improves the slew rate of the op
–amp. Even the output stage can be dropped: many integrated applications do
not need low output impedance; moreover, the slew rate permitted by the gain
stage can be sufficient for the application. When the output stage is not used
the circuit, it is an operational transconductance amplifier, OTA. This circuit
achieves the voltage gain using an input transconductor and a relatively large
output resistance. The product of transconductance and output resistance fixes
upon the voltage gain.
The stages described above are being discussed in detail below:
� INPUT STAGE
The input stage is the dual-input, balanced-output differential amplifier.
This stage generally provides most of the voltage gain of the amplifier and
designed so that it provides a high input impedance, large common mode
rejection ratio, power supply rejection ratio, low offset voltage, low noise and
high gain.
� INTERMEDIATE STAGE
In most cases the gain provided by the input stages is not sufficient and
additional amplification is required. This is provided by intermediate stage,
which is another differential amplifier, driven by the output of the first stage.
It serves other purpose also. As this stage uses differential input unbalanced
output differential amplifier, so it provide required extra gain as well as
convert the differential signal to single ended signal. So that rest of the stages
need not contain symmetrical differential stages.
� LEVEL SHIFTING STAGE
As direct coupling is used in operation
amplifier, the dc voltage at the output of
intermediate stage is well above ground
potential. This increase in dc level tends to
shift the operating point of the succeeding
stages and, therefore limits the output
voltage swing and may even distort the
output signal. Therefore generally the
level translator (shifting) circuit is used
after the intermediate stage to shift the dc
level at the output of the intermediate
stage to zero volts with respect to ground.
� OUTPUT STAGE
This stage is output buffer. It provides the low output impedance and
larger output current needed to drive the load of op-amp. It normally does not
contribute to the voltage gain. If op-amp is the internal component of switched
capacitor circuit, the output load is usually a capacitor and the buffer need not
provide a large current or very low output impedance. However, if the op-amp
is at the circuit output, it may have to drive a large capacitor and low resistive
load. This requires large current driving capability and very low output
impedance, which can only be attained by using large devices with appreciable
dc bias currents. This is usually a push-pull complementary amplifier output
stage. The output stage increases the output voltage swing and raises the
current supplying capability of the op-amp. A well-designed output stage also
provides low output resistance.
1.5 OBJECTIVE OF THE WORK
Designing high – performance analog
circuits is becoming increasingly
challenging with the persistent trend
towards reduced supply voltages .The
main bottleneck in an analog circuit is the
operational – amplifier. At large supply
voltages, there is a trade – off among
speed, power and gain. The main
characteristics under consideration are
high gain, high PSRR, low offset voltage,
high output swing. Performance of any
circuit depends upon these characteristics.
At reduced supply voltages, output swing
becomes an important parameter. Due to
the consistent efforts the Op-amp
architectures have evolved from a simple
Two-Stage architecture to the high
performance Telescopic amplifier
involving less power consumption, low
noise, high gain etc. The objective of our
work is to design the procedure for
Telescopic operational amplifier and
evaluate the performance parameters.
1.6 ORGANIZATION OF THE THESIS Chapter 1: The basic architecture of CMOS op-amp and the definitions
related to it’ s concerned parameters along with the organization
of thesis and the objective of problem is discussed.
Chapter 2: Literature survey of some of the popular op-amp topologies is
being done along with their advantages and disadvantages.
Chapter 3: In the third chapter the design procedure of CMOS Telescopic op-
amp is
presented.
Chapter 4: In the fourth chapter the design procedure of High Swing CMOS
Telescopic op-amp is presented.
Chapter 5: The Tanner tools being used are discussed in detail.
Chapter 6: In the sixth chapter the noise analysis of Telescopic op-amp is
done.
Chapter 7: The physical layout of Telescopic op-amp and its design rules are
being discussed.
Chapter 8: This chapter illustrates the
results and discusses the same.
Chapter 9: The last chapter finally
concludes the problem and discusses
the scope for future work. After this
chapter, a list of important
references used to comprehend the
theoretical concepts is included.
Appendix: Papers presented and communicated:
• Presented paper on “ Design of improved swing CMOS
Telescopic operational amplifier” in National conference
on VLSI design and Technology held on 15-16 April
2004,BVCOE, New Delhi.
• Paper titled “ Design of CMOS Telescopic operational
amplifier ” communicated in VDAT-2004, 26-28 August,
2004 to be held in Mysore.
• Paper titled “ Noise analysis of CMOS Telescopic
operational amplifier ” communicated in National
Conference on Electronic Circuits & Communication
Systems (ECCS-04)” , September 23-24, 2004, TIET,
Patiala.
Chapter 2
COMMONLY USED TOPOLOGIES 2.1 EVOLUTION
The evolution of very large scale integration (VLSI) technology has
developed to the point where millions of transistors can be integrated on a
single die or “ chip” . Integrated circuits once filled the role of subsystem
components, partitioned at analog-digital boundaries, they now integrate
complete systems on a chip by combining both analog and digital functions.
Complementary Metal-oxide semiconductor (CMOS) technology has been the
mainstay in mixed –signal implementations because it provides density and
power savings on the digital side, and a good mix of Components for analog
design.
In a few years from now CMOS technology will overpower the whole
Electronics Industry. Designing High Performance analog circuits is becoming
increasingly challenging with the persistent trend toward reduced supply
voltages. The main bottleneck in an analog circuit is the OPERATIONAL –
AMPLIFIER. At large supply voltages, there is a tradeoff among speed,
power and gain amongst other performance parameters. Often these
parameters present contradictory Choices for the Operational – amplifier
architecture [1,2].
2.2 CMOS OPERATIONAL -AMPLIFIER It is one of the most versatile and important building blocks in analog
circuit design. Based upon the value of their output resistance they are being
classified into two categories [1].
1. UNBUFFERED OPERATIONAL-AMPLIFIER: These are Operational
Transconductance Amplifiers (OTA), which have high output resistance.
2. BUFFERED OPERATIONAL –AMLIFIER: These are Voltage
Operational Amplifiers, which have low output resistance.
Operational - amplifiers are amplifiers (controlled sources) that have
sufficiently high forward gain so that when negative feedback is applied, the
closed-loop transfer – function is practically independent of the gain of the op-
amp. The primary requirement of an op-amp is to have an open loop gain that
is sufficiently large to implement negative feed –back concept.
2.3 DESIGN OF CMOS OP-AMPS CMOS op-amps are very similar in architecture to their bipolar counterparts.
It has different stages, which are explained below [2,3,18,19]
DIFFERENTIAL TRANSCONDUCTANCE STAGE ¾ It forms input to op-amp.
¾ This stage sometimes provides the differential to single stage
conversion.
¾ Normally a good portion of overall gain is provided by this stage,
which improves Noise and offset performance.
HIGH GAIN STAGE ¾ It is the second stage of op-amp, which is typically an inverter.
¾ If the differential input stage doesn’ t perform the differential – to-
single –ended conversion then it is accomplished by the second stage
inverter.
BUFFER STAGE
¾ If the op-amp must drive a low resistance load, the second stage must
be followed by a buffer stage whose objective is to lower the output
resistance and maintain a large Signal swing.
BIAS CIRCUITS
¾ Bias circuits are provided to establish the proper operating point for
each transistor in quiescent stage
When selecting an optimal architecture for the operational –amplifier, several fundamental Issues and tradeoffs are needed to be considered based upon
the specific requirements.
2.4 SINGLE STAGE vs. MULTI STAGE 1. Single stage circuits are inherently faster than Multi stage designs due to
the presence of fewer poles [20].
2. Single stage circuits consume less power because of fewer current legs.
3. But it is very difficult for a single stage circuit to meet the requirements
for gain and dynamic range under very low supply voltage like that of 3 V
or low.
2.5 OTHER TOPOLOGIES
There are several available op-amp architectures. A few popular topologies
are discussed below:
2.5.1 TWO STAGE AMPLIFIER With all the transistors in the output stage of this amplifier
placed in the saturation regime, it has a differential output swing of 2Vsup –
4Vds,sat where
Vsup = supply voltage
Vds, sat = minimum Vds required to saturate a transistor for a typical Vds, sat of
200mV, the differential swing is about 2Vsup – 0.8V which is superior to that
of most other topologies. It’ s non-dominant poles arising from it’ s output
nodes, is located at (gm6/CL), where
gm6 = transconductance of transistor M5 or M6
CL = load capacitance
Since this pole is determined by an explicit load capacitance, it typically
occurs at a relatively low frequency.
Fig 2.1 Two – Stage amplifier
ADVANTAGES: 1. It has high output voltage swing.
DISADVANTAGES: 1. It has a compromised frequency response.
2. This topology has high power consumption because of two stages in it’ s
design.
3. It has a poor negative Power Supply Rejection at higher frequencies.
This op-amp particularly has applications in Telecommunications area. After
initial success, it was noted that this op-amp suffers from a poor PSRR
(Power Supply Rejection Ratio) [15].
2.5.2 FOLDED CASCODE AMPLIFIER Although only Vds, sat is needed to saturate the bottom-most load transistors
and the top –most current source transistors in order to allow for process
variation, a small safety margin Vmargin is often added to Vds to ensure
saturation. Accounting for these, and the Vds, sat the differential output
swing is 2 Vsup – 8 Vds, sat – 4 Vmargin. With a voltage margin of 100mV, this is
estimated to be 2 Vsup – 2V.
Although the currents in the output stage can be much smaller than that
flowing through the input devices, in practice, the output stage current is
picked to be the same or almost the same as the current in the input stage
[21,23].
Fig 2.2 Folded Cascode amplifier
ADVANTAGES: 1. This design has corresponding superior frequency response than two –
stage operational - amplifiers.
2. It has better high frequency Power Supply Rejection Ratio (PSRR).
The power consumption of this design is approximately the same as that of
the two-stage design
DISADVANTAGES: 1. Folded cascode has two extra current legs, and thus for a given settling
requirment, they will double the power dissipation.
2. The folded cascode stage also has more devices, which contribute
significant input referred thermal noise to the signal.
2.5.3 TELESCOPIC CASCODE AMPLIFIER Although Telescopic operational - amplifier has smaller swing, which
means reduced dynamic range, this is offset somewhat by the lower noise
factor. The above reason implies that the Telescopic op-amp is a better
candidate for low power, low noise single stage Operational
Transconductance Amplifier. The single stage architecture normally
suggests low power consumption [13].
Disadvantage of a Telescopic op-amp is severely limited output
swing. It is smaller than that of Folded Cascode because the tail transistor
directly cuts into output swing from both sides of the operational - amplifier.
The Telescopic operational - amplifier shown in fig 2.3(a), all transistors are biased in saturation region. Transistors M1 - M2, M7 – M8, and tail current source M9 must have at least Vds, sat to offer good common - mode rejection, frequency response and gain.
The maximum differential output swing of a telescopic op-amp is 2Vsup -
10Vds,sat - 6Vmargin . Under identical conditions, the output swing of this design
is limited to 2Vsup-2.6V.In a 3V supply system; this represents a 45%
reduction of the available output swing. At large supply voltages, the
telescopic architecture becomes the natural choice for systems requiring
moderate gain for the op-amp. Reducing supply voltages, on the other hand,
forces reconsideration in favour of the Folded Cascode, or in the extreme case,
the two-stage design.
Although a Telescopic op-amp without the tail current source fig
2.3(b) improves the differential swing by 2Vds,sat + 2Vmargin (600 mV), the
common – mode rejection and power-supply rejection of such a circuit is
greatly compromised. Moreover, the performance parameters (such as unity-
gain frequency) of the op-amp with no tail or with a tail transistor in the linear
region is sensitive to input common- mode and supply voltage variation,
which is undesirable in most analog cases.
Fig 2.3 (a) Telescopic amplifier Fig 2.3 (b) No-tail telescopic amplifier
Other op-amps that have traditionally been employed in high performance
applications include the class AB op-amp. This amplifier, however
requirements a minimum supply voltage of 2Vt + 4Vds,sat + 2Vmargin , where
Vt = threshold voltage
For Vt = 0.8V, Vsup must be greater than 2.6V.
This requirement renders this architecture unsuitable in future Low Voltage
Applications. Other drawbacks are degraded frequency response and large op-
amp noise. The design under consideration combines the low power, high-
speed advantage of the Telescopic architecture with the high Swing capability
of the Folded Cascode and the Two Stage Design. It achieves its high
performance while maintaining High Common mode and supply rejection and
ensuring constant performance parameters [7].
Chapter 3
TELESCOPIC CASCODE AMPLIFIER 3.1 INTRODUCTION
The gain that can be achieved by a single stage is around 40 dB. Thus, in
order to achieve 80 dB or so it is necessary to use a cascade of two stages. However,
two stages bring about two poles one close to the other and this requires compensation
network, besides increasing the global complexity, reduces the design flexibility.
A cascode with cascode load permits us to achieve high gain (around
80 dB) without the disadvantage of having two poles one close to each other.
Therefore, the use of cascode based OTA is an interesting solution alternative
to the two stages OTA [1,17,19].
The simp lest version of a sing le stage OTA is the telesc op ic
a rc hitec ture, shown in Fig3.1, the input d ifferentia l pa ir injec ts the
signa l c urrents into c ommon ga te stages. Then, the c irc uit
ac hieves the d ifferentia l to sing le ended c onversion with a
c asc ode c urrent mirror .The transistors a re p lac ed one on the top
o f the other to c rea te a sort of Telesc op ic c omposition (from this
the name of the c irc uit). The sma ll signa l resistanc e a t the output
node is quite high: it is the para llel c onnec tion o f two c asc ode
c onfigura tions. Suc h a high resistanc e benefits the sma ll signa l
ga in without limiting the c irc uit func tiona lity when we require an
OTA func tion.
By inspection of the circuit one finds the low-frequency small signal differential gain is proportional to the square of the product of a transistor transconductance and an output resistance.
Ao= gm1
+ 442668
442668 .
dsmdsdsmds
dsmdsdsmds
rgrrgrrgrrgr
Thus, as expected, the telescopic cascode achieves a gain similar to the one of the two stages architecture. Moreover, by inspection of the circuit, all the nodes, excluding the output,
Fig.3.1 Telescopic Cascode single stage OTA
shows a pretty low small signal resistance. Node I is an equivalent ground for
differential signals; node 2,3 and 4 are source terminals of transistors M3, M4
and M6 respectively.
. Assuming the capacitance is affecting the given nodes due to parasitic
contributions, the resulting time constants are all much smaller than the one
associated to the output node. Thus, the output node can easily become the
dominant pole of the circuit. Since the circuit shows one high impedance node
only, it is not possible (and not necessary) to exploit the Miller effect to
procure pole splitting. A possible capacitance loading the output node permits
to make dominant the related pole and ensure stability [1,17].
Thus, the 0 dB axis is crossed at the angular frequency Fig. 3.2 shows
the simplified small signal equivalent circuit for a single pole approximation.
The current generated by the transconductance generator gm1vin is injected into
the output resistance that is in parallel with the capacitance at the output node
(CL). The time constant CLrout gives rise to a pole that causes a roll-off of the
Bode plot with a slope of 20 dB/decade.
Fig.3.2 Simplified equivalent circuit of a single stage OTA and its Bode diagram
wT = gm1/CL
The Telescopic configuration uses only one bias current. It flows through the
differential input stage, the common base stage and the differential to single
ended converter. Therefore, for a given bias voltage, the power is used at the
best .By contrast, we have disadvantages: they concern the limited allowed
output dynamic range and the request to have an input common mode voltage
pretty close to ground (or Vss).
The Triode limit of M6 establishes the maximum allowed output voltage. By
inspection of the circuit it is given by
Vout, max= VDD – VGS7 – VGS5 + VGS6 – VSAT,P = VDD – VTh,P – 2VSAT,P
For typical situations it is 1 V or more below the positive supply voltage.
The lower boundary of the output voltage depends the triode limit of M4
that, in turn depends on VB1
Vout, min = VB1 – VGS4 + Vsat, 4 = VB1 – VTh,n
Normally the designer broadens the output swing by keeping low VB1.
However, the value of VB1 affects the minimum level of the input common
mode voltage
Vin, cm <= VB1 – VGS4 – Vsat,2 + VGS2 = VB1 – 2Vsat,n
In turn, the input common mode voltage should allow M9 to be in the
saturation region.
Vin, cm > VSAT, 9 + VGS2
Therefore, we can achieve an optimum negative swing (3Vsat,n above ground)
Keeping the input common mode voltage as low as Vsat, 9 + VGS2
approximately equal to VTh, n + 2Vsat). Assuming a symmetrical output swing
around Vout.max and Vout.min the output common mode voltage becomes
Vout, cm = VDD + VB1 – VTh,n – VTh,p – 2Vsat,p
That for a typical design is a bit higher than VB1 . Thus, the output common
mode voltage is different (higher) than the input common mode voltage. This,
in some applications is a limit: for instance, it is not possible to connect the
Telescopic cascode in the unity gain configuration. An interesting feature of
this configuration is that it needs only two wires for the Biasing. Let’ s discuss
the Building blocks of a Telescopic op-amp in detail.
3.2 DIFFERENTIAL STAGE A differential pair is widely used as the input stage of the op-amplifier.
Fig 3.3 shows its CMOS configuration. It is made of two transistors with their
source in
Fig.3.3 Differential Input Pair
common, fed by current source. The transistors may either be n-channel (as
shown in Figure or p-channel, and they are matched to each other. If the two
transistors are in saturation region, we can write
( )21121 ThGS
ox VVL
WCI −
= P
( )22222 ThGS
ox VVL
WCI −
= P
where (W/L)1 and (W/L)2 are exactly equal, the transistors being matched.
Moreover, in the above equations the output conductance has been neglected.
The input signals can be expressed as
VGS1 = VGS0 + Vin/2;
VGS1 = VGS0 - Vin/2
Where VGS0 is the common mode component and Vin is a differential signal.
Since the bias current can be expressed as
( )211
21 ThGS VVL
WOXSS CIII −
=+= P
Therefore, in the differential stage, like in the case of the inverter with active load, the transconductance gain increases with the square root of the bias current [17].
3.3 High Compliance Current Mirror The current mismatch inherent to the modified cascode configurations and the
additional circuit complexity can be avoided by using the high compliance
scheme, shown in Fig.3.4 By comparing the given circuit with the usual
cascode current mirror.
Fig.3.4 High Compliance Current Mirror
There is diode connection of transistor M1 incorporates transistor
M4.Therefore, the drain-to –source voltage of M1 is no longer equal to its gate-
to-source voltage. Instead the value of VDS1 and that of VDS2 are controlled
by the gate of transistors M4 and M3 respectively. The matching between these
two elements ensures identical voltage at the drains of M1 and M2, thus leading
to a systematic current matching. The gates of M3 and M4 should be biased by
a voltage that keeps both M1 and M2 in saturation and which, at the same time,
should avoid M4 going into triode region. Therefore,
Vbias – VTh, 4 – Vsat, 4 > Vsat, 1
Vbias – Vds1 – VTh, 4 < VTh, 1 + Vsat, 1 – Vds1
that requires keeping Vbias between one threshold plus two saturations and two
thresholds plus one saturation. This condition can be achieved because VTh is
normally higher than Vsat. The designed value of Vbias causes VGS1 to split
between VDS1 and VDS2. Typically the choose value of Vbias splits VGS1 evenly
between the two drain-to-source voltage [17].
3.4 DESIGN PROCEDURE
SPECIFICATIONS � Gain at dc (Av)
� Unity gain bandwidth (GB)
� Load capacitance (CL)
� Slew rate (SR)
� Power Dissipation (Pdiss)
3.4.1 DESIGN STEPS
STEP1: The first step of the design gives the estimation of the bias current.
assuming the GBW established by the dominant node, we have
( ) LTHGS
ssT CVV
If 12
2−
=S
where Iss is the tail current.
STEP 2: Design Tail transistor M9 and calculate W and L of this transistor by
using the transistor in saturation .The equation used is
( )2ThGS
9
oxSS VV
LW
2C
I −
µ=
STEP 3: Calculate the bias VB2 of transistor M9 using the equation
VB2 = VGS9 – VTh
STEP 4: Design the differential pair of the circuit, by assuming both of them
to be working in saturation mode. Their aspect ratios could be
calculated using bias current Iss. The equation used is
( )2ThGS
1
oxSS VVLW
CI −
µ=
STEP 5:Calculate the common mode voltage that allows M9 to be in
saturation
Vin, cm >= Vsat, 9 + VGS1
STEP 6: Design the High Compliance Current mirror and calculate the Bias
voltage that is applied to both the gates by the following equation
VB1 – V2 – VTh, n = Vsat, 3
Where VB1 is the bias voltage that is applied to High
Compliance current mirror, V2 is the voltage at node 2 and VTh, n is
the threshold voltage. The aspect ratios of transistors M3 and M4
can be calculated by assuming both the transistors in saturation and
both are matching. The current equation is
( )2
4,3ThGSoxSS VV
LWCI −
= P
where
VGS = VB1 – Vsat, 2 – VTh,n
STEP 7: Design the Cascode Current Mirror stage where there are four
PMOS transistors, which are identical, and the current passing
through them is same as the drain and gate are tied to each other. They all are in saturation mode. The current flowing is same that was in High Compliance Current Mirror stage.
The aspect ratios can be calculated by the following current equation
( )2
8,7,6,5ThGSoxSS VV
LWCI −
= P
Where
VGS = VDD – 3VTh,p
3.4.2 AN EXAMPLE SPECIFICATIONS
• 6OHZ�UDWH� ����9� V • Load capacitor = 3pf
• Unity Gain Bandwidth = 1 MHz
• DC gain = 70dB
• Phase Margin = 55 degree
STEP 1: Estimation of Bias current ISS
AI
I
SS
SS
P
S
5.56)10*3)(1.0(
*210*60**2 12
6
=
= −
���EXW�WDNH�LW�DV���� A; it accounts for some margin and for
different VDS in the reference generator and tail current source.
STEP 2: Design M9 by taking saturation current equation
( )
VVVVVV
WL
LW
LW
B
GSB
ThGS
8.0
1.02.474
10
42.47
1.02
10*33.610*150
2
92
9
9
2
9
56
==
=−=
=
=
=
−−
PP
we are taking L as 10 times the technology parameter. Since we are
XVLQJ��PLFURQ�WHFKQRORJ\��WDNH�/ �� � Also, we are assuming for the input pair VGS – VTh = 0.1V
STEP 3: Design M1 and M2 by taking half the tail current and calculate their
aspect ratios that would be same and then calculate the common –
mode input voltage.
( )
09.237
1.0*10*63.610*150
2,1
2
2,1
56
=
= −−
LW
LW
P
P9.2370
10=
=WL
( )( ) 1.0
09.237*10*33.62*10*75
1
5
62
1
=−
=− −
−
ThGS
ThGS
VV
VV
VV
V
VVVVV
cmin
cmin
GSsatcmin
GS
9.0
8.01.0
8.0
,
,
19,,
1
=+≥
+≥=
STEP 4:Design High Compliance Current mirror and Bias voltage VB1 .The
two transistors used are identical. Calculate their aspect ratios by
using the differential current and keeping both the transistors in
saturation.
VB1 – V2 – VTh, n = Vsat, 3
VB1- 0.2 - 0.7 = 0.3
VB1 = 1.2V
Now,
( )
( ) PP
13210
2.13
7.02.02.1*10*33.610*75
4,3
4,3
2
4,3
56
==
=
−−
= −−
WL
LW
LW
STEP 5: Design the cascade current mirror .It consists of four PMOS
transistors that are identical and the current passing through all of
them is same as that of the previous stage i.e. High compliance
current mirror. Determine their aspect ratios by placing all
transistors into saturation.
( )2
8,7,6,5
56 89.15**10*64.210*75 −
= −−
LW
129.08,7,6,5
≅=
LW
PP
1010
==
WL
Since we have to take the aspect ratio at-least 1 .So taking the approximate
value of 1.
STEP 6:Calculating the maximum and minimum values of output voltage.
The circuit used has three drain-to-source jumps. Thus, designed VB1
and input common-mode voltage would permit a minimum output
swing just at three saturations above ground. Thus,
Vout, min = 3Vsat,n = 0.3V
By contrast it is not possible to have the output swing close to the
positive rail. Thus, upward swing is given by,
Vout, max = VDD – VTh, p – 2Vsat,p =(1.8 - 0.7) = 1.1V
Table 1
MOS M1 M2 M3 M4 M5 M6 M7 M8 M9
W/L 237.09 237.09 13.2 13.2 1 1 1 1 47.42
Fig.3.5.Telescopic Cascode with their W/L’ s
Chapter 4
HIGH SWING OPERATIONAL AMPLIFIER
4.1 IMPORTANCE OF HIGH SWING IN
OPERATIONAL AMPLIFIERS
In analog circuits where kT/C noise is the dominant noise, the relationship
between op-amp performance metrics such as speed, signal-to-noise ratio
(SNR), and power consumption can be shown to be
)I.(V
Cgm
.
CkT
)Swing(Power
Speed.SNR
sup
2
λ
β
γ
=
(1)
where the constants β, γ and λare the feedback factor of the closed-loop op-
amp, the number of kT/C noise contributions at the output of the amplifier,
and the ratio of the total current consumption of the op-amp to the current I
flowing through one of the input devices, respectively. Here, speed
corresponds to the dominant pole location of the op-amp. The above
expression simplifies to
sup
2
V)Swing(
PowerSpeed.SNR ∝
(2)
where gm ∝ I as in the case when the input devices are in weak inversion or
in the saturation region of strong inversion. The proportionality constant in the
last term is a function of the architecture of the op-amp and the switched-
capacitor circuitry around the op-amp. It is clear from this expression that
increase in the swing of the op-amp leads to overall performance improvement
that can be exploited to achieve lower power or higher SNR or speed [2,10].
4.2 METHODOLOGY FOR IMPROVED SWING In the topology shown in Fig. 4.1, transistors M7–M9 are deliberately driven
deep into the linear region. Since these transistors normally operate in the
linear region Vmargin, is not needed across these devices. Under these
conditions, the output swing is shown to be
,loadlin,dstaillin,dsinargmsat,dssup V2V2V2V6V2 −− −−−− where taillin,dsV − and ,loadlin,dsV − are the
drain-to-source voltages for the tail and load transistors, respectively. With
Vds, sat of 200 mV, Vmargin of 100 mV, Vds, lin-tail of 80 mV, and Vds, lin-load of 160
mV, the differential output swing is 2Vsup-1.88 V, which is superior not only
to a telescopic amplifier by about 0.7 V but also to a regular folded-cascode
amplifier by roughly 100 mV. The swing enhancement stems not only from
the difference between Vds, sat and the voltage across the devices in the linear
region but also because of the fact that we no longer need Vmargin across
devices placed in the linear region. It is important to note that any reduction in
voltage across the tail transistor improves differential swing twofold as the tail
transistor cuts into the output swing from both sides of the amplifier. Also, the
elimination of Vmargin across the tail and the load devices itself contributes to a
swing enhancement of 4Vmargin . This benefit of increased swing by pushing
the load and tail transistors in the linear region, however, is accompanied by
slightly degraded common-mode rejection ratio (CMRR) and differential gain
of the amplifier. The PSRR positive and PSRR negative remains the same and
less power dissipation and good slew rate [13,25].
Fig .4.1. Methodology for enhancing swing
4.3 DESIGN PROCEDURE
SPECIFICATIONS
� Unity gain bandwidth (GB)
� Load capacitance (CL)
� Slew rate (SR)
� Power Dissipation (Pdiss)
4.3.1 DESIGN STEPS A design procedure is developed for improving output swing of Single stage CMOS Telescopic operational
amplifier.
STEP 1: The first step of the design is the estimation of the bias current.
Assuming the GBW established by the dominant node, we have
( ) LTHGS
ssT C
1VV
I2f2
−=π
where Iss is the tail current.
STEP 2: Design Tail transistor M9 and calculate W and L of this transistor by
using the transistor in deep linear region. The equation used is
( )( )2
9
22 DSDSTGS
oxSS VVVV
LWCI −−
= P
where TGS VV ≥
TGSDS VVV −%
STEP 3: Calculate the bias VB2 of transistor M9 using the equation
VB2 = VGS9 – VTh
STEP 4: Design the differential pair of the circuit, by assuming both of them
to be working in saturation mode. Their aspect ratios could be
calculated using bias current Iss. The equation used is
( )2
2,1
ThGSoxSS VVL
WCI −
= P
STEP 5: Calculate the common mode voltage that allows M9 to be in
saturation
Vin, cm >= Vsat, 9 + VGS1
STEP 6: Design the High Compliance Current mirror and calculate the bias
voltage that is applied to both the gates by the following equation
VB1 – V2 – VTh, n = Vsat, 3
Where VB1 is the bias voltage that is applied to High Compliance
current mirror, V2 is the voltage at node 2 and VTh, n is the Threshold
voltage .The aspect ratios of transistors M3 and M4 can be calculated
by assuming both the transistors in saturation and both are matching.
The current equation is
( )2
4,3ThGSoxSS VV
LWCI −
= P
where
VGS = VB1 – Vsat, 2 – VTh, n
STEP 7: Design the Cascode Current Mirror stage where there are four PMOS
transistors, which are identical, and the current passing through them
is same as the drain and gate are tied to each other. The transistors
M5 and M6 are in saturation mode while transistors M7 and M8 are
deliberately driven into deep linear region. The current flowing is
same that was in High Compliance Current Mirror stage. The aspect
ratios can be calculated by the following current equation
( )2
6,56,5 ThGSox VV
LWCI −
= P
Where
VGS = VDD – 3VTh,p
The top most cascode load transistors are driven in deep linear
region. The current equation is
( )( )2
8,7
22 DSDSTGS
oxSS VVVV
LWC
I −−
=
P
Where TGS VV ≤
TGSDS VVV −
4.4 AN EXAMPLE SPECIFICATIONS
• 6OHZ�UDWH� ����9� V • Load capacitor = 3pf
• Unity Gain Bandwidth = 1 MHz
• DC gain = 70dB
• Phase Margin = 60 degree
STEP 1: Estimation of Bias current ISS
AI
I
SS
SS
P
S
5.56)10*3)(1.0(
*210*60**2 12
6
=
= −
�������EXW�WDNH�LW�DV���� A; it accounts for some margin and for
different VDS in the reference generator and tail current source
STEP 2:Design Tail transistor M9 and calculate W and L of this transistor by
using the transistor in deep linear region. The equation used is
( )( )2
9
22 DSDSTGS
oxSS VVVV
LWCI −−
= P
))07.0()07.0)(1.0(2(2
10*33.610*150 2
9
56 −
=
−−
LW
08.5219
=
LW
VVVV
VVV
WL
B
GSB
DS
ThGS
8.0
07.0
1.083.5210
10
2
92
9
===
=−=
=P
P
we are taking L as 10 times the technology parameter. Since we are
using 1micrRQ�WHFKQRORJ\��WDNH�/ �� � Also, we are assuming for the input pair VGS – VTh = 0.1V
STEP 3: Design M1 and M2 by taking half the tail current and calculate their
aspect ratios that would be same and then calculate the common –
mode input voltage.
( )
( )( )
VV
V
VVVVV
VV
VV
WL
LW
LW
cmin
cmin
GSsatcmin
GS
ThGS
ThGS
9.0
8.01.0
8.0
1.009.237*10*33.6
2*10*75
9.237010
09.237
1.0*10*63.610*150
,
,
19,,
1
1
5
62
1
2,1
2
2,1
56
=+≥
+≥=
=−
=−
==
=
=
−
−
−−
PP
STEP 4:Design High Compliance Current mirror and Bias voltage VB1 .The
two transistors used are identical. Calculate their aspect ratios by
using the differential current and keeping both the transistors in
saturation.
VB1 – V2 – VTh, n = Vsat, 3
VB1- 0.2 - 0.7 = 0.3
VB1 = 1.2V
Now,
( )
( ) PP
13210
2.13
7.02.02.1*10*33.610*75
4,3
4,3
2
4,3
56
==
=
−−
= −−
WL
LW
LW
STEP 5: Design the Cascode Current Mirror stage where there are four
PMOS transistors, which are identical, and the current passing
through them is same as the drain and gate are tied to each other.
The transistors M5 and M6 are in saturation mode while transistors
M7 and M8 are deliberately driven into deep linear region. The
current flowing is same that was in High Compliance Current Mirror
stage. The aspect ratios can be calculated by the following current
equation
( )2
6,56,5 ThGSox VV
LWCI −
= P
Where
VGS = VDD – 3VTh,p
The top most Cascode load transistors are driven in deep linear
region .The current equation is
( )( )2
9
22 DSDSTGS
oxSS VVVV
LWCI −−
= P
Where TGS VV ≤
TGSDS VVV −
( )
PP
1010
129.0
89.15**10*64.210*75
6,5
2
6,5
56
==
≅=
−
= −−
WL
LW
LW
Since we have to take the aspect ratio at-least 1 .So taking the
approximate value of 1.
13.0
1.055.6254
10
455.625
))13.0()13.0)(1.0(2(2
10*33.610*150
9
8,7
2
8,7
56
==−
==
=
−−
=
−−
DS
ThGS
VVV
WL
LW
LW
PP
STEP 6: Calculating the maximum and minimum values of output voltage.
The circuit used has three drain-to-source jumps. Thus, designed
VB1 and input common-mode voltage would permit a minimum
output swing just at three saturations above ground. Thus,
Vout, min = 3Vsat,n = 0.3V
By contrast it is not possible to have the output swing close to the
positive rail. Thus, upward swing is given by,
Vout, max = VDD – VTh, p – 2Vsat,p =(1.8 - 0.7) = 1.1V
Table 2
MOS M1 M2 M3 M4 M5 M6 M7 M8 M9
W/L 237.09 237.09 13.2 13.2 1 1 625.45 625.45 521.08
Chapter 5
5.Introduction to Tanner Tool
Tanner tool is a Spice Computer Analysis Programmed for Analog Integrated
Circuits. Tanner tool consists of the following Engine Machines
1. S-EDIT (Schematic Edit)
2. T-EDIT (Simulation Edit)
3. W-EDIT (Waveforms Edit)
4. L-EDIT (Layout Edit)
Using these engine tools, spice programme provides facility to the user to design &
simulate new ideas in Analog Integrated Circuits before going to the time consuming
& costly process of chip fabrication.
5.1 SCHEMATIC EDIT TOOL (S-EDIT) S-Edit is hierarchy of files, modules & pages. It introduces symbol &
schematic modes. S-Edit provides the facility of:
1. Beginning a design.
2. Viewing, drawing & editing of objects.
3. Design connectivity.
4. Properties, net lists & simulation.
5. Instance & browse schematic & symbol mode.
BEGINNING A DESIGN: It explains the design process in detail in
terms of file module operation and module [5].
Browser: Effective schematic design requires a working knowledge of the S-
Edit design hierarchy of files & modules. S-Edit design files consist of
modules. A module is a functional unit of design such as a transistor, a gate
and an amplifier.
Modules contain two components:
1) Primitives – Geometrical objects created with drawing tools.
2) Instances – References to other modules in file. The instanced module is
the original.
S-Edit has two viewing modes:
1) Schematic Mode: to create or view a schematic, we operate in schematic
mode.
2) Symbol Mode: it represents symbol of a larger functional unit such as
operational amplifier.
5.2 T-SPICE Pro Circuit ANALYSIS Let’ s have an introduction to the integrated components of the T- Spice Pro
circuit analysis suite.
Schematic data files (.sdb) describing the circuits to be analyzed in graphical
form, for display and editing by S- Edit™ Schematic Editor.
Simulation input files (.sp) describing the circuits to be analyzed in textual
form, for editing and simulation by T- Spice™ Circuit Simulator.
Simulation output files (.out) containing the numerical results of the circuit
analyses, for manipulation and display by W- Edit™ Waveform Viewer.
5.3 CIRCUIT SIMULATOR (T-SPICE) T- Spice Pro’ s waveform probing feature integrates S- Edit, T- Spice, and W-
Edit to allow individual points in a circuit to be specified and analyzed. Let’ s
discuss a few analysis:
The heart of T-Spice operation is the input
file (also known as the circuit description,
the net list & the input deck). This is a
plain text file that contains the device
statement & simulation commands, drawn
from the SPICE circuit description
language with which T-Spice constructs a
model of the circuit to be simulated. Input
files can be created and modified with any
text editor. T-Spice is a tool used for simulation of the circuit. It provides the facility of
1. Design Simulation
2. Simulation Commands
3. Device Statements
4. User-Designed External Models
5. Small Signal & Noise Models
T-Spice uses Kirchoff’ s Current Law (KCL) to solve circuit problems. To T-
Spice, a circuit is a set of devices attached to nodes. The voltage at all nodes
represents the circuit state. T-Spice solves for a set of node voltage that
satisfied KCL (implying that sum of currents flowing into each node is zero).
In order to evaluate whether a set of node voltages is a solution, T-Spice
computers and sums all the current flowing out of each device into nodes
connected to it (its terminals). The relationship between the voltages at device
terminals and the currents through the terminal is determined by the device
model for a resistor of resistance R is
RVI /∆=
Where V∆ represents the voltage difference across the device.
Let’ s discuss a few analysis:
DC Operating Point Analysis DC operating point analysis finds a circuit’ s steady- state condition, obtained
(in principle) after the input voltages have been applied for an infinite amount
of time. The .include command causes T- Spice to read in the contents of the
model file ml2_ 125. md for the evaluation of nmos and pmos transistors .
This file consists of two. model commands, describing two MOSFET models
called nmos and pmos .For example:
.model pmos pmos
+ Level= 2 Ld=. 03000u Tox= 225. 000E- 10
+ Nsub= 6.575441E+ 16 Vto=- 0. 63025 Kp= 2.635440E- 05
+ Gamma= 0.618101 Phi=. 541111 Uo= 361.941
+ Uexp= 8.886957E- 02 Ucrit= 637449 Delta= 0. 0
+ Vmax= 63253.3 Xj= 0.112799u Lambda= 0.0
+ Nfs= 1.668437E+ 11 Neff= 0. 64354 Nss= 3.00E+ 10
+ Tpg=- 1.000 Rsh= 150 Cgso= 3.35E- 10
+ Cgdo= 3.35E- 10 Cj= 4.75E- 04 Mj=. 341
+ Cjsw= 2.23E- 10 Mjsw=. 307
ml2_125. md assigns values to various Level 2 MOSFET model parameters
for both n - and p -type devices. When read by the input file, these parameters
are used to evaluate Level 2 MOSFET model equations, and the results are
used to construct internal tables of current and charge values. Values read or
interpolated from these tables are used in the computations called for by the
simulation. Two transistors, mn1 and m1p, are defined in invert1. sp . These
are MOSFETs, as indicated by the key letter m, which begins their names.
Following each transistor name are the names of its terminals. The required
order of terminal names is: drain – gate – source – bulk. Then the model name
(nmos or pmos in this example), and physical characteristics such as length
and width, are specified. The .op command performs a DC operating point
calculation and writes the results to the file specified in the Simulate > Start
Simulation dialog. The output file lists the DC operating point information for
the circuit described by the input file.
DC Transfer Analysis DC transfer analysis is used to study the voltage or current at one set of points
in a circuit as a function of the voltage or current at another set of points. This
is done by sweeping the source variables over specified ranges, and recording
the output. A list of sources to be swept, and the voltage ranges across which
the sweeps are to take place follow the .dc command, indicating transfer
analysis. The transfer analysis will be performed as follows: vdd will be set at
2 volts and vin will be swept over its specified range; vdd will then be
incremented to 2.5 volts and vin will be reswept over its range; and so on,
until vdd reaches the upper limit of its range.
The .dc command ignores the values assigned to the voltage sources vdd and
vin in the voltage source statements, but they must still be declared in those
statements. The results for nodes in and out are reported by the .print dc
command to the specified destination.
Transient Analysis Transient analysis provides information on how circuit elements vary with
time. The basic T- Spice command for transient analysis has three modes. In
the default mode, the DC operating point is computed, and T- Spice uses this
as the starting point for the transient simulation.
The. tran command specifies the characteristics of the transient analysis to be
performed: it will last for 600 nanoseconds, with time steps no larger than 2
nanoseconds.
AC Analysis AC analysis characterizes the circuit’ s behavior dependence on small- signal
input frequency. It involves three steps: (1) calculating the DC operating point;
(2) linearizing the circuit; and (3) solving the linearized circuit for each
frequency.
vdiff sets the DC voltage difference between nodes in2 and in1 to –0. 0007
volts; its AC magnitude is 1 volt and its AC phase is 90 degrees. The .ac
command performs an AC analysis. Following the .ac keyword is information
concerning the frequencies to be swept during the analysis. In this case, the
frequency is swept logarithmically, by decades (DEC); 5 data points are to be
included per decade; the starting frequency is 1 Hz and the ending frequency
is 100 MHz. The two. print commands write the voltage magnitude (in
decibels) and phase (in degrees), respectively, for the node out to the specified
file.
The. acmodel command writes the small- signal model parameters and
operating point voltages and currents for all circuit devices
Noise Analysis Real circuits, of course, are never immune
from small, “ random” fluctuations in
voltage and current levels. In T- Spice, the
influence of noise in a circuit can be
simulated and reported in conjunction with
AC analysis. The purpose of noise analysis
is to compute the effect of the noise
associated with various circuit devices on
an output voltage or voltages as a function
of frequency. Noise analysis is performed in conjunction with AC analysis; if the .ac
command is missing, then the. noise command is ignored. With the .ac
command present, the. noise command causes noise analysis to be performed
at the same frequencies: starting at 1 Hz, ending at 100 MHz, 5 data points per
decade. The. noise command takes two arguments: the output at which the
effects of noise are to be computed, and the input at which the noise can be
considered to be concentrated for the purposes of estimating the equivalent
noise spectral density. The. print command is used to print results.
5.4 WAVEFORM-EDIT
The ability to visualize the complex
numerical data resulting from VLSI circuit
simulation is critical to testing,
understanding & improving these circuits.
W-Edit is a waveform viewer that
provides ease of use, power & speed in a
flexible environment designed for
graphical data representation. The
advantages of W-Edit includes: 1. Tight Integration with T-spice, Tanner EDA’ s circuit level simulator.
W-Edit can chart data generated by T-spice directly, without
modification of the output text data files. The data can also be charted
dynamically as it is produced during the simulation.
2. Charts can automatically configured for the type of data being
presented.
3. A data is treated by W-Edit as a unit called a trace. Multiple traces
from different output files can be viewed simultaneously in single or
several windows; traces can be copied and moved between charts &
windows. Trace arithmetic can be performed on existed tracing to
create new ones.
4. Chart views can be panned back & forth and zoomed in & out,
including specifying the exact X-Y coordinate range.
5. Properties of axes, traces, rides, charts, text & colors can be
customized.
Numerical data is input to W-Edit in the form of plain or binary text files.
Header & Comment information supplied by T-Spice is used for automatic
chart configuration. Runtime update of results is made possible by linking W-
Edit to a running simulation in T-Spice.
W-Edit saves data with chart, trace, axis & environment settings in files with
the WDB (W-Edit Database).
5.5 LAY-OUT (L-EDIT)
It is a tool that represents the masks that
are used to fabricate an integrated circuit.
It describes a layout design in terms of
files, cells & mask primitives. On the
layout level, the component parameters are
totally different from schematic level. So it
provides the facility to the user to analyse
the response of the circuit before
forwarding it to the time consuming &
costly process of fabrication. There are
rules for designing layout diagram of a
schematic circuit using which user can
compare the output response with the
expected one.
L- Edit: An Integrated Circuit Layout Tool In L- Edit, layers are associated with masks used in the fabrication process.
Different layers can be conveniently represented by different colors and
patterns. L- Edit describes a layout design in terms of files, cells, instances,
and mask primitives. You may load as many files as desired into memory. A
file may be composed of any number of cells. A file may be composed of any
number of cells. These cells may be hierarchically related, as in a typical
design, or they may be independent, as in a “ library” file. Cells may contain
any number or combination of mask primitives and instances of other cells.
Cells: The Basic Building Blocks The basic building block of the integrated circuit design in L- Edit is a cell.
Design layout occurs within cells. A cell can:
… Contain part or all of the entire design.
… Be referenced in other cells as a sub- cell, or instance.
… Be made up entirely of instances of other cells.
… Contain original drawn objects, or primitives.
… Be made up entirely of primitives or a combination of primitives and
instances of other cells.
Hierarchy L- Edit supports fully hierarchical mask design. Cells may contain instances of
other cells. An instance is a reference to a cell; should you edit the instanced
cell, the change is reflected in all the instances of that cell. Instances simplify
the process of updating a design, and also reduce data storage requirements,
because an instance does not need to store all the data within the instanced cell
— instead, only a reference to the instanced cell is stored, along with
information on the position of the instance and on how the instance may be
rotated and mirrored. There is no preset limit to the size or complexity of the
hierarchy. Cells may contain instances of others cells that in turn contain
instances of other cells, to an arbitrary number of levels (subject only to
hardware constraints).
L- Edit does not use a “ separated” hierarchy: instances and primitives may
coexist in the same cell at any level in the hierarchy. Design files are self-
contained. The “ pointer” to a cell contained in an instance always points to a
cell within the same design file. When cells are copied from one file to
another, L- Edit automatically copies across any cells that are instanced by the
copied cell, to maintain the self- contained nature of the destination file.
Design Rules Manufacturing constraints can be defined in L- Edit as design rules. Layouts
can be checked against these design rules.
Design Features L- Edit is a full- custom mask editor. Manual layout can be accomplished
more quickly because of L- Edit’ s intuitive user interface. In addition, one can
construct special structures to utilize a technology without, worrying about
problems caused by automatic transformations. Phototransistors, guard bars,
vertical and horizontal bipolar transistors, static structures, and Schottky
diodes, for example, are as easy to design in CMOS- Bulk technology as are
conventional MOS transistors.
Floor plans L- Edit is a manual floor planning tool. You have the choice of displaying
instances in outline, identified only by name, or as fully fleshed- out mask
geometry. When you display your design in outline, you can manipulate the
arrangement of the cells in your design quickly and easily to achieve the
desired floor plan.
One can manipulate instances at any level in the hierarchy, with insides hidden
or displayed, using the same graphical move/ select operations or rotation/
mirror commands that you use on primitive mask geometry.
Memory Limits In L- Edit, one can make your design files as large as one like, given available
RAM and disk space.
Hard Copy L- Edit provides the capability to print hard copy of the design. A multiage
option allows very large plots to be printed to a specific scale on multiple 8 1/
2 x 11 inch pages. An L- Edit macro is available to support large- format,
high- resolution, color plotting on inkjet plotters.
Variable Grid L- Edit’ s grid options support lambda- based design as well as micron- based
and mil- based design.
Error Recovery L- Edit’ s error- trapping mechanism catches system errors and in most cases
provides a means to recover without losing or damaging data.
L- Edit Modules … L- Edit ™: a layout editor
… L- Edit ¤ Extract ™: a layout extractor
… L- Edit ¤ DRC ™: a design rule checker
L- Edit is a full- featured, high-
performance, interactive, graphical mask
layout editor. L- Edit generates layouts
quickly and easily, supports fully
hierarchical designs, and allows an
unlimited number of layers, cells, and
levels of hierarchy. It includes all major
drawing primitives and supports 90°, 45°,
and all- angle drawing modes.
L- Edit ¤ Extract creates SPICE- compatible circuit netlists from L- Edit
layouts. It can recognize active and passive devices, sub circuits, and the most
common device parameters, including resistance, capacitance, device length,
width, and area, and device source and drain area.
L- Edit ¤ DRC features user- programmable rules and handles minimum
width, exact width, minimum space, minimum surround, non- exist, overlap,
and extension rules. It can handle full chip and region- only DRC. DRC offers
Error Browser and Object Browser functions for quickly and easily cycling
through rule- checking errors.
Chapter 6
NOISE ANALYSIS OF TELESCOPIC
CASCODE
Noise limits the minimum signal level that a circuit can process with acceptable
quality. Today’ s analog designers constantly deal with the problem of noise because it trades with power dissipation,
speed and linearity. Real circuits, of course, are never immune from small,"
random" fluctuations in voltage and current levels. In T-Spice, the influence of
noise in a circuit can be simulated and reported in conjunction with AC analysis.
The purpose of noise analysis is to compute the effect of the noise associated with various circuit devices on an output
voltage or voltage as a function of frequency. Noise analysis is performed in conjunction with AC analysis; if the .ac
command is missing, then the. noise command is ignored. With the .ac
command present, the. noise command causes Noise Analysis to be performed at
the same frequencies at 1Hz, ending at
100MHz, 5 data points per decade. Noise models take the form of frequency
dependent mean-square currents (since the underlying phenomenon are “ random” )
generates by adding a current source to the circuit for each modeled noise source. Noise sources at different points in the
circuit are uncorrelated. Noise models are available for resistors and semiconductor devices (diodes, BJTs, JFETs, MOSFETs and MESFETs). Semiconductor device
models may contain noise model parameters, which affect the size of noise sources. External model devices may also
contain noise sources. Noise analysis results can be reported with the. print
noise command. The telescopic topology has fewer noise
contributing devices, so it is a better candidate for low noise single stage OTA
[19]. The total output noise in the circuit is dominated by the input devices (M1 and M2) and the active loads at the top of the
cascade (M7 and M8). The noise contribution from cascade devices is
negligible .The principle noise sources in
the MOSFET are thermal noise and flicker noise generated in the channel. Flicker
noise in a MOSFET is usually larger than in a JFET because the MOSFET is a
surface device in which the fluctuating occupancy of traps in the oxide modulates the conducting surface channel all along the channel. The relations between the
flicker noise and the MOSFET geometry and bias conditions depend on the
fabrication process. In most cases, the flicker noise, when referred to the input, is
independent of the bias voltage and current and is inversely proportional to the
product of the act.
6.1 TYPES OF NOISE Analog signals processed by integrated
circuits are corrupted by two different types of noise: device noise and
“ environmental” noise. The latter refers to random disturbances that a circuit
experiences through the supply or ground lines or through the substrate [19].
6.1.1 THERMAL NOISE
RESISTOR THERMAL NOISE-The random motion of electrons in
a conductor introduces fluctuations in the voltage measured across the
conductor even if the average current is zero. Thus, the spectrum of thermal
noise is proportional to the absolute temperature.
Fig 6.1 Thermal noise of a resistor
As shown in Fig.6.1, the thermal noise of a resistor R can be modeled by a series voltage source, with the one-sided
spectral density
For f 0≥
where k=1.38*10 23− J/K is the Boltzmann
constant. The above equation suggests that thermal noise is white .In reality, SV(f) is
flat for up to roughly 100 THz, dropping at higher frequencies.
6.1.2 FLICKER NOISE
The interface between the gate oxide and the silicon substrate in a
( ) kTRfSV 4=
MOSFET entails an interesting phenomenon. Since the silicon crystal reaches an end at this interface, many
“ dangling” bonds appear, giving rise to extra energy states. As charge carriers
move at the interface, some are randomly trapped and later released by such energy states, introducing “ flicker” noise in the
drain current. In addition to trapping, several other mechanisms are believed to
generate flicker noise [19].
Fig 6.2 Dangling bonds at the oxide silicon surface
Unlike thermal noise, the average
power of flicker noise cannot be predicted easily. Depending on the “ cleanness” of
the oxide-silicon interface, Flicker noise may assume considerably different values and as such varies
from one CMOS technology to another. The flicker noise is more easily
modeled as a voltage source in series with the gate and roughly given by
fWLC
KVox
n12 = (1)
where K is a process –dependent constant on the order of 10 25− V 2 F.The trap
–and-release phenomenon associated with the dangling bonds occurs at low
frequencies more often. For this reason, flicker noise is also called 1/f noise.
Equation (1) does not depend on the bias current or the temperature. This is
only an approximation and in reality, the flicker noise equation is somewhat
complex.
The inverse dependence of equation (1) on W L suggests that to decrease
1/f noise, the device area must be increased. It is therefore not surprising to
see devices having areas of several thousand square microns in low-noise
applications. It is also believed that PMOS devices exhibit less 1/f noise than
NMOS transistors because the former carry the holes in a “ buried channel” ,
i.e., at some distance from the oxide-silicon interface. Nonetheless, this
difference between PMOS and NMOS transistors is not consistently observed.
Chapter 7
ANALOG LAYOUT DESIGN 7.1 LAYOUT DESIGN RULES
The physical mask layout of any circuit to be manufactured using a particular
process must confirm to a set of geometric constraints or rules, which are generally called layout design rules. These rules usually specify the minimum allowable line widths for physical objects on chip
such as metal and polysilicon interconnects or diffusion areas, minimum
feature dimensions, and minimum allowable separations between two such
features. If a metal line width is too small, for example, it is possible for the line to break during the fabrication process or
afterwards, resulting in an open circuit. If the two lines are placed too close to each
other in the layout, they may form an unwanted short circuit by merging during or after the fabrication process. The main objective of design rules is to achieve, for
any circuit to be manufactured with a
particular process, a high overall yield and reliability while using the smallest
possible silicon area. There is usually trade off between higher yield, which is
obtained through conservative geometries, and better area efficiency, which is
obtained through aggressive, high-density placement of various features on the
chip. The layout design rules, which are specified for a particular fabrication
process normally, represent a reasonable optimum point in terms of yield and
density. It must be emphasized, however, that the design rules do not represent
strict boundaries, which separate “ correct” designs from “ incorrect” ones. A
layout which violates some of the specified design rules may still result in an
operational circuit with reasonable yield, whereas another layout observing all
specified design rules may result in a circuit which is not functional and/or has
very low yield. To summarize, we can say, in general, that observing the
layout rules significantly increases the probability of fabricating a successful
product with high yield.
The design rules are usually described in two ways:
1. Micron rules, in which the layout constraints such as minimum feature
sizes and minimum allowable feature separations are stated in terms of
absolute dimensions in micrometers, or,
2. Lambda rules, which specify the layout constraints in terms of a single
pDUDPHWHU�� ��DQG�WKXV�DOORZ�OLQHDU��SURSRUWLRQDO�VFDOLQJ�RI�DOO�JHRPHWULFDO�constraints.
Lambda-based design rules were originally devised to simplify the industry-standard micron-based design rules and to
allow scaling capability for various processes. It must be emphasized,
however, that most of the sub-micron CMOS process design rules do not lend
themselves to straightforward linear
scaling. The use of lambda based design rules must therefore be handled with caution in sub-micron geometries.
The design rules define geometrical relations referring to the following four
possibilities [14]: ¾ Element width, Wmin: it is the minimum
(or the maximum) width allowed for a
given element. It avoids possibly
opening or vanishing of the element. For
example, we have a rule defining the
minimum width of the poly gate and a
rule defining the minimum size of poly-
metal contacts.
¾ Element spacing ¨:min: this is the
minimum distance between two
elements. This rule avoids shortening.
The elements can be of the same kind
(for example metal-metal) or of a
different kind. For example, we have a
rule defining the minimum distance
between two metal lines or the
minimum distance between a poly line
and unrelated diffusion.
¾ Inner overlap Win, min: is the minimum
separation between two elements that
we design one inside the other. This rule
avoids the two elements detaching. For
example, we have a rule defining the
inner overlap of the contact over or
below a metal.
¾ External extension, Wex, min: is the
minimum extension of an element
overlapping another element. This kind
of rule ensures that the two elements are
fully overlapped. For example, we use a
design rule to ensure that the poly gate
always crosses the active area.
The above four categories of design rules are specified for all the possible layers
used by technology. The above description of possible rules refers to the minimum
spacing. However, some rules require the assigned figure to be “ exact” . Therefore, excepting the latter case, the designer can exceed the minimum spacing by an extent
considered appropriate [14].
7.2 LAYOUT OF TRANSISTORS
The final step in integrated design is physical description. This consists of
defining the masks to be used for processing. An MOS transistor is achieved
by the simple overlap of two rectangles: one defining the active area and the other
defining the polysilicon gate. (Fig 7.1)
Fig 7.1 The two layers that achieve a transistor
The parts of the active area that are not protected by the gate originate the source
Poly gate
Active area
and drain, while the part protected by the gate forms the transistor channel. To ensure that the source and drain are
separated, even in presence of fabrication inaccuracies, the gate overlaps the active
area to a given extent, its value being defined by the design rules of the
technology used. The physical design is not limited to
the masks of the active area and polysilicon. When the transistor must be
realized in the well, a suitable pattern must be defined. Moreover it is necessary to arrange the connections of source, drain and gate together with the substrate and well biasing. A typical layout of a MOS transistor (sitting in the well) is shown in Fig. 7.2. It represents a pattern typical of analog circuits: the aspect ratio (W/L) of the transistor is not at a minimum, as is
usually the case for analog designs.
Fig 7.2 Layout of a p-channel transistor (inside an n-well)
The key points to consider when we draw transistor layouts are the
following:
¾ Parasitic resistances at source and drain must be kept as low as possible.
¾ Parasitic capacitances should be minimized.
¾ Matching between paired elements is very important.
Concerning the first condition, we should remember that drain and source
diffusions have a given sheet resistance. With only a few squares, we can
achieve the hundreds of ohms of resistance: even with a current as low as few
tens of� $�ZH�FDQ�KDYH�GURS�YROWDJHV�RI�PLOLYROWV��7KHUHIRUH��DV�VKRZQ�LQ�)LJ��7.2, we must use multiple contacts on the top of source and drain regions to
avoid parasitic transversal drop voltages. Designers prefer multiple contacts
placed at a minimum distance instead of using a single large contact placed at
a minimum distance instead of using a single large contact. Many contacts
placed at a minimum distance instead of using a single large contact. Many
contacts placed close to each other make the surface of metal connections
smoother than when using only one contact; this prevents micro cracks in the
metal that can be a source of failure[17].
Parasitic capacitances derive from the reverse source-substrate or drain
substrate diodes. We have just seen that this is useful in establishing good
contacts. Hence, source and drain area must be large enough to accommodate
contacts and to fulfil the design rules. However, it is possible to reduce the
source and drain area and, consequently, reduce the parasitic capacitances.
This is achieved using the layout shown in Fig. 7.3.
Fig 7.3 Interdigitized transistor
The transistor is split into a given number parts that are connected in parallel. We can see that most of the source and drain area is used doubly allowing the left and right parts of the transistors to be connected. It follows that the parasitic capacitances can be reduced up to a factor of 2.
Matching is very important when we have to design current mirrors and differential pairs. In general, bad matching produces high offset. Therefore, we have to use layouts that optimize matching. This is achieved by providing the best symmetrical conditions. Transistors with different orientation Fig. 7.4(a) match badly. Moreover, we can suffer mismatch if the current in transistors is flowing in opposite directions Fig. 7.4(b).
Fig 7.4 Badly matching transistors: a) bad orientation b) with opposite current flow
The best methods of achieving good matching are shown in Fig 7.5.We assume that the two transistors that should match have one of the terminals (source or drain) in common so that we can use the interdigitated arrangement. Each transistor is split into four equal parts; they are interleaved in two by two’ s so that for one pair of pieces of same transistor we have currents flowing in opposite directions. A final point concerns the biasing of substrate or of the well. This is a very important issue: we have to ensure that the biasing is as close as possible to the active devices. Any
noisy signal affecting the substrate or the well should be sunk by the biasing and should not affect current itself. For this reason, any possible silicon space should be used for biasing purposes.
Fig 7.5 Layout of a matched transistor pair
7.3 STACKED LAYOUT Splitting transistor in a number of fingers favors a stack arrangement and improves the layout matching. For example say in Fig 7.6 presenting the layout of a simple current mirror. The four fingers of each transistor were interleaved so that the centroid of the two transistors is one close to each other. The arrangement of the stack was AABBAABB (where A and B represent the fingers of M1 and M2 respectively). An alternative organization was ABBAABBA that lead to an identical common centroid. However, the boundary conditions are not symmetrical: two fingers of M1 establish the two boundaries while M2 has all the fingers inside the array [17,19].
The above layout strategy can be generalized for more complex cells. However, it is important to work on a design that favours the stacked approach. The transistor’ s fingers that should be laid-out on the same stack must have the same width. This is often possible that all the circuits include
Fig7.6 Layout of current mirror
transistors, which sizes are not particularly critical. A small change of the widths doesn’ t modify the performances but permits a better layout.
7.4 LAYOUT OF TELESCOPIC CASCODE AMPLIFIER
Using the techniques of analog layout as described above, the layout of Telescopic cascode amplifier is developed. The schematic of Telescopic cascode amplifier is as shown in Figure 7.7.
Fig.7.7 Telescopic Cascode single stage OTA
The circuit is divided into four stacks. The bottom-most Tail transistor (M9) is an n-type transistor .The width of the transistor is very large so it is divided into twenty fingers of equal width. The source terminal is connected to the ground, which is shown by Metal 1 .The drain is connected to the combined source terminal of the differential pair. The bias voltage VB2 is provided externally.
The second stack comprises of the Differential pair. The two transistors used are matching transistors .We are using twenty fingers, ten for each transistor. The common source terminal of differential pair is connected to the drain of Tail transistor. The drain of M1 and M2 are connected to the source of M3 and M4 respectively. The Vin+ and Vin- voltage sources are provided externally.
The third stack comprises of High Compliance Current mirror pair M3
and M4. These two transistors are given the same bias VB1 provided externally. We have used five fingers for each transistor. The final stack comprises the all p-type transistors. As their sizes are very small so they have laid down with only one finger.
The below scheme shows the possible floor planning.
E F G H
CCCCC DDDDD
ABBAABBAABBAABBAABBA
IIIIIIIIIIIIIIIIIIII
The used letters denotes transistor fingers corresponding to
A--- M1 (237.09) F--- M6 (1)
B--- M2 (237.09) G--- M7 (1)
C--- M3 (13.2) H--- M8 (1)
D--- M4 (13.2) I--- M9 (47.42)
E--- M5 (1)
The values in braces are the W/Ls of transistors. We have taken length as 10 P��)LJXUH�����VKRZV�WKH�REWDLQHG�OD\RXW��7ZR�PHWDO�OD\HUV�IDYRXU�WKH�interconnections. Only few metal crossings use metal 2.
Chapter 8
RESULTS AND DISCUSSIONS 8.1 TELESCOPIC OPERATIONAL AMPLIFIER
The telescopic operational amplifier is a high gain amplifier. The gain
achieved is 101.33 dB with unity gain bandwidth of 1.84 MHz. The phase
margin achieved is 30.41 degree. The matching in transistors is quiet good as
the offset voltage is very less i.e. 0.35 mV. The output swing is 2.62 V, which
is its limitation. The slew rate is found to be 0.63 V/ V�� 2WKHU� SDUDPHWHUV�calculated are PSRRn and PSRRp that are 101.55 dB and 101.22 dB
respectively. The common mode gain is 21.39 dB. Thus CMRR is 4.74.
8.2 HIGH-SWING TELESCOPIC OPERATIONAL AMPLIFIER
The swing limitation has been removed with almost negligible changes
in other parameters. The swing has increased to 3.42 V but now gain is 99.39
dB and GB is 1.81 MHz, which are almost same that we achieved in earlier
circuit. The phase margin is 47.5 degree. The slew rate has increased to 6.7
9� V��7KH�RIIVHW�YROWDJH�KDV� LQFUHDVHG� WR������P9��3655Q�DQG�3655S� WKDW�DUH��������G%�DQG��������G%�UHVSHFWLYHO\��7KH�SRZHU�GLVVLSDWHG�LV������ :��The CMRR is 4.7.
8.3 LAYOUT The layout of telescopic operational amplifier is developed and
simulation files are extracted. The simulations of extracted files give us the
gain of 103.5 dB with phase margin of 172.02 degree. The gain bandwidth is
�����0+]��7KH�VOHZ�UDWH�LV�IRXQG�WR�EH������9� V��2WKHU�SDUDPHWHUV�FDOFXODWHG�
are PSRRn and PSRRp that are 102.5 dB and 102.3 dB respectively. The
common mode gain is 18.08. Thus, the CMRR is 5.72.
Chapter 9
9.1 CONCLUSION Operational amplifier is the basic building block of today’ s Analog
Electronic systems. The main bottleneck in an analog circuit is the
operational – amplifier. The design procedure is developed for Single stage
Telescopic operational amplifier. The
Net-list files generated and then simulated using T-spice
environment. We have simulated circuits for measuring ac gain
using Bode plot and have calculated the phase margin. We have
also measured PSRR positive and PSRR negative, CMRR, offset
voltage, output-swing and Slew-rate.
The development of a design equation based procedure
provides a quick and effective mechanism for directly estimating
the MOS circuit parameters of the op-amp The performance
requirements Op-amp designed with these calculated circuit values
were able to satisfy these requirements to a good extent as
evidenced by the T-spice simulations. The design equations
highlighted the principal factors affecting the performance
specifications, which made it very easy to redesign the circuit for
different sets of specifications.
The Telescopic op-amp has the inherent disadvantage of low output swing. A high-
swing, high performance Single Stage CMOS Telescopic operational amplifier is analyzed and the results are presented in
the form of design equations and procedure. The high swing of the op-amp
is achieved by employing the tail and current source transistors in the deep linear region. Trade - off among such factors as
bandwidth, Gain, Phase margin, bias voltages, output swing, slew rate, CMRR,
PSRR, power are made evident. The results of SPICE simulation are shown to agree very well with the use of our design
equations. Noise limits the minimum signal level that a circuit can process with acceptable
quality. Today’ s analog designers constantly deal with the problem of noise because it trades with power dissipation,
speed and linearity. Real circuits, of course, are never immune from small,"
random" fluctuations in voltage and current levels. In T-Spice, the influence of
noise in a circuit can be simulated and reported in conjunction with AC analysis
The physical mask layout of any circuit to be manufactured
using a particular process must confirm to a set of geometric
constraints or rules, which are generally called layout design rules.
Using the analog layout techniques of matching transistors and
stacked layout one can develop the layout of any analog circuit. A
layout of Single stage CMOS Telescopic op-amp is developed which
works satisfactorily.
9.2 FUTURE SCOPE • This is one technique of developing layout. Other techniques can also
be developed according to designer’ s ability to comprehend new
design.
• The design procedure can also be developed taking into consideration
other factors like low power etc.
