Dynamic Random Access Memory DRAM Bill Polinsky Dr - People

© Dr. Lynn Fuller, Motorola Professor

Rochester Institute of TechnologyMicroelectronic Engineering

Introduction to DRAM Technology

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ROCHESTER INSTITUTE OF TECHNOLOGYMICROELECTRONIC ENGINEERING

Dynamic Random Access Memory DRAM

Bill Polinsky Micron Technology, Boise, Idaho

Dr. Lynn Fuller Motorola Professor

Microelectronic Engineering Rochester Institute of Technology 82 Lomb Memorial Drive Rochester, NY 14623-5604 Tel (585) 475-2035 Fax (585) 475-5041 [email protected]

8-28-2001 lec_dram.ppt




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OUTLINE

•Introduction•Memory Organization•DRAM Basics•Capacitor Classification•Tantalum PentaOxide Capacitor•(Ba,Sr)TiO3 (BST) Capacitor•Single Layer Nitride Capacitor•Salicide Bridged Trench Capacitor•SOI DRAM•Future of DRAM•References




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INTRODUCTION

Read-Only Memories (ROMs) - These are used to store informationthat will not change during the life of the system. They are permanentlyprogrammed during manufacture.Nonvolatile read-write Memories (EPROM, EEPROM) - Thesedevices retain the information stored in them when the power is turnedoff. They can be erased but usually much slower than they can bewritten. The number of erase/write cycles may be limited.Dynamic Random Access Memories (DRAMs) - Information is storedas charge on a capacitor. The stored charge will eventually leak away soDRAMs must be periodically refreshed. Typically DRAMs arerefreshed every 5-50 milli seconds. One transistor one capacitor per cell.Static Random Access Memories (SRAM) - These devices storeinformation in two cross-coupled inverters. Such a memory does notneed to be refreshed. CMOS SRAM is low power. The SRAM cell requires six transistors making it fewer bits per chip than DRAM.




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MEMORY ORGANIZATION

sense amplifiers/drivers

Column decoder

Row

decoder

Word Line

Storage Cell

Bit Line

Input/output

ColumnAddress bits

Row AddressBits

A0.AJ

20

2J




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DRAM BASICS

•A DRAM memory cell is formedwith one transistor and onecapacitor. Referred to as a 1T1Ccell.•Storing a logic ONE requires avoltage of +Vcc/2 across C1.•Storing a logic ZERO requires avoltage of -Vcc/2 across C1.•Various leakage paths cause thecapacitor to slowly deplete charge.•The capacitor needs to be refreshedperiodically, which makes theDRAM dynamic rather than static.•Typical refresh rates are every5-50 msec




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TWO DRAM STORAGE CELLS

WL0 WL1

Vcc/2

Bit




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OPEN DIGITLINE MEMORY ARRAY

The memory bit transistor gate isconnected to a word line (column)

A memory array is a quantity of1T1C cells along a given digit line(row). None of the cells connectedto a given digit line share acommon word line.

Only one word line at a time isactivated.

WL0

D0

D1

WL1 WL3WL2

Vcc

/2

Vcc

/2

Vcc

/2




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READ OUT AMPLIFIER

WL0

D0

D1

WL1 WL3WL2

Vcc

/2

Vcc

/2

Vcc

/2Vref

D0 Out

D1 Out

C1

If a 1 was stored in C1 then when WL0goes high D0 will go higher. If it ishigher than Vref D0 Out will be high.The problem is that the voltage on D0only increases a small amount becausethe capacitance of the digit line is largecompared to C1




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SIMPLE ARRAY

•Accessing the DRAM cell resultsin charge sharing between thecapacitor and the digitline.•This causes the digitline voltageto either increase or decrease for aONE or ZERO on the capacitor.•This causes a differential involtage between two digitlines, D0and D0*.•The voltage difference can be“sensed” and the correct logic levelcan be determined.




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SENSE AMPLIFER DETAILS

Digit LineReferenceDigit Line

C0

Vdd/2

Vdd

Vdd/2

φs

φs

φp

Q9Q8

Q5

Q6

Q2Q1

Q3 Q4

Q7 is turned on withsignal φp precharging the two digit lines to Vdd/2

Q7

Note: the memory isorganized into two arraysso that one can be usedas the reference for the other. (with basicallyidentical digit line capacitance)

WL0

Vdd/2

D0D0*




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SENSE AMPLIFIER DETAILS

Φs goes high and the data in the selected memory cell is sensed.The word line WL0 goes high and the charge on selected capacitorC0 is shared with the capacitance of the digit line D0. If a “1” wasstored in C0 the voltage on D0 will initially be a little higher thanVdd/2. The voltage on the reference digit line will initially beVdd/2. The crosscoupled inverters amplify these starting voltageand bring the digit line D0 to Vdd and D0* to zero volts. Thecapacitor C0 is recharged (refreshed) at the same time it is read.

If a “0” was stored in C0 the voltage on D0 will initially be a littlelower than Vdd/2. The crosscoupled inverters bring D0 to zero volts, refreshing C0 and providing a one for an output on D0*.




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SENSE AMPLIFER WAVEFORMS

D0

D0*

φs

φs




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LAYOUT OF BASIC CELL

Eight Cells - Each red ovalshape is a capacitor. Theblue poly wordlines formtransistors between thegreen rectangularconnection to the digitline.




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BURIED CAPACITOR CELL

•Digitline (bitline) is made ofAluminum with a Tungsten plug.•Capacitor top and bottom plate ismade from poly-silicon.•The top plate (poly 3) forms the cellplate and is shared by all capacitors.•The capacitor shape can be arectangle or concentric cylinders.•The ONO dielectric is optimized toachieve low leakage and maximumcapacitance.•The ONO must be able to handlefields caused by the maximumDRAM operating voltage. For thisreason the cell plate is biased at+Vcc/2.




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BURIED DIGITLINE CELL

•This type of cell is called a COB(Capacitor over Bitline) or burieddigitline configuration.•The digitline is very close to thesurface of silicon, making thedigitline pitch small and thecontact is easier to produce.•However, the capacitor contact isvery hard to produce because thecontact has to be cut in betweenthe digitlines, which are at nearminimum pitch to begin with.




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BURIED DIGITLINE CELL




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TRENCH CAPACITOR CELL

•Trench capacitors are formed byetching deep holes into the siliconsubstrate.•The trench is coated with a dielectricmaterial, eg. ONO or Nitride.•The storage node if formed bydepositing doped poly-silicon into thetrench.•Contact from the transistor to thecapacitor is done with a conductivestrap.•The substrate serves as a common nodefor all of the capacitors, which preventsthe use of a +Vcc/2 bias.•For Gbit and beyond DRAMs thetrench will be too difficult to etch, theaspect ratio will be too great foracceptable capacitance.

•Advantage of the trench capacitor isthat the DRAM structure will have lesstopology than other cell structures.




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CAPACITOR AREA AND REQUIRED CAPACITANCE

Shows the trend of capacitor area andrequired capacitance. •Thermally robust Ta2O5

(Tantalum PentaOxide) has beenattractive for DRAM capacitors.•Ta2O5 has a dielectric constantin the range of 16-40.•Ta2O5 has good conformal stepcoverage when deposited usingCVD.•(Ba,Sr)TiO3 Is AnotherAlternative Capacitor.




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TANTALUM PENTAOXIDE CAPACITOR

Capacitance of more than 90fF/celland leakage current less than 2x10^-15 A/cell is obtained by applying aWNx/poly-si top electrode with arugged poly-si surface (projectionarea = 0.4um) with an effectiveoxide thickness of 3.5 nm.

As deposited Ta2O5 is known to be very leaky. The leakage current isreduced by annealing the film in UV-O3 at 300 C and dry O2 at 800 C.Annealing in O2 forms a thin layer of SiO2 over the poly and provides abarrier to carrier flow. The ozone provides atomic oxygen to fillvacancies in the film.




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BIAS OPTIMIZATION FOR TANTALUM PENTAOXIDE

At Vcc of 3.3 volts the maximum leakage current can be reduced by twoorders of magnitude when Vp is changed from 1.65 volts (conventionalVp=Vcc/2) to a Vp of 1.0 volts.

By using a bias Vp = 1.0 volts, Vspr is the maximum Vcc that can beapplied for a given current magnitude.

Using a bias optimization scheme cangreatly improve the quality of thecapacitor by reducing leakage currentat a given supply voltage, VCC.




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EPITAXIAL (Ba,Sr)TiO3 CAPACITOR

As well as a high dielectric constant, low leakage current in very thincapacitors with a epitaxial (Ba,Sr)TiO3 dielectric.To achieve this superior performance the film is because of theheteroepitaxial technique used to deposit the film.

Their superior performance is attributedto the appropriate lattice deformationcaused by the lattice constant mismatchbetween BSTO and SRO and thecleanliness of their hetroepitaxialinterfaces.




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HETEROEPITAXY

Their superior performance is attributed to the appropriate lattice deformation caused bythe lattice constant mismatch between BSTO and SRO and the cleanliness of theirhetroepitaxial interfaces.Heteroepitaxial growth is classified as the growth on dissimilar materials. Whichmeans that the material being grown has a lattice mismatch from the underlyingmaterial.The heteroepitaxial growth in this case of (Ba,Sr)TiO3 thin film is classified asincommensurate growth.Incommensurate growth is the production of thick layers that are not lattice matched tothe substrate. The misfit between the two crystals must be accommodated by defects ator near the interface.

In this case, the mismatch is a plus to the capacitor, as a result of comparision betweenepitaxial and polycrystalline capacitors with identical dielectric thicknesses, themismatched induced lattice deformation is highly effective to increase the dielectric

constant of the film.




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SINGLE LAYER NITRIDE CAPACITOR

Key Technology for increasingcapacitance for the Gbit era trenchcapacitors is a thinner dielectric filmwith low leakage current.

SiN is promising for material that haslow leakage current and the potentialto be thinned further and it has a highdielectric constant.




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SINGLE LAYER NITRIDE CAPACITOR

Calculated Voltage based on ideal films

Actual Voltage based on actual films

A novel SiN-CVD technology using SiCl4-NH3 system was developed instead ofconventional SiH2Cl2-NH3 system toovercome this subject.

SiN Film has a greater potential for thicknessreduction because of its higher dielectricconstant. Nitride ε~7 Whereas SiO2 ε~4-5.

However, the actual leakage current in SiNfilm is larger than in Si02 films because ofbonds introduced in deposition.




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SINGLE NITRIDE LAYER CAPACITOR BY NOVEL CVD

In order to improve the SiN film quality, the Si-H bond density has beenreduced using this method; SiCl4-NH3 (TCS-SiN) as reactants.

SiCl4 has no Si-H molecular bond in itself.

SiCl4 can react with NH3 at room temperature and form Si(NH2)4 orSi(NH)2 molecule, which has no Si-H bond.A FT-IR measurement was done to findout how many Si-H bonds are present inthe film. As shown in the figure, the Si-Hbond that usually exists in conventionalNitride deposition cannot be detected.




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SINGLE NITRIDE LAYER CAPACITOR BY NOVEL CVD

This new Si-N (TCS) shows superiorelectrical characteristics over theconventional DCS Nitride deposition.At the required leakage current, theTCS capacitor can handle ~2 voltscompared to the conventional ~1.3volts with a dielectric thickness of4.63 nm.

The equivalent oxide thickness is can be reduced below 4 nm whichis a promising capacitor dielectric for the Gigabit era and beyond.




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SALICIDE BRIDGED TRENCH CAPACITOR

The connection from capacitor to thetransistor can be made with a salicidebridge on top of the conventionalDrain connection.

The salicide bridge provides a lowseries resistance path for currentto flow through.

The salicide bridge does not increasethe leakage current in the trenchcapacitor which is always a concern.When introducing new materials.




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SALICIDE BRIDGED TRENCH CAPACITOR

The DSS process makes it possible tofabricate a self-aligned buried oxide collarand a salicide bridge over a thick oxidecollar.




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PATTERN BONDED SOI DRAM

Previous reports of SOI DRAMdescribed the limitation of scalingdown due to short channel effects ofthe PMOS, and the LOCOSisolation scheme.

The process described here patternbonded SOI (PBSOI) reduces negativeeffects, and reduces gate delay andleakage is just as good as conventionalBulk type DRAMs.

The PBSOI will enable higher speedDRAMs for future DRAM generations.




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PATTERN BONDED SOI DRAM




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PATTERN BONDED SOI




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FUTURE OF DRAM

With increasing density of DRAM a trench type capacitor will not suffice do toincreasing aspect ratio of trenches needed to have enough capacitance. The etch willjust become impossible.

This will force the industry to use Capacitorover bitline (COB) schemes. With COB thecapacitor size can increase by increasing sizein the vertical direction, which itself posesmany etch and planarization challenges. Inthe near future the dielectric will be Ta2O5thin films due to its high dielectric constantand good film quality for small filmthickness.




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FUTURE OF DRAM

DRAM will move towards SOI formation to minimize floating bodyeffects and minimize latchup.

DRAM will become less of a commodity with the introduction andmanufacturability of embedded DRAM, that is DRAM on the samesubstrate as logic and microprocessors.




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REFERENCES

1. “State-of-the-art and future trends in DRAMS”, Microelectronics Journal 27 (1996),C.G. Hwang, S.I. Lee and M.Y. Lee

2. “DRAM Plate Electrode Bias Optimization for Reducing Leakage Current in UV-O3and O2 Annealed CVD Deposited Ta2O5 Dielectric Films”, Transactions on ElectronDevices, Vol. 42, No. 10, Sudhir K. Madan.

3. “Single Layer Nitride Capacitor Dielectric Film and High Concentration DopingTechnology for 1Gb/4Gb Trench-Type DRAMs”, IEDM 97-265, Shigehiko Saida,Tsutomu Sato, Ichiro Mizushima, Yoshio Ozawa and Yoshitaka Tsunashima.

4. “Epitaxial (Ba,Sr)TiO3 Capacitors with Extremely High Dielectric Constant forDRAM Applications”, IEDM 97-257, N. Fukushima, K. Abe, M. Izuha, T. Schimizuand T. Kawakubo.

5. The Science and Engineering of Microelectronic Fabrication, Stephen Cambell p.355.




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REFERENCES (CONTINUED)

.6. “A Salicide-Bridged Trench Capacitor with a Double-Sacrificial-Si2N4 Sidewall

(DSS) for High-Performance Logic-Embedded DRAMs:, IEDM 97-37, M.Togo,S.Iwao, H.Nobusawas,M.Hamada,K.Yoshida,N.Yasuzato and T.Tanigawa.

7. “A New Planer Stacked Technology (PST) for Scaled and Embedded DRAMS”,IEDM 1996, S.P. Sim, W.Lee,Y.Ohu,H.Choe, J.Kim, H. Ban, I.Kim, Y. Chang, Y.Lee, H.Kang, U.Chung, C. Choi and C.Hwang.

8. “Advanced Integration Technology for a Highly Scalable SOI DRAM with SOC”,IEDM 96, Il-Kwon Kim, Woo-Tag Kang, Joon-Hee Lee, Sunil Yu, Sang Lee, KyeheeYeom.




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