Dynamic Data Stability in Low-power SRAM Design

Dynamic Data Stability in Low-power SRAM Design

M. Sharifkhani, Member, IEEE, S. M. Jahinuzzaman, Student Member, IEEE, M. Sachdev, Senior Member, IEEE

Electrical & Computer Engineering, University of Waterloo 200 University Avenue West, Waterloo, ON, N2L 3G1, Canada

Abstract- SRAM cell stability measurement is traditionally based on static criteria of data stability requiring 3 coincident points in butterfly curves. We introduce dynamic criteria of stability for the cell knowing that the cell operates in a dynamic environment. It reveals that the true noise margin of the cell can be made considerably higher than the SNM once the cell access time is sufficiently shorter than the cell time-constant. This behavior enables enhancing SRAM yield as well as reducing cell operating voltage without compromising reliability. A 40Kb SRAM designed using SVGND scheme exploits the dynamic behavior of the cell in order to increase the stability and reduce the static and dynamic power consumption. The SRAM unit realized in 0.13µm CMOS consumes 702uW at 100MHz during write operation and offers a 27pA/Cell leakage current.

I. INTRODUCTION Holding one bit of data is the main purpose of an SRAM cell. An SRAM cell has this ability if it satisfies the static criteria of data stability (d-stability). That is, the feedback and feedforward DC transfer characteristics of the comprising inverters coincide in three points. In other words, there are three separate DC solutions for the circuit: two stable solutions and one meta-stable solution. This criteria has governed the realm of SRAM design since 1968 when it is proposed by Hill [1]. Static Noise Margin, (SNM) is a well known measure for the data stability in an SRAM cell. Fig.1 shows the logic behind derivation of SNM. For a noise source, SNM is defined as the amount of DC noise that if applied to the cell, it no longer satisfies the static criteria for data stability [2]. A pair of symmetric series, DC noise sources has been widely used to characterize the SNM because it models the widespread, time invariant non-idealities such as mismatch between the comprising inverters.

The static criteria of data stability is useful for a static circuit. An SRAM cell, however, has two distinct circuit topologies during its access time and non-access time, from DC perspective. Consequently, the SNM is conventionally derived for either one of these two configurations, separately. Since the SNM during the access time is the worst, it is usually referred to as the SNM of the cell. Therefore, the conventional notion of SNM is based on two concept (a) a static criteria for data stability and (b) static noise sources. Recently, there have been reports that the dynamic behavior of the transistors should be taken into account and there are some circuit applications for that matter in the design [3, 4, 5] and test of SRAM circuits [6].

+_

+_

Fig. 1. The criteria for data stability and derivation of SNM based on that

BLBL

VH

Virtual ground(VL)

Cg

Cg

Cgd

Cdg

Cgs

Capacitances that are affected by change of cell virtual ground voltage

VH

VH

VL

VL

VH

VL

M1 M2

M3 M4

M5 M6

WL

Leaking transistor in the retention mode

WL

AB

VDD VDD

VSSVSS

Fig.2. The internal node voltages of an SRAM cell as its state variables, the

capacitance seen from the virtual ground of the cell The paper revisits the concept of SNM considering the

dynamic behavior of transistors. The paper introduces new criteria for data stability in an SRAM cell knowing that the cell operates in a dynamic environment. The definition of the dynamic criteria for d-stability which is a superset to the static criteria of d-stability reveals a different noise margin for the same static noise sources that is conventionally used.

Furthermore, we present a segmented virtual grounding scheme which trades the additional noise margin to gain lower power consumption by a special way of varying the cell virtual ground without compromising the d-stability.

The paper consists of the following sections. Section II provides an analysis of the dynamic behavior of the cell and presents the dynamic criteria for data stability. In addition the section shows the simulation results. Section III presents segmented virtual grounding (SVGND) architecture that exploits the benefits of dynamic data stability to offer a low power design. Section IV shows the measurement results and

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makes a comparison with the recently reported low-power schemes. Section V concludes the paper.

Fig.3. Location and RoC of the DC solutions of the equations describing the dynamic behavior of the cell in retention in the state space and the trajectory

of the state variable for arbitrary initial conditions in the state space

II. DYNMIC DATA STABILITY An SRAM cell has distinct properties that have to be taken

into account in the d-stability analysis. First of all, the cell is a non-linear circuit since it is based on non linear components, the transistors. Secondly, the cell goes to access and non access (retention) modes, thereby showing a time varying circuit as well. Therefore, a non-linear, time variant analysis is required to describe the behavior of the cell.

The analysis can be made using state space equation describing the state variables of the cell. State space variables of VA and VB can describe the state of the cell (See Fig.2). To begin, we are interested in finding the behavior of the cell in the retention mode. That is because the cell may remain in the retention mode for an indefinitely long time. Also, we are interested in characterizing the behavior of the cell in the subthreshold region (VH-VL<VT) for low-power applications. The analysis, however, can be extended to any voltage setting as will be shown later. The state space equations presented in differential equation (DE) Eq.1 describe the behavior of the cell in the retention mode in which Ii represents the current through transistor Mi(in Fig.2):

3 13

4 21

(1 ),

(1 )

H B Tp H A

t t

B L Tn A L

t t

V V V V VA

nV nVop

V V V V VB nV nV

on

dVC I I I I e edtdVC I I I I e edt

− − −−

− − −−

= − = − = − = −

(1)

Similar equations can be driven for I4 and I2. In Eq.1, C is the parasitic capacitor at each of the nodes A and B.

Solving the DE of Eq.1 in the two dimensional state space for a statically d-stable cell in retention mode reveals the type of DC solutions of the circuit. The DC solutions are indicated in the state space shown in Fig.3. The stable solutions associated with logic ‘1’ or ‘0’ (S1 and S0) are asymptotically stable and they have a region of convergence (RoC.) The RoC is the area where the state of the cell is attracted toward the corresponding stable point. Shown in Fig.4, the behavior of the state of the cell in the retention mode is similar to the shadow of a ball on the XY-surface, when a ball is located on a saddle.

Fig.4. The state of the cell behaves similar to the shadow of a ball on the 2-

dimensional state space when the ball is on a saddle shaped surface

Fig.5. The DC solution of a statically d-unstable accessed cell overlaid on the

DC solution of the cell in retention, and the trajectory of three potential periodic solutions when the cell alternates between accessed and retention

When the cell goes to the accessed mode, the access

transistors also affect VA and VB. Therefore, a different set of DE describes the behavior of the accessed cell:

, ( , )A Ba A B

dVC I V V

dt= (2)

This DE provides a different set of stable solution(s) associated with the accessed cell in the state space.

The dynamic stability analysis is especially important if the cell is statically d-unstable in the accessed mode. In that case, there will only be one DC solution for Eq.2, namely Su in Fig.5. The RoC of this solution covers the entire state space. If the cell goes to the accessed mode from retention mode, the state of the cell moves towards the only DC solution of the accessed cell, Su, regardless of the original logic state (S1 or S0) in the retention mode. Depending on the time constant of the cell, it takes some time for the state of the cell to move away from its initial condition on S1 or S0 and settles on Su. If the cell returns to the retention mode, Eq. 1 governs the cell again. Therefore, the state of the cell is attracted towards one of the logic states depending on the location of the state of the cell on the state space. Hence, if the cell access time is short enough such that the state of the cell does not escape from the RoC of the original logic state, the cell is able to recover its original logic state and remains data stable even though it is d-

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unstable from static perspective in the accessed mode. S

NM

D (

mV

)

Fig.6. Expansion of SNM to SNMD as the cell, of Fig.2, enters subthreshold

region and the cell access time (Ta) is finite The mathematical analysis of Eq.1 and 2 is complex and

beyond the scope of this paper. Interested readers can find more on analysis of these equations in [6] where we have shown that the worst case scenario for d-stability occurs when the cell is periodically accessed. Also, we have shown that the criteria for dynamic d-stability is that there exist at least three periodic solutions for the nonlinear periodic time variant differential equations describing the periodically accessed cell. These periodic solutions are convergent too. Therefore, for any arbitrary initial condition, the state of the cell will converge to one of these periodic solutions. This property can be used to perform dynamic d-stability simulations.

The theory of dynamic data stability indicates that the cell noise margin can be enhanced if the cell access time is kept below the cell time constant. Fig.6 shows the simulated results of the dynamic SNM (SNMD) when a typical cell is accessed periodically under different cell access times (Ta) for a constant operational speed (100MHz). In this simulation, the cell low voltage (VL) is elevated to reduce the cell supply voltage (VH-VL of Fig.2). Clearly, when the cell enters the subthreshold region, the cell time constant is lower so the cell can satisfy the dynamic criteria of data stability under a higher static noise for a typical cell access time, providing a higher noise margin. Furthermore, the reduction of the cell access time enhances the noise margin, particularly when the cell nears the subthreshold region.

III. A LOW POWER SRAM MODULE BASED ON SEGMENTED VIRTUAL GROUNDING (SVGND)

The extra SNM offered by the dynamic stability of the cell can be traded with power consumption in advanced SRAM architectures. In this section, we employ this feature in conjunction with the SVGND architecture that we proposed in [7]. Cell supply voltage/ground variation schemes are effective to reduce the power consumption or extend the d-stability. However, they incur significant dynamic power overhead since it affects the internal capacitor of the cells in an entire block or column (See Fig.2.) A 40Kb SRAM is implemented based on SVGND where the number of cells that go under virtual ground variation are limited significantly. The architecture accommodates multiple words per row.

Fig.7 shows the details of the SRAM block. A segment consists of a set of 8 cells on the same column with a shared

segment virtual ground (SVG). For a segment, a virtual ground switch (SW) connects the SVG to the column virtual ground (CVG) which is a high metal layer node shared between all SWs on the same column. If the SW of a segment is activated by segment select signal SS of that segment, the SVG of the segment is connected to the CVG of the column; otherwise, the virtual ground of the segment keeps its nominal voltage, VL=0.5V. The SS of a segment is generated by the pre-decoder of the row decoder at no additional hardware cost and is activated only if a cell in the segment is accessed for read or write operation. Conversely, the CVG is lowered to 0V only if one of the cells on the column is to be read. CVG of unselected columns remain at VL. This makes the accessed cells on the unselected columns to go to accessed retention mode (AR-mode) with a weak drive transistor due to a high source voltage. Therefore, in both read and write operations, the unselected bitlines do not discharge. In addition, the cell ground switching is restricted to only 8 cells per bit.

Fig.7. The architecture of the segmented virtual grounding based on segmentation of a column

The bodies of all PMOS and NMOS transistors are connected to 1.2V and 0V at all times. The cell VH and VL are 0.9V and 0.5V, respectively in retention mode leaving all transistors in subthreshold region and offering an SNM of 130mV in retention mode. Owing to the reverse body bias on all transistors, the cell leakage current drops by 16 times. The cell is accessed by a wordline voltage of VWL=1.1V. This offers a 60% higher write noise margin since the cell is in subthreshold region. With bitlines precharged at VH, a bitline voltage swing of 0.4V has proven to be sufficient for successful write operation in the experiment. During the read operation, the CVG of the selected columns drops to 0V which results in the SVG drop of the segments containing the selected cells. The amplified Vgs of the drive transistors provides a bitline discharge of less than 2 nS. The AR-mode cells will remain in the same original voltage setting which

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keeps the drive transistor in subthreshold, so the unselected bitline do not discharge and the cell has a long time constant.

Accessing a cell operating in the subthreshold region jeopardizes the data stability of the cell. Recently published subthreshold techniques in [8, 9] employ additional transistors or wordlines to save the data of the subthreshold cell when it is accessed. In the proposed scheme, the data stability of the AR-mode cells is guaranteed by exploiting the concept of dynamic data stability that is discussed in Section II. In this architecture, access time of less than 2 ns is achievable, owing to the high Vgs of the drive transistor of the cells to be read. Such a short access time offers an SNM increase of up to 60%. Considering the Gaussian distribution of the threshold voltage the cell transistors, such an increase in SNM reduces the probability of failure significantly.

IV. MEASUREMENT RESULTS Fig.8 shows the silicon chip micrograph. The unit is divided into four similar SRAM blocks. The area overhead of the scheme is about 8% which is due to the SW for each segment. The unit consumes 702µW during the write operation when it runs at 100MHz. The leakage current of each cell in such condition is about 27pA/cell at room temperature. The read power consumption is 630µW at the same frequency.

Table.1 draws a comparison between the proposed scheme and the recently reported subthreshold schemes. It can be seen that the proposed scheme offers a smaller area overhead and a higher speed compared to the reported schemes. The higher speed is due to the normal voltage setting of the cells to be read. Obviously, the size of the SRAM, the word size and the way the unit is broken down into multiple blocks affect the dynamic energy consumption. Yet, it can be seen that the proposed scheme offers the lowest energy/operation for a unit memory size, despite its regular 1.2V voltage requirement. This power reduction is mainly due to the fact that the non selected bitlines do not discharge in read or write operation in the proposed scheme and the decoders/sense amp and write drivers are shared for 4 words on a row.

IV. CONCLUSION

Introducing the dynamic criteria for d-stability in an SRAM cell was the main objective of this paper. It is shown that in a dynamic environment, in order to remain data stable the cell should offer three periodic solutions in the two dimensional state space once it is accessed periodically. Furthermore, it is shown that these solutions are convergent. This property can be used in the simulation method for the verification of the criteria. The static noise margin was revisited in light of the dynamic criteria for data stability. Simulation results suggests that if the cell time constant is longer than the cell access time, the cell offers a higher noise margin compared to the conventional SNM. The effect of cell access time on the SNMD was studied as well.

A 40Kb SRAM is designed based on SVGND scheme. The scheme exploits the dynamic behavior of the cell to increase the stability and to reduce the static and dynamic power consumption. The scheme offers multiple words per row.

However, the non-selected cells on the accessed row remain in the subthreshold region. Therefore, they do not discharge the bitline which saves power. The stability of these cells is extended by reducing the cell access time to less than 2nS. The cell to be read goes to normal voltage setting which provide a sufficient bitline discharge during the cell access time. This architecture offers the benefit of regular speeds while keeping the cells of the array, with the exception of cells to be read, in the subthreshold region. Also, the scheme offers a significantly smaller area overhead compared to other subthreshold schemes.

Fig.8. Silicon micrographs and associated layout of the 40Kb SRAM

Table.1 Figure This work [8] [9] Tech. (CMOS) 0.13µ 65nm 0.13µ Size 40Kb 256Kb 2Kb Freq. (MHz) 100 0.025 1 Leakage (pA/Cell) 27 25 250 Area Overhead 8%, 6T N/A, 8T 42%, 6T Energy/Op. (pJ) 7 160 1 Energy/Op./bit (pJ/bit) 175µ 625µ 500µ Min. Cell Supply (V) 0.4 0.35 0.2 Configuration Mulpl-word Single-word Mulpl-word

REFERENCES

[1] C. F. Hill, “Noise margin and noise immunity of logic circuits,”. Microelectron., 1968, vol. 1, pp. 16-21. [2] J. Lohstroh, E. Seevinck, J. de Groot, “Worst-case static noise margin criteria for logic circuits and their mathematical equivalence,” IEEE Journal of Solid-State Circuits, Volume 18, Issue 6, pp. 803 – 807, Dec 1983. [3] M. Sharifkhani and M. Sachdev, “A low power SRAM architecture based on segmented virtual grounding,” Proceedigs of IEEE Symposium on Low-Power Electronics and Design (ISLPED), 256-261, Oct. 2006. [4] M. Khellah et al., “Wordline and bitline pulsing schemes for improving SRAM cell stability in low-vcc 65nm CMOS designs,” IEEE Symp. on VLSI Circuits Digest of Tech. Papers, pp. 9–10, 2006. [5] H. Pilo, et. al, “An SRAM design in 65nm and 45nm technology nodes eaturing read and write-Assist circuits to expand operating voltage” Symposium on VLSI Circuits, Digest of Technical Papers. 15-17, 2006. [6] M. Sharifkhani, S. M. Jahinuzzaman, M. Sachdev “Dynamic data stability in SRAM cells and its implications on data stability tests,” Proceedings of the IEEE International Workshop on Memory Test and Design Technology (IEEE MTDT), pp. 55-64, 2006. [7] M. Sharifkhani, M. Sachdev, “Segmented virtual ground architecture for low-power embedded SRAM,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 15, pp. 196 - 205, Feb. 2007. [8] N. Verma and A. Chandrakasan, “A 65nm 8T sub-Vt SRAM employing sense-amplifier redundancy,” IEEE ISSCC Digest of Tech. Papers, pp. 328–329, Feb. 2007. [9] B. Zhai et al., “A sub-200mv 6T SRAM in 0.13u CMOS,” IEEE ISSCC Digest of Tech. Papers, pp. 332–333, Feb. 2007.

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Dynamic Data Stability in Low-power SRAM Design