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SystemVue - DVB2 Baseband Verification Library

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SystemVue 2010.072010

DVB2 Baseband Verification Library


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DVBS2_BCHEncoder Part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 DVBS2 BCHEncoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

DVBS2_BitInterleaver Part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 DVBS2 BitInterleaver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

DVBS2_LDPCEncoder Part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 DVBS2 LDPCEncoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

DVBS2_Mapper Part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 DVBS2 Mapper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

DVBS2_CRCEncoder Part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 DVBS2 CRCEncoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

DVBS2_MergerSlicer Part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 DVBS2 MergerSlicer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

DVBS2_PLFramer Part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 DVBS2 PLFramer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

DVBS2_PLScrambler Part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 DVBS2 PLScrambler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

DVBS2_Demapper Part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 DVBS2 Demapper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

DVBS2_FrameSync Part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 DVBS2 FrameSync . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

DVBS2_LDPCDecoder Part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 DVBS2 LDPCDecoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

DVBS2_PLDemuxFrame Part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 DVBS2_PLDemuxFrame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

DVBS2_Receiver Part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 DVBS2 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

DVBS2_Source Part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 DVBS2 Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

DVBT2_P1_Gen Part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 DVBT2 P1 Gen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

DVBT2_P2_Data_Gen Part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 DVBT2 P2 Data Gen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

DVBT2_Source Part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 DVBT2 Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

DVBS2_BBScrambler Part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 DVBS2 BBScrambler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58


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DVBS2_BCHEncoder PartCategories: FEC Encoding (dvb2ver)

The models associated with this part are listed below. To view detailed information on amodel (description, parameters, equations, notes, etc.), please click the appropriate link.

Model Description

DVBS2_BCHEncoder (dvb2ver) BCH encoder for DVB-S2

DVBS2 BCHEncoder

Description: BCH encoder for DVB-S2Domain: UntimedC++ Code Generation Support: NOAssociated Parts: DVBS2 BCHEncoder Part (dvb2ver)

Model Parameters

Name Description Default Units Type RuntimeTunable

FecFrame frame mode: Normal, Short Normal Enumeration NO

CodeRate code rate for LDPC: 1/4, 1/3, 2/5, 1/2, 3/5, 2/3, 3/4,4/5, 5/6, 8/9, 9/10

1/4 Enumeration NO

Input Ports

Port Name Signal Type Optional

1 input int NO

Output Ports


2 output int NO

Notes/Equations

This model is to implement the outer channel coding: BCH encoder. Each firing, N bch1.

bits output tokens are generated and K bch bits input tokens consumed.

The FEC sub-system shall perform outer coding (BCH), Inner Coding (LDPC) and Bit2.interleaving. The input stream shall be composed of BBFRAMEs and the outputstream of FECFRAMEs. Each BBFRAME (K bch bits) shall be processed by the FEC

coding subsystem, to generate a FECFRAME (N ldpc bits). The parity check bits


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(BCHFEC) of the systematic BCH outer code shall be appended after the BBFRAME,and the parity check bits (LDPCFEC) of the inner LDPC encoder shall be appendedafter the BCHFEC field, as shown in the figure below.

The tables below give the FEC coding parameters for the normal FECFRAME (nldpc =3.64 800 bits) and the short FECFRAME (nldpc = 16 200 bits).

In this model, A t-error correcting BCH (N bch, K bch) code shall be applied to each4.

BBFRAME (K bch) to generate an error protected packet. The BCH code parameters

for nldpc = 64 800 and for nldpc = 16 200 are given in tables below. The generatorpolynomial of the t error correcting BCH encoder is obtained by multiplying the first tpolynomials in table 6a for nldpc = 64 800 and in table 6b for nldpc = 16 200.


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BCH encoding of information bits m = (m Kbch-1, m Kbch-2,..., m 1, m 0) onto a5.

codeword: c = (m Kbch-1, m Kbch-2,..., m 1, m 0, d Nbch-Kbch-1, d Nbch-Kbch-2,..., d 1, d 0) is achieved as follows:

Multiply the message polynomial m(x) = m Kbch-1 x Kbch-1 + m Kbch-2 x Kbch-2 +

... + m 1 x + m 0 by x Nbch-Kbch

Divide x Nbch-Kbch m(x) by g(x), the generator polynomial. Let d(x) = d Nbch-

Kbch-1 x Nbhc-Kbch-1 + ... + d 1 x + d 0 be the remainder.

Set the codeword polynomial c(x) = x Nbch-Kbch m(x) + d(x)

References

ETSI EN 302 307, "Digital Video Broadcasting (DVB); Second generation framing1.structure, channel coding and modulation systems for Broadcasting, InteractiveServices, News Gathering and other broadband satellite applications" Version 1.1.2,Jun. 2006.


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DVBS2_BitInterleaver PartCategories: FEC Encoding (dvb2ver)


Model Description

DVBS2_BitInterleaver (dvb2ver) Bit interleaver for DVB-S2

DVBS2 BitInterleaver

Description: Bit interleaver for DVB-S2Domain: UntimedC++ Code Generation Support: NOAssociated Parts: DVBS2 BitInterleaver Part (dvb2ver)

Model Parameters



ModType modulation type: QPSK, 8PSK, 16APSK, 32APSK QPSK Enumeration NO


1/4 Enumeration NO

Direction Interleaver or Deinterleaver: Interlv, Deinterlv Interlv Enumeration NO

Input Ports


1 input real NO

Output Ports


2 output real NO

Notes/Equations

This model is to implement the bit level interleaver or deinterleaver for 8PSK,1.16APSK, and 32APSK modulation formats. For QPSK, the interleaer is disabled andthe output is directly connected with the input. Each firing, N ldpc bits output tokens

are generated and N ldpc bits input tokens consumed.

For 8PSK, 16APSK, and 32APSK modulation formats, the output of the LDPC encoder2.


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shall be bit interleaved using a block interleaver. Data is serially written into theinterleaver column-wise, and serially read out row-wise (the MSB of BBHEADER isread out first, except 8PSK rate 3/5 case where MSB of BBHEADER is read out third)as shown in figures below.

The configuration of the block interleaver for each modulation format is specified in3.the table below.


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Both interleaver and deinterleaver functions are implemented in this model. They are4.chosen by parameter Direction.

References



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DVBS2_LDPCEncoder PartCategories: FEC Encoding (dvb2ver)


Model Description

DVBS2_LDPCEncoder (dvb2ver) The LDPC Encoder for DVB-S2

DVBS2 LDPCEncoder

Description: The LDPC Encoder for DVB-S2Domain: UntimedC++ Code Generation Support: NOAssociated Parts: DVBS2 LDPCEncoder Part (dvb2ver)

Model Parameters




1/4 Enumeration NO

Input Ports


1 input int NO

Output Ports


2 output int NO

Notes/Equations

This model is to implement the inner channel coding: LDPC encoder. Each firing,1.Nldpc bits output tokens are generated and K ldpc(=N bch) bits input tokens

consumed.The FEC sub-system shall perform outer coding (BCH), Inner Coding (LDPC) and Bit2.interleaving. The input stream shall be composed of BBFRAMEs and the outputstream of FECFRAMEs. Each BBFRAME (K bch bits) shall be processed by the FEC

coding subsystem, to generate a FECFRAME (N bits). The parity check bits


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ldpc

(BCHFEC) of the systematic BCH outer code shall be appended after the BBFRAME,and the parity check bits (LDPCFEC) of the inner LDPC encoder shall be appendedafter the BCHFEC field, as shown in the figure below.

The tables below give the FEC coding parameters for the normal FECFRAME (nldpc =3.64 800 bits) and the short FECFRAME (nldpc = 16 200 bits).

The task of the LDPC encoder is to determine N ldpc-K ldpc parity bits ( p 0, p 1,..., p4.

Nldpc-Kldpc-1) for every block of K ldpc information bits (i 0, i 1,..., i Kldpc-1). The

procedure is as follows:Initialize p 0 = p 1 = p 2 = ... = p Nldpc-Kldpc-1 = 0

Accumulate the first information bit, i 0, at parity bit addresses specified in the

first row of tables B.1 through B.11 in annex B of Reference [1].For example, for rate 2/3 (table B.6), (all additions are in GF(2))


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p 0 = p 0 + i 0 p 2767 = p 2767 + i 0p 10491 = p 10491 + i 0 p 240 = p 240 + i 0p 16043 = p 16043 + i 0 p 18673 = p 18673 + i 0p 506 = p 506 + i 0 p 9279 = p 9279 + i 0p 12826 = p 12826 + i 0 p 10579 = p 10579 + i 0p 8065 = p 8065 + i 0 p 20928 = p 20928 + i 0p 8226 = p 8226 + i 0For the next 359 information bits, i m, m =1, 2, ..., 359 accumulate im at parity


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bit addresses (x + (m mod 360) * q)mod(N ldpc-K ldpc ) where x denotes the

address of the parity bit accumulator corresponding to the first bit i0 , and q is acode rate dependent constant specified in table 7a/7b.

Continuing with the example, q = 60 for rate 2/3. So for example forinformation bit i1 , the following operations are performed,p 60 = p 60 + i 1 p 2827 = p 2827 + i 1p 10551 = p 10551 + i 1 p 300 = p 300 + i 1p 16103 = p 16103 + i 1 p 18733 = p 18733 + i 1p 566 = p 566 + i 1 p 9339 = p 9339 + i 1p 12886 = p 12886 + i 1 p 10639 = p 10639 + i 1p 8125 = p 8125 + i 1 p 20988 = p 20988 + i 1p 8286 = p 8286 + i 1For the 361st information bit i 360, the addresses of the parity bit accumulators

are given in the second row of the tables B.1 through B.11. In a similar mannerthe addresses of the parity bit accumulators for the following 359 informationbits i m, m = 361, 362, ..., 719 are obtained using the formula (x + (m mod

360) * q)mod(N ldpc-K ldpc) where x denotes the address of the parity bit

accumulator corresponding to the information bit i 360 , i.e. the entries in the

second row of the tables B.1 through B.11.In a similar manner, for every group of 360 new information bits, a new rowfrom tables B.1 through B.11 are used to find the addresses of the parity bitaccumulators.

After all of the information bits are exhausted, the final parity bits are obtained as5.follows:

Sequentially perform the following operations starting with i = 1.p i = p i + p i-1, i = 1,2,...,N ldpc-K ldpc-1

Final content of p i , i = 0,1,..,N ldpc-K ldpc-1 is equal to the parity bit p i.

References


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DVBS2_Mapper PartCategories: Mapping (dvb2ver)


Model Description

DVBS2_Mapper (dvb2ver) The constellation mapper for DVB-S2

DVBS2 Mapper

Description: The constellation mapper for DVB-S2Domain: UntimedC++ Code Generation Support: NOAssociated Parts: DVBS2 Mapper Part (dvb2ver)

Model Parameters





1/4 Enumeration NO

Input Ports


1 input int NO

Output Ports


2 output complex NO

Notes/Equations

This model is used to implement the constellation mapper.1.Each FECFRAME (which is a sequence of 64 800 bits for normal FECFRAME, or 16 2002.bits for short FECFRAME), shall be serial-to-parallel converted (parallelism level = η

MOD, 2 for QPSK, 3 for 8PSK, 4 for 16APSK, 5 for 32APSK), in figures 9 to 12, the

MSB of the FECFRAME is mapped into the MSB of the first parallel sequence. Eachparallel sequence shall be mapped into constellation, generating a (I,Q) sequence ofvariable length depending on the selected modulation efficiency η .


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MOD

The input sequence shall be a FECFRAME, the output sequence shall be a XFECFRAME3.(compleX FECFRAME), composed of 64 800/η MOD (normal XFECFRAME) or 16 200/η

MOD (short XFECFRAME) modulation symbols. Each modulation symbol shall be a

complex vector in the format (I,Q) (I being the in-phase component and Q thequadrature component).For QPSK, the System shall employ conventional Gray-coded QPSK modulation with4.absolute mapping (no differential coding). Bit mapping into the QPSK constellationshall follow figure 9. The normalized average energy per symbol shall be equal to 1.Two FECFRAME bits are mapped to a QPSK symbol i.e. bits 2i and 2i+1 determinesthe ith QPSK symbol, where i = 0,1, 2, ..., (N/2)-1 and N is the coded LDPC blocksize.

For 8PSK, the System shall employ conventional Gray-coded 8PSK modulation with5.absolute mapping (no differential coding). Bit mapping into the 8PSK constellationshall follow figure 10. The normalized average energy per symbol shall be equal to 1.Bits 3i, 3i+1, 3i+2 of the interleaver output determine the ith 8PSK symbol where i =0, 1, 2,... (N/3)-1 and N is the coded LDPC block size.


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The 16APSK modulation constellation (figure 11) shall be composed of two concentric6.rings of uniformly spaced 4 and 12 PSK points, respectively in the inner ring of radiusR1 and outer ring of radius R2. The ratio of the outer circle radius to the inner circleradius (γ =R2/R1) shall comply with table 9. If 4R1 2 + 12R2 2 = 16 the averagesignal energy becomes 1. Bits 4i, 4i+1, 4i+2 and 4i+3 of the interleaver outputdetermine the ith 16APSK symbol, where i = 0, 1, 2, ..., (N/4)-1 and N is the codedLDPC block size.


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The 32APSK modulation constellation (see figure 12) shall be composed of three7.concentric rings of uniformly spaced 4, 12 and 16 PSK points, respectively in theinner ring of radius R1, the intermediate ring of radius R2 and the outer ring orradius R3. Table 10 defines the values of γ 1 = R2/R1 and γ 2 = R3/R1. If 4R1 2 +

12R2 2 + 16R3 2 = 32 the average signal energy becomes equal to 1. Bits 5i, 5i+1,5i+2, 5i+3 and 5i+4 of the interleaver output determine the ith 32APSK symbol,where i = 0, 1, 2, (N/5)-1.


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References



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DVBS2_CRCEncoder PartCategories: Mode Adaptation (dvb2ver)


Model Description

DVBS2_CRCEncoder (dvb2ver) The CRC encoder for DVB-S2

DVBS2 CRCEncoder

Description: The CRC encoder for DVB-S2Domain: UntimedC++ Code Generation Support: NOAssociated Parts: DVBS2 CRCEncoder Part (dvb2ver)

Input Ports


1 input int NO

Output Ports


2 output int NO

Notes/Equations

This model is used to implement CRC-8 encoder defined in clause 5.1.4 in Reference1.[1] for broadcasting. Each firing, 188*8 bits output tokens are generated and thesame number input tokens consumed.UPL = 188*8 the input stream is a sequence of User Packets of length UPL bits,2.preceded by a sync-byte (the sync-byte being = 0D when the original stream did notcontain a sync-byte).The useful part of the UP (excluding the sync-byte) shall be processed by a3.systematic 8-bit CRC encoder. The generator polynomial shall be:g(X) = (X 5+X 4+X 3+X 2+1)(X 2+X+1)(X+1) = X 8+X 7+X 6+X 4+X 2+1The CRC encoder output shall be computed as: CRC = remainder(X 8 u(X):g(X))4.

Where u(X) is the input sequence (UPL-8 bits) to be systematically encoded.The figure below gives a possible implementation of the CRC generator bymeans of a shift register (Note: the register shall be initialized to all zeros beforethe first bit of each sequence enters the circuit).The computed CRC-8 shall replace the sync-byte of the following UP.


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As described in DVBS2 MergerSlicer (dvb2ver), the sync-byte is copied into theSYNC field of the BBHEADER for transmission.

References



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DVBS2_MergerSlicer PartCategories: Mode Adaptation (dvb2ver)


Model Description

DVBS2_MergerSlicer (dvb2ver) Segment the input signals in to DFLs and insert head for DVB-S2

DVBS2 MergerSlicer

Description: Segment the input signals in to DFLs and insert head for DVB-S2Domain: UntimedC++ Code Generation Support: NOAssociated Parts: DVBS2 MergerSlicer Part (dvb2ver)

Model Parameters



CodeRate code rate for LDPC: 1/4, 1/3, 2/5, 1/2, 3/5, 2/3,3/4, 4/5, 5/6, 8/9, 9/10

1/4 Enumeration NO

NumOfLdpcBlocks the number of LDPC blocks, to fullfillNumOfLdpcBlocks*DFL/(188*8) is an integervalue

188 Integer NO

rollOffFactor roll off factor for the root raised cosine filter:0.35, 0.25, 0.20

0.35 Enumeration NO

Input Ports


1 input int NO

Output Ports


2 output int NO

Notes/Equations

This Merger/Slicer input stream is organised as Packetized Input Stream. Each firing,1.NumOfLdpcBlocks*K bch bits output tokens are generated and NumOfLdpcBlocks*DFL


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bits input tokens consumed.According to the figure below, The UP length is UPL bits (where UPL = 0 is not2.supported). The input stream shall be buffered until the Merger/Slicer may readthem.The Slicer shall read (i.e. slice) from its input (support single input stream) a DATA3.FIELD, composed of DFL bits (Data Field Length), where: K bch -(10x8) ≥ DFL ≥ 0 (K

bch is described in DVBS2 BCHEncoder (dvb2ver), 80 bits are dedicated to the

BBHEADER. In this DVB-S2 library, we only support DFL = K bch-80.

The Merger shall concatenate, in a single output, different data fields read and sliced4.from its input. In presence of a single stream, only the slicing functionality applies.A DATA FIELD shall be composed of bits taken from a single input port and shall be5.transmitted in a homogeneous transmission mode (FEC code and modulation).In this Broadcast services applications, the Merger/Slicer shall allocate a number of6.input bits equal to the maximum DATAFIELD capacity (DFL = K bch -80), thus

breaking UPs in subsequent DATAFIELDs. In the same time, this model consumesNumOfLdpcBlocks*K bch bits each firing, selecting the NumOfLdpcBlocks to make the

NumOfLdpcBlocks*K bch could be divided by UPL to porcess an integer number of UPs

each firing.After Sync-byte replacing by CRC-8 (see DVBS2 CRCEncoder (dvb2ver)), it is7.necessary to provide the receiver a method to recover UP synchronization (when thereceiver is already synchronized to the DATA FIELD). Therefore the number of bitsfrom the beginning of the DATA FIELD and the beginning of the first complete UP(first bit of the CRC-8) shall be detected by the Merger/Slicer and stored in SYNCDfield (i.e. SYNC Distance) of the Base-Band Header. For example, SYNCD = 0Dmeans that the first USER PACKET is aligned to the DATA FIELD.

A fixed length base-band Header (BBHEADER) of 10 bytes shall be inserted in front of8.the DATA FIELD, describing its format (the maximum efficiency loss introduced bythe BBHEADER is 0.25 % for nldpc = 64 800 and 1 % for nldpc = 16 200 assuminginner code rate 1/2).MATYPE (2 bytes): describes the input stream(s) format, the type of Mode Adaptation9.and the transmission Roll-off factor, as explained in the table below.First byte (MATYPE-1):10.


25

TS/GS field (2 bits): Transport Stream Input or Generic Stream Input(packetized or continuous).SIS/MIS field (1 bit): Single Input Stream or Multiple Input Stream.CCM/ACM field (1 bit): Constant Coding and Modulation or Adaptive Coding andModulation (VCM is signalled as ACM).ISSYI (1 bit), (Input Stream Synchronization Indicator): ISSYI = 0 = not-activein this library right now.NPD (1 bit): Null-packet deletion active/not active.RO (2 bits): Transmission Roll-off factor (α).In this library, the first 6 bits are constant value: 111100, while the last2 bits is decided by the roll-off factor.

Second byte (MATYPE-2):11.If SIS/MIS = Multiple Input Stream, then second byte = Input Stream Identifier(ISI); else second byte reserved.In this library, the second byte is reserved to be 00000000.

UPL (2 bytes): User Packet Length in bits, in the range [0,65535].12.EXAMPLE 1: 0000HEX = continuous stream.EXAMPLE 2: 000AHEX = UP length of 10 bits.EXAMPLE 3: UPL = 188x8D for MPEG transport stream packetsIn this library, the 2 bytes UPL is 188x8D = 0000010111100000B.

DFL (2 bytes): Data Field Length in bits, in the range [0,58112].13.EXAMPLE: 000AHEX = Data Field length of 10 bits.In this library, the DFL = K bch-80.

SYNC (1 byte): copy of the User Packet Sync-byte.14.EXAMPLE 1: SYNC = 47HEX for MPEG transport stream packets.EXAMPLE 2: SYNC = 00HEX when the input Generic packetized stream did notcontain a sync-byte (therefore the receiver, after CRC-8 decoding, shall removethe CRC-8 field without reinserting the Sync-byte).In this library, the SYNC byte is 47HEX.EXAMPLE 3: SYNC = not relevant for Generic continuous input streams.

SYNCD (2 bytes): distance in bits from the beginning of the DATA FIELD and the first15.UP from this frame (first bit of the CRC-8). SYNCD = 65535D means that no UPstarts in the DATA FIELD.CRC-8 (1 byte): error detection code applied to the first 9 bytes of the BBHEADER.16.

CRC-8 shall be computed using the encoding circuit of the figure in DVBS2CRCEncoder (dvb2ver) (switch in A for 72 bits, in B for 8 bits).

The BBHEADER transmission order is from the MSB of the TS/GS field.17.Table below shows the BBHEADER and the slicing policy for a Single Transport18.Stream Broadcast Service which is implemented in this library.


26

References



27

DVBS2_PLFramer PartCategories: PL Framing (dvb2ver)


Model Description

DVBS2_PLFramer (dvb2ver) The physical layer framing for DVB-S2

DVBS2 PLFramer

Description: The physical layer framing for DVB-S2Domain: UntimedC++ Code Generation Support: NOAssociated Parts: DVBS2 PLFramer Part (dvb2ver)

Model Parameters





1/4 Enumeration NO

InsertPilot Insert Pilot Block or not: NO, YES YES Enumeration NO

Input Ports


1 input complex NO

Output Ports


2 output complex NO

Notes/Equations

This model is used to implement the Physical Layer framer process, according to the1.figure below.The PLFraming sub-system shall generate a physical layer frame (named PLFRAME)2.by performing the following processes:

XFECFRAME slicing into an integer number S of constant length SLOTs (length:


28

M = 90 symbols each); S shall be according to the table below.

PLHEADER generation and insertion before the XFECFRAME for receiverconfiguration. PLHEADER shall occupy exactly one SLOT (length: M = 90Symbols).Pilot Block insertion (for modes requiring pilots) every 16 SLOTS, to helpreceiver synchronization. The Pilot Block shall be composed of P = 36 pilotsymbols.

The PLFRAMING efficiency is η = 90S/[90(S+1)+ P int{(S-1)/16}], where P = 36 and3.int{.} is the integer function.The PLHEADER is intended for receiver synchronization and physical layer signalling.4.NOTE: after decoding the PLHEADER, the receiver knows the PLFRAME duration andstructure, the modulation and coding scheme of the XFECFRAME, the presence orabsence of pilot symbols. The PLHEADER (one SLOT of 90 symbols) shall becomposed of the following fields:

SOF (26 symbols), identifying the Start of Frame.PLS code (64 symbol): PLS (Physical Layer Signalling) code shall be a non-systematic binary code of length 64 and dimension 7 with minimum distancedmin = 32. It is equivalent to the first order Reed-Muller under permutation. Ittransmits 7 bits for physical layer signalling purpose. These 7 bits consists oftwo fields: MODCOD and TYPE defined as follows:

MODCOD (5 symbols), identifying the XFECFRAME modulation and FECrate;TYPE (2 symbols), identifying the FECFRAME length (64 800 bits or 16 200bits) and the presence/absence of pilots.

The PLHEADER, represented by the binary sequence (y 1, y 2,...y 90) shall be5.

modulated into 90PI/2BPSK symbols according to the rule:I 2i-1 = Q 2i-1 = (1/sqrt(2))(1-2y 2i-1), I 2i = -Q 2i = -(1/sqrt(2))(1-2y 2i) for i = 1, 2,

..., 45


29

SOF shall correspond to the sequence 18D2E82HEX (01-1000-....-0010 in binary6.notation, the left-side bit being the MSB of the PLHEADER).MODCOD shall correspond to 5 bits, identifying code rates in the set η C = [1/4, 1/3,7.

2/5, 1/2, 3/5, 2/3, 3/4, 4/5, 5/6, 8/9, 9/10] and modulations in the set of spectrumefficiencies η MOD = [2, 3, 4, 5] according to the table below.

The MSB of the TYPE field shall identify 2 FECFRAME sizes (0 = normal: 64 800 bits;8.1 = short: 16 200 bits). The LSB of the TYPE field shall identify the pilotconfigurations (see clause 5.5.3) (0 = no pilots, 1 = pilots).The MODCODE and TYPE fields are bi-orthogonally coded with a (64,7) code. Such9.code is constructed starting from a bi-orthogonal (32,6) code according to theconstruction in the figure below.

The particular construction guarantees that each odd bit in the (64,7) code is either10.always equal to the previous one or is always the opposite. Which of the twohypotheses is true depends on the bit b7. This fact can be exploited in casedifferentially coherent detection is adopted in the receiver.

The MODCOD and the MSB of the TYPE field shall be encoded by a linear blockcode of length 32 with the following generator matrix.


30

The most significant bit of the MODCOD is multiplied with the first row of the matrix,11.the following bit with the second row and so on. The 32 coded bits is denoted as ( y 1,y 2, ...,y 32 ). When the least significant bit of the TYPE field is 0, the final PLS code

will generate ( y 1,y 1,y 2,y 2,...,y 32,y 32 ) as the output, i.e. each symbol shall be

repeated. When the least significant bit of the TYPE field is 1, the repeated symbol isfurther binary complemented. The 64 bits output of the PLS code is further scrambledby the binary sequence:0111000110011101100000111100100101010011010000100010110111111010.Two PLFRAME configurations shall be possible:12.

Without pilots;With pilots.In this latter case a PILOT BLOCK shall be composed of P = 36 pilot symbols.Each pilot shall be an un-modulated symbol, identified by I = (1/sqrt(2)), Q =(1/sqrt(2)). The first PILOT BLOCK shall be inserted 16 SLOTs after thePLHEADER, the second after 32 SLOTs and so on. If the PILOT BLOCK positioncoincides with the beginning of the next SOF, then the PILOT BLOCK is nottransmitted.

References



31

DVBS2_PLScrambler PartCategories: PL Framing (dvb2ver)


Model Description

DVBS2_PLScrambler (dvb2ver) The physical layer scrambling for DVB-S2

DVBS2 PLScrambler

Description: The physical layer scrambling for DVB-S2Domain: UntimedC++ Code Generation Support: NOAssociated Parts: DVBS2 PLScrambler Part (dvb2ver)

Model Parameters

Name Description Default Units Type Runtime Tunable




Direction Scramble or Descramble: Scramble,Descramble

Scramble Enumeration NO

Input Ports


1 input complex NO

Output Ports


2 output complex NO

Notes/Equations

This model is used to implement the physical framer scrambler or descrambler.1.Prior to carrier modulation, each PLFRAME, excluding the PLHEADER, shall be2.randomized for energy dispersal by multiplying the (I+jQ) samples by a complexrandomization sequence (C I + jC Q): ISCRAMBLED = (I*C I - Q*C Q); QSCRAMBLED

= (I*C Q + Q*C I)

NOTE: The randomization sequence rate corresponds to the I-Q PLFRAME symbol3.


32

rate, thus it has no impact on the occupied signal bandwidth. The randomizationsequence has a period greater than the maximum required duration of about 70 000symbols).The randomization sequence shall be reinitialized at the end of each PLHEADER (see4.the figure below). The PLFRAME duration depends on the modulation selected, thusthe randomization sequence length shall be truncated to the current PLFRAME length.

The scrambling code sequences shall be constructed by combining two real m-5.sequences (generated by means of two generator polynomials of degree 18) into acomplex sequence. The resulting sequences thus constitute segments of a set of Goldsequences.Let x and y be the two sequences respectively. The x sequence is constructed using6.the primitive (over GF(2)) polynomial 1+x 7 + x 18. The y sequence is constructedusing the polynomial 1+ y 5 + y 7 + y 10 + y 18.The sequence depending on the chosen scrambling code number n is denoted zn in7.the sequel. Furthermore, let x(i) , y(i) and z n(i) denote the i th symbol of the

sequence x, y, and z n respectively. The m-sequences x and y are constructed as:

Initial conditions:x is constructed with x(0) = 1, x(1) = x(2) = ... = x(16) = x(17) = 0.y(0) = y(1) =...= y(16) = y(17) = 1.

Recursive definition of subsequent symbols:x(i+18) = x(i+7) + x(i) modulo 2, i = 0,..., 2 18 - 20.y(i+18) = y(i+10) + y(i+7) + y(i+5) + y(i) modulo 2, i = 0,..., 2 18 - 20.

The nth Gold code sequence zn n = 0,1,2,...,2 18-2, is then defined as:8.z n(i) = [x((i+n) modulo (2 18-1)) + y(i) ] modulo 2, i = 0,..., 2 18 - 2.

These binary sequences are converted to integer valued sequences R n (R n assuming9.

values 0, 1, 2, 3) by the following transformation:R n(i) = 2*z n((i + 131 072) modulo (2 18-1)) + z n(i) i = 0, 1, ..., 66 419.

Finally, the n th complex scrambling code sequence C I(i) + jC Q(i) is defined as:10.


33

The figure below gives a possible block diagram for PL scrambling sequences11.generation for n = 0.

In case of broadcasting services, n = 0 shall be used as default sequence, to avoid12.manual receiver setting or synchronization delays.Both scrambler and descrambler functions are implemented in this model. They are13.chosen by parameter Direction.

References



34

DVBS2_Demapper PartCategories: Receiver (dvb2ver)


Model Description

DVBS2_Demapper (dvb2ver) The constellation demapper for DVB-S2

DVBS2 Demapper

Description: The constellation demapper for DVB-S2Domain: UntimedC++ Code Generation Support: NOAssociated Parts: DVBS2 Demapper Part (dvb2ver)

Model Parameters





1/4 Enumeration NO

EsNo Es versus noise density 1 Float NO

Input Ports


1 input complex NO

Output Ports


2 output real NO

Notes/Equations

This model implements the constellation demapper. First it transforms received1.symbol values into log-likelihoods; then performs soft demapping (converts M-arysymbol likelihoods to bitwise LLRs).The linear approximation to log-MAP is used.2.


35

References



36

DVBS2_FrameSync PartCategories: Receiver (dvb2ver)


Model Description

DVBS2_FrameSync (dvb2ver) The frame synchronization for DVB-S2

DVBS2 FrameSync

Description: The frame synchronization for DVB-S2Domain: UntimedC++ Code Generation Support: NOAssociated Parts: DVBS2 FrameSync Part (dvb2ver)

Model Parameters





1/4 Enumeration NO


SymbolRate Symbol rate 1e7 Integer NO

Input Ports


1 input complex NO

Output Ports


2 output complex NO

3 index int NO

4 DeltaF real NO

Notes/Equations

A scheme to correlate on both the SOF and PLSCODE differentially is used for frame1.


37

synchronization. The shift registers in the circuit can be partitioned into two sections.The first is associated with SOF, the second with PLSCODE. There are in total 57 tapsassociated with the 89 registers. In the first part, 25 of them are associated with thepair-wise difference of SOF. In the second part, 32 nonzero taps are associated withPLSCODE since only 32 out of the 64 differentials are known. The taps associatedwith the shift register for computing the correlation can be obtained as follows. Firstset all the registers to zero, then shift the modulated SOF and a modulated andscrambled codeword of PLSCODE into the circuit. Once the rightmost registerbecomes nonzero, the tap associated with a register is just the complex conjugate ofthe content of the corresponding register. Given that the modulated SOF andPLSCODE take only ±1, ±i, the taps only take these four possible values as well.When used for frame synchronization, the incoming signal arriving at the correlator is2.sampled at one sample per symbol. It is first differentially decoded and the resultingsamples are then sequentially shifted into a shift register of length 89. The contentsof the shift register are multiplied with the taps. The first 25 and the last 32 values atthe output of the multipliers are separately summed together in two differentbranches. The outputs of the two summers are respectively added and subtracted toproduce two values. The maximum of the absolute value out of the two branches isthe final output of this correlation circuit.The output is then further processed by a peak search algorithm.3.

References



38

DVBS2_LDPCDecoder PartCategories: Receiver (dvb2ver)


Model Description

DVBS2_LDPCDecoder (dvb2ver) The LDPC Decoder for DVB-S2

DVBS2 LDPCDecoder

Description: The LDPC Decoder for DVB-S2Domain: UntimedC++ Code Generation Support: NOAssociated Parts: DVBS2 LDPCDecoder Part (dvb2ver)

Model Parameters



CodeRate code rate for LDPC: 1/4, 1/3, 2/5, 1/2, 3/5,2/3, 3/4, 4/5, 5/6, 8/9, 9/10

1/4 Enumeration NO

DecodeAlgorithm decoding algorithm for LDPC: Sum Product,Normalized Min-Sum, Offset Min-Sum

SumProduct

Enumeration NO

Input Ports


1 Input real NO

2 sigma real NO

Output Ports


3 Output int NO

Notes/Equations

This model is to implement the inner channel decoding: LDPC decoder. Each firing,1.Nldpc bits input tokens are consumed and K ldpc(=N bch) bits output are generated.

Sum Product decoding algorithm for LDPC codes is described here. The parity check2.


39

matrix H can be viewed as a bipartite graph with two kinds of nodes: N variablenodes corresponding to the encoded variables, and M parity check nodescorresponding to the parity checks represented by the rows of the matrix H. Eachvariable is connected to d s parity check nodes and each parity check node is

connected to d v variable nodes, furthermore, for LDPC codes in DVB-S2, both d sand d v aren’t constant.

The decoding of LDPC codes, Belief Propagation (BP) algorithm, is based on passingmessages between variable nodes and parity check nodes along the edges throughwhich they are connected in an iterative manner. The messages represent estimatesof the codeword bits based on the received signals and form the parity checkconstraints. Two different computations have to be performed during a decodingiteration, namely the variable node update and parity check node update. Assumethat L mn represent the parity check to variable message along the i th edge

connected to the n th parity check node during the q th iteration (we will not explicitly

use the index n to denote quantities associated with the n th node as operations are

identical at all nodes). Similarly, let Z mn represent the variable to parity check

message along the i th edge connected to the n th variable node during the q thiteration. Also denote the set of parity check nodes connected to variable nodes n asM n and the set of variable nodes connected to parity check node m as N(m). Then

each iteration i of the Sum Product decoding includes the following steps:a). Initialization: after transmission through the channel, compute the posterioriprobability of each variable node n as L n(0)=L c y n, where y n is received vector.

Assuming the AWGN channel with noise variance σ 2, the reliability value is L c=2/σ 2

. The initialization is done in every position (m,n) of the parity check matrix H, whereH m,n=1.

b). Processing in parity check nodes.c). Processing in variable nodes.d). Posteriori probabilities.The Min-Sum algorithm uses simplified processing in parity check nodes.3.Normalized Min-Sum(NMS) decoding algorithm for LDPC codes: the parity check node4.processing could be improved by dividing with a constant smaller than 1.Offset Min-Sum (OMS) decoding algorithm for LDPC codes is another approach to5.improve the accuracy of the extrinsic messages passing by the Min-Sum algorithm. Itreduces the reliability values by a positive constant.

References

ETSI EN 302 307, "Digital Video Broadcasting (DVB); Second generation framing1.structure, channel coding and modulation systems for Broadcasting, InteractiveServices, News Gathering and other broadband satellite applications" Version 1.1.2,Jun. 2006.Hu, X.-Y., Eleftheriou, E., Arnold, D.-M., and Dholakia, A.: “EEfficient2.Implementations of the Sum-Product Algorithm for Decoding LDPC codes”, IEEETransactions on Communications, 2005, 53, (8).


40

M. Fossorier, M. Mihaljevic, H. lmai, “Reduced complexity iterative decoding of low3.density parity codes based on Belief Propagation,” IEEE Transactions onCommunications, vol 47, May 1989.Jinghu Chen and M. Fossorier, “Density Evolution for BP-Based Decoding Algorithm of4.LDPC Codes and Their Quantized Versions”, IEEE Commun Lett, vol. 6, No. 5, May2002.


41

DVBS2_PLDemuxFrame PartCategories: Receiver (dvb2ver)


Model Description

DVBS2_PLDemuxFrame (dvb2ver) The physical layer framing demux for DVB-S2

DVBS2_PLDemuxFrame

Description: The physical layer framing demux for DVB-S2Domain: UntimedC++ Code Generation Support: NOAssociated Parts: DVBS2 PLDemuxFrame Part (dvb2ver)

Model Parameters





1/4 Enumeration NO


Input Ports


1 input complex NO

Output Ports


2 output complex NO

Notes/Equations

This model is used to implement the Physical Layer frame demux process. It's the1.reverse procedure of DVBS2_PLFramer. It removes the PLHeader and pilots.

References


42



43

DVBS2_Receiver Part DVBS2 baseband receiver

Categories: Receiver (dvb2ver)


Model

DVBS2_Receiver (dvb2ver)

DVBS2 Receiver

Description: DVBS2 baseband receiverAssociated Parts: DVBS2 Receiver Part (dvb2ver)

Model Parameters



ModType modulation type: QPSK, 8PSK, 16APSK,32APSK

16APSK Enumeration NO


8/9 Enumeration NO

rollOffFactorIndex roll off factor index for the root raisedcosine filter

0 Float NO


SymbolRate complex symbol rate 10000000 Hz Float NO

OverSamplingRatio oversampling ratio 2 Float NO

SNR signal to noise ratio 3 dB Float NO

Input Ports

Port Name Description Signal Type Optional

1 input Terminal: Standard Data PortTerminal

complex NO

Output Ports


44


2 output Terminal: Standard Data PortTerminal

int NO

Notes/Equations

This subnetwork completes DVB-S2 baseband receiver.1.The DVBS2_Receiver schematic is shown below:2.

This subnetwork contains these features: Base-Band Filtering, Frame3.synchronization, Descrambler, De-framing, Demapper, Deinterleaver, LDPC Decoderand BCH Decoder.It outputs decoded data to calculate BER and PER. The referenced PER curve for4.different FecFrame, ModType and CodeRate are shown in References.

References

ETSI EN 302 307, "Digital Video Broadcasting (DVB); Second generation framing1.structure, channel coding and modulation systems for Broadcasting, InteractiveServices, News Gathering and other broadband satellite applications" Version 1.1.2,Jun. 2006.ETSI TR 102 376, "Digital Video Broadcasting (DVB) User guidelines for the second2.generation system for Broadcasting, Interactive Services, News Gathering and otherbroadband satellite applications (DVB-S2)" Version 1.1.1, Feb. 2005.


45

DVBS2_Source Part DVBS2 baseband signal source

Categories: Source (dvb2ver)


Model

DVBS2_Source (dvb2ver)

DVBS2 Source

Description: DVBS2 baseband signal sourceAssociated Parts: DVBS2 Source Part (dvb2ver)

Model Parameters



ModType modulation type: QPSK, 8PSK, 16APSK,32APSK

16APSK Enumeration NO


8/9 Enumeration NO

NumOfLdpcBlocks the number of LDPC blocks, to fullfillNumOfLdpcBlocks*DFL/(188*8) is an integervalue

188 Float NO

rollOffFactorIndex roll off factor index for the root raised cosinefilter

0 Float NO


SymbolRate complex symbol rate 10000000 Hz Float NO

OverSamplingRatio oversampling ratio 2 Float NO

Output Ports


1 output Terminal: Standard Data PortTerminal

complex NO

2 beforeBCH Terminal: Standard Data PortTerminal

int NO

Notes/Equations


46

This subnetwork completes DVB-S2 baseband signal source. A functional block1.diagram of DVB-S2 system is illustrated below:

The DVBS2_Source schematic is shown below:2.

Forward Error Correction (FEC) Encoding shall be carried out by the concatenation of3.BCH outer codes and LDPC(Low Density Parity Check) inner codes (rates 1/4, 1/3, 2/5, 1/2, 3/5, 2/3, 3/4, 4/5,5/6, 8/9, 9/10). Depending on theapplication area, the FEC coded block shall have length n ldpc = 64 800 bits or 16 200

bits. Bit interleaving shall beapplied to FEC coded bits for 8PSK, 16APSK and 32APSK.Mapping into QPSK, 8PSK, 16APSK and 32APSK constellations shall be applied,4.depending on the application area.Gray mapping of constellations shall be used for QPSK and 8PSK.Physical layer framing shall be applied, synchronous with the FEC frames, to provide5.Dummy PLFRAME insertion,Physical Layer (PL) Signalling, pilot symbols insertion (optional) and Physical LayerScrambling for energy dispersal.Dummy PLFRAMEs are transmitted when no useful data is ready to be sent on thechannel. The System provides a


47

regular physical layer framing structure, based on SLOTs of M = 90 modulatedsymbols, allowing reliable receiversynchronization on the FEC block structure. A slot is devoted to physical layersignalling, including Start-of-Framedelimitation and transmission mode definition. Carrier recovery in the receivers maybe facilitated by the introductionof a regular raster of pilot symbols (P = 36 pilot symbols every 16 SLOTs of 90symbols), while a pilot-less transmissionmode is also available, offering an additional 2,4 % useful capacity.Base-Band Filtering and Quadrature Modulation shall be applied, to shape the signal6.spectrum (squared-root raisedcosine, roll-off factors 0,35 or 0,25 or 0,20) and to generate the RF signal.

References



48

DVBT2_P1_Gen Part DVBT2 P1 baseband signal source



Model

DVBT2_P1_Gen (dvb2ver)

DVBT2 P1 Gen

Description: DVBT2 P1 baseband signal sourceAssociated Parts: DVBT2 P1 Gen Part (dvb2ver)

Model Parameters

Name Description Default Units Type Runtime Tunable

S1_Index index of S1 modulation pattern 1 Positiveinteger

NO

S2_Index index of S2 modulation pattern 1 Positiveinteger

NO

OversamplingRatio oversampling ratio: x1, x2, x4, x8 x2 Enumeration NO

Output Ports


1 Output Terminal: Standard Data PortTerminal

complex NO

Notes/Equations

This subnetwork generates DVB-T2 P1 preamble symbol according to section 9.8 in1.[1]. The P1 symbol structure is in the following figure.


49

The scheme in the following figure shows how the P1 symbol is generated:2.

The DVBT2_P1_Gen schematic is shown below:3.


50

References

ETSI EN 302 755 "Digital Video Broadcasting (DVB); Frame structure channel coding1.and modulation for a second generation digital terrestrial tellevision broadcastingsystem (DVB-T2)". Version 1.1.1, Oct. 2008.


51

DVBT2_P2_Data_Gen Part DVBT2 P2 and Data baseband signal source



Model

DVBT2_P2_Data_Gen (dvb2ver)

DVBT2 P2 Data Gen

Description: DVBT2 P2 and Data baseband signal sourceAssociated Parts: DVBT2 P2 Data Gen Part (dvb2ver)

Model Parameters


Mode DVB-T2 Mode: 1K mode, 2K mode, 4Kmode, 8K mode, 16K mode, 32K mode

1K mode Enumeration NO

GuardInterval DVB-T2 Guard Interval: 1/128, 1/32, 1/16,19/256, 1/8, 19/128, 1/4

1/16 Enumeration NO

CarrierMode DVB-T2 Carrier Mode: Normal, Extended Normal Enumeration NO

PilotPattern DVB-T2 Pilot Pattern for Scatter Pilot: PP1,PP2, PP3, PP4, PP5, PP6, PP7, PP8

PP4 Enumeration NO


PAPR_RC PAPR reduction by using reserved carriers?:NO, YES

NO Enumeration NO

NumDataSym number of OFDM symbols of data in T2-frame

10 Positiveinteger

NO

PAPR_Vclip clip threshold for reserved carrier PAPR 2 Float NO

RunMode 0: Run with calculating Index array inequation; 1: Generate binary Index files andRun with binary Index files reading: Useequation Index arrays, Use binary Indexfiles

UseequationIndexarrays

Enumeration NO

Input Ports


52


1 MappingData Terminal: Standard Data PortTerminal

complex NO

Output Ports



complex NO

Notes/Equations

This subnetwork generates DVB-T2 P2 symbols and data symbols according to1.section 8 (except section 8.3,8.4 and 8.5) and section 9 in [1].The DVB-T2 frame structure is shown in following figure. At the top level, the frame2.structure consists of super-frames, which are divided into T2-frames and these arefurther divided into OFDM symbols. The super-frame may in addition have FEF parts(see clause 8.4). In this subnetwork, only T2-frame is implemented.

The T2-frame comprises one P1 preamble symbol, followed by one or more P2preamble symbols, followed by a configurable number of data symbols. In certaincombinations of FFT size, guard interval and pilot pattern (see clause 9.2.7), the lastdata symbol shall be a frame closing symbol. The details of the T2-frame structureare described in clause 8.3.2).The P1 symbols are unlike ordinary OFDM symbols and are inserted later (see clause9.8).The P2 symbol(s) follow immediately after the P1 symbol. The main purpose of theP2 symbol(s) is to carry L1 signalling data. The L1 signalling data to be carried isdescribed in clause 7.2, its modulation and error correction coding are described inclause 7.3 and the mapping of this data onto the P2 symbol(s) is described in clause8.3.5.Various cells within the OFDM frame are modulated with reference information whose3.transmitted value is known to the receiver. Cells containing reference information aretransmitted at "boosted" power level. The information transmitted in these cells arescattered, continual, edge, P2 or frame-closing pilot cells. The locations andamplitudes of these pilots are defined in clauses 9.2.3 to 9.2.7 for SISOtransmissions, and are modified according to clause 9.2.8 for MISO transmissions.The value of the pilot information is derived from a reference sequence, which is aseries of values, one for each transmitted carrier on any given symbol (see clause9.2.2).PAPR reduction using reserved carriers is also implemented in P2 and Data OFDM4.symbols part. Parameter PAPR_RC can control whether to use this PAPR reductionalgorithm or not.


53

The DVBT2_P2_Data_Gen schematic is shown below:5.

References



54

DVBT2_Source Part DVBT2 baseband signal source



Model

DVBT2_Source (dvb2ver)

DVBT2 Source

Description: DVBT2 baseband signal sourceAssociated Parts: DVBT2 Source Part (dvb2ver)

Model Parameters


55


Bandwidth bandwidth of DVB-T2: 1.7 MHz, 5 MHz, 6MHz, 7 MHz, 8 MHz, 10 MHz

8 MHz Enumeration NO

Mode DVB-T2 Mode: 1K mode, 2K mode, 4Kmode, 8K mode, 16K mode, 32K mode

1K mode Enumeration NO

GuardInterval DVB-T2 Guard Interval: 1/128, 1/32, 1/16,19/256, 1/8, 19/128, 1/4

1/16 Enumeration NO

CarrierMode DVB-T2 Carrier Mode: Normal, Extended Normal Enumeration NO

PilotPattern DVB-T2 Pilot Pattern for Scatter Pilot: PP1,PP2, PP3, PP4, PP5, PP6, PP7, PP8

PP4 Enumeration NO


PAPR_RC PAPR reduction by using reserved carriers?:NO, YES

NO Enumeration NO

PAPR_Vclip Clip threshold 2 Float NO

NumDataSym number of OFDM symbols of data in T2-frame

10 Positiveinteger

NO

S1_Index index of S1 modulation pattern in P1 1 Positiveinteger

NO

S2_Index index of S2 modulation pattern in P1 1 Positiveinteger

NO

RunMode 0: Run with calculating Index array inequation; 1: Generate binary Index files andRun with binary Index file reading: Useequation Index arrays, Use binary Indexfiles

UseequationIndexarrays

Enumeration NO

Input Ports


1 MappingData Terminal: Standard Data PortTerminal

complex NO

Output Ports



complex NO

Notes/Equations

This subnetwork generates DVB-T2 uncoded source according to section 8 (except1.section 8.3,8.4 and 8.5) and section 9 in [1].The DVB-T2 frame structure is shown in following figure. At the top level, the frame2.structure consists of super-frames, which are divided into T2-frames and these arefurther divided into OFDM symbols. The super-frame may in addition have FEF parts(see clause 8.4). In this subnetwork, only T2-frame is implemented.


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The T2-frame comprises one P1 preamble symbol, followed by one or more P2preamble symbols, followed by a configurable number of data symbols. In certaincombinations of FFT size, guard interval and pilot pattern (see clause 9.2.7), the lastdata symbol shall be a frame closing symbol. The details of the T2-frame structureare described in clause 8.3.2).The P1 symbols are unlike ordinary OFDM symbols and are inserted later (see clause9.8).The P2 symbol(s) follow immediately after the P1 symbol. The main purpose of theP2 symbol(s) is to carry L1 signalling data. The L1 signalling data to be carried isdescribed in clause 7.2, its modulation and error correction coding are described inclause 7.3 and the mapping of this data onto the P2 symbol(s) is described in clause9.3.5.Various cells within the OFDM frame are modulated with reference information whose3.transmitted value is known to the receiver. Cells containing reference information aretransmitted at "boosted" power level. The information transmitted in these cells arescattered, continual, edge, P2 or frame-closing pilot cells. The locations andamplitudes of these pilots are defined in clauses 9.2.3 to 9.2.7 for SISOtransmissions, and are modified according to clause 9.2.8 for MISO transmissions.The value of the pilot information is derived from a reference sequence, which is aseries of values, one for each transmitted carrier on any given symbol (see clause9.2.2).PAPR reduction using reserved carriers is also implemented in P2 and Data OFDM4.symbols part. Parameter PAPR_RC can control whether to use this PAPR reductionalgorithm or not.The DVBT2_Source schematic is shown below:5.


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References



58

DVBS2_BBScrambler PartCategories: Stream Adaptation (dvb2ver)


Model Description

DVBS2_BBScrambler (dvb2ver) The baseband scrambler for DVB-S2

DVBS2 BBScrambler

Description: The baseband scrambler for DVB-S2Domain: UntimedC++ Code Generation Support: NOAssociated Parts: DVBS2 BBScrambler Part (dvb2ver)

Model Parameters




1/4 Enumeration NO

Input Ports


1 input int NO

Output Ports


2 output int NO

Notes/Equations

The complete BBFRAME from DVBS2 MergerSlicer (dvb2ver) shall be randomized.1.The randomization sequence shall be synchronous with the BBFRAME, starting fromthe MSB and ending after Kbch bits. Each firing, Kbch bits output tokens aregenerated and the same number input tokens consumed.The scrambling sequence shall be generated by the feed-back shift register of the2.figure below. The polynomial for the Pseudo Random Binary Sequence (PRBS)generator shall be: 1 + X 14 + X 15

Loading of the sequence (100101010000000) into the PRBS register, as indicated in3.


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the figure, shall be initiated at the start of every BBFRAME.

References


Documents

DVB2 Baseband Verification Library - Keysightedadownload.software.keysight.com/eedl/systemvue/... · SystemVue - DVB2 Baseband Verification Library 1 SystemVue 2010.07 2010 ... 5.BCH