dsPIC33CHXXXMP508 FAMILY

dsPIC33CHXXXMP508 FamilyFlash Programming Specification

1.0 DEVICE OVERVIEWThis document defines the programming specificationfor the dsPIC33CHXXXMP508 16-bit Digital SignalController (DSC) family. These devices contain both aMaster and Slave CPU core. The Slave core programis loaded into the Slave program RAM from the MasterFlash program memory at run time. The Slave programis appended to the Master program and written to theMaster Flash program memory via a single Hex file.Therefore, the scope of this document will only includethe programming of the Master Flash program memory.This programming specification is required only forthose developing programming support for thefollowing devices:

• dsPIC33CH64MP50X• dsPIC33CH128MP50X• dsPIC33CH64MP20X• dsPIC33CH128MP20X

Topics covered include:

• Section 1.0 “Device Overview”• Section 2.0 “Programming Overview”• Section 3.0 “Device Programming – ICSP”• Section 4.0 “Device Programming – Enhanced

ICSP”• Section 5.0 “The Programming Executive”• Section 6.0 “Device ID”• Section 7.0 “Checksum Computation”• Section 8.0 “AC/DC Characteristics and

Timing Requirements”

2.0 PROGRAMMING OVERVIEWThere are two methods of programming that arediscussed in this programming specification:

• In-Circuit Serial Programming™ (ICSP™)• Enhanced In-Circuit Serial Programming

The ICSP programming method is the most directmethod to program the device; it is also the slower of thetwo methods. It provides native, low-level programmingcapability to erase, program and verify the device.

The Enhanced In-Circuit Serial Programming(Enhanced ICSP) protocol uses a faster method thattakes advantage of the Programming Executive (PE), asillustrated in Figure 2-1. The Programming Executiveprovides all the necessary functionality to erase,program and verify the chip through a small commandset. The command set allows the programmer toprogram the dsPIC33CHXXXMP508 family deviceswithout having to deal with the low-level programmingprotocols of the chip.

FIGURE 2-1: PROGRAMMING SYSTEM OVERVIEW FOR ENHANCED ICSP™

This specification is divided into two major sections thatdescribe the programming methods independently.Section 3.0 “Device Programming – ICSP” describesthe In-Circuit Serial Programming method. Section 4.0“Device Programming – Enhanced ICSP” describesthe Enhanced In-Circuit Serial Programming (ICSP)method.

Programmer ProgrammingExecutive

On-Chip Memory

dsPIC33CHXXXMP50X/20X

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2.1 Required ConnectionsThese devices require specific connections forprogramming to take place. These connections includepower, MCLR and one programming pin pair (PGEDx/PGECx). Table 2-1 describes these connections (referto the specific device data sheet for pin descriptionsand power connection requirements).

2.2 Power RequirementsAll devices in the dsPIC33CHXXXMP508 family powertheir core digital logic at a nominal 1.2V. All devices inthe dsPIC33CHXXXMP508 family incorporate acapless on-chip regulator that allows the device to runits core logic from VDD. The regulator provides powerto the core from the other VDD pins and does notrequire an external CPU Logic Filter Capacitor (VCAP)connection.

The specifications for core voltage are listed inSection 8.0 “AC/DC Characteristics and TimingRequirements”.

FIGURE 2-2: CONNECTIONS FOR THE ON-CHIP REGULATOR

TABLE 2-1: PINS USED DURING PROGRAMMING

VDD

VSS

3.3V

AVDD

AVSS

dsPIC33CHXXXMP50X/20X

Pin Name Pin Type Pin Description

MCLR I Programming EnableVDD and AVDD(1) P Power Supply(1)

VSS and AVSS(1) P Ground(1)

PGECx I Programming Pin Pair: Serial Clock PGEDx I/O Programming Pin Pair: Serial Data Legend: I = Input O = Output P = PowerNote 1: All power supply and ground pins must be connected, including AVDD and AVSS.

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2.3 Pin DiagramsFigure 2-3 through Figure 2-8 show the pin diagramsfor the dsPIC33CHXXXMP508 family. The pins that arerequired for programming are listed in Table 2-1 andare indicated in bold text in the figures. Refer to theappropriate device data sheet for complete pindescriptions.

2.3.1 PGECx AND PGEDx PIN PAIRSAll devices in the dsPIC33CHXXXMP508 family havethree separate pairs of programming pins, labeled asPGEC1/PGED1, PGEC2/PGED2 and PGEC3/PGED3.Any one of these pin pairs may be used for deviceprogramming by either ICSP or Enhanced ICSP. Unlikevoltage supply and ground pins, it is not necessary toconnect all three pin pairs to program the device.However, the programming method must use both pinsof the same pair.

FIGURE 2-3: PIN DIAGRAMS

28-Pin SSOP

RA1

VSS

PGEC2/RB4

RA2RA3

RA0MCLR

RA4

PGEC3/RB6

PGED2/RB3RB2

VSSRB1RB0 VDD

RB7

PGEC1/RB9PGED1/RB8

VDDAVSSAVDD

1234567891011121314

2827262524232221201918171615

RB15RB14RB13RB12

RB10RB11

PGED3/RB5

dsPI

C33

CH

64M

P502

/202

dsPI

C33

CH

128M

P502

/202

Legend: Bold indicates pins used in device programming.

= Pins are up to 5V tolerant

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FIGURE 2-4: PIN DIAGRAMS (CONTINUED)

28-Pin UQFN 6x6 mm

28 27 26 25 24 23 22

8 9 10 11 12 13 14

318171615

45

7

12 20

19

6

21AV

DD

MCLRRA0RA1RA2RA3

PGED1/RB8RB7PGEC3/RB6PGED3/RB5PGEC2/RB4PGED2/RB3RB2

RB14RB15

dsPIC33CH64MP502/202dsPIC33CH128MP502/202

RA

4

AVSS

VDD

VSS

RB

0R

B1

PGEC

1/R

B9

VSS

VDD

RB

10R

B11

RB1

2R

B13

Legend: Bold indicates pins used in device programming.

= Pins are up to 5V tolerant

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FIGURE 2-5: PIN DIAGRAMS (CONTINUED)

36-Pin UQFN 5x5 mm

36 35 34 33 32 31 30

10 11 12 13 14 15 16

3

22

21

20

19

4

5

7

1

2

24

23

6

25

8

917 18

26

272829

dsPIC33CH64MP503/203dsPIC33CH128MP503/203

RB14RB15

MCLRRC0RA0RA1RA2

RA3RA4

AVD

D

AVSS

RC

1R

C2

VDD

VSS

RC

3R

B0

RB2PGED2/RB3PGEC2/RB4VSSVDDPGED3/RB5PGEC3/RB6RB7PGED1/RB8

PGEC

1/R

B9R

C4

RC

5VS

S

VDD

RB

10R

B11

RB

12R

B13

RB

1

Legend: Bold indicates pins used in device programming.

= Pins are up to 5V tolerant

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FIGURE 2-6: PIN DIAGRAMS (CONTINUED)

48-Pin TQFP 7x7 mm/UQFN 6x6 mm

46 45 44 43 42 41 40 39 38

13 14 15 16 17 18 19 20 21 22

3

32

31

30

29

28

27

26

25

4

5

7

8

9

10

11

1

2

34

33

6

23

35

3747

1224

36

48

MCLR

dsPIC33CH64MP505/205dsPIC33CH128MP505/205

RB14RB15RC12RC13

RD13RC0RA0RA1RA2RA3RA4

AVD

D

AVSS

RC

1R

C2

RC

6VD

D

VSS

RC

3R

B0

RB

1R

D10

RC

7

RB2PGED2/RB3PGEC2/RB4RC8RC9RD8VssVDDPGED3/RB5PGEC3/RB6RB7PGED1/RB8

PGEC

1/R

B9R

C4

RC

5R

C10

RC

11VS

S

VDD

RD

1R

B10

RB1

1R

B12

RB1

3

Legend: Bold indicates pins used in device programming.

= Pins are up to 5V tolerant

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FIGURE 2-7: PIN DIAGRAMS (CONTINUED)

RB14RB15RC12RC13

MCLR

RC0RA0RA1RA2

RC14RC15

RD15VSSVDD

RD14RD13

64-Pin TQFP 10x10 mm/QFN 9x9 mm

2345678910111213141516

4847

22

44

24 25 26 27 28 29 30 31 32

1

4645

23

4342414039

63 62 61 5960 58 57 56 5455 53 52 51 4950

3837

34

3635

33

17 19 20 211864

RA

4A

VDD

AVS

S

RC

1R

D12

RA

3

RC

2R

C6

VDD

VSS

RC

3R

B0

RB

1R

D11

RD

10R

C7

RB2PGED2/RB3PGEC2/RB4RC8RC9RD9RD8VssVDDRD7RD6RD5PGED3/RB5PGEC3/RB6RB7PGED1/RB8

PGEC

1/R

B9

RC

4R

C5

RC

10R

C11

RD

4R

D3

V SS

VDD

RD

2R

D1

RD

0R

B10

RB

11R

B12

RB

13

dsPIC33CH64MP506/206dsPIC33CH128MP506/206

Legend: Bold indicates pins used in device programming.

= Pins are up to 5V tolerant

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FIGURE 2-8: PIN DIAGRAMS (CONTINUED)

80-Pin TQFP 12x12 mm

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65

1 602 593 584 575 566 557 548 539 5210 5111 5012 4913 4814 4715 4616 45

21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

17181920

37 38 39 40

44434241

64 63 62 61

dsPIC33CH64MP508/208dsPIC33CH128MP508/208

RB14RE0

RB15RE1

RC12RC13RC14RC15

MCLR

RA2RE3RA1RE2

RD15VSS

RA0RC0

RD13RD14

VDD

RA

3R

E4

RA

4R

E5

AVD

DAV

SSR

D12

RC

1R

C2

RC

6V D

DVS

SR

C3

RB

0R

B1

RD

11R

E6

RD

10R

E7

RC

7

RB2RE8PGED2/RB3RE9PGEC2/RB4RC8RC9RD9RD8VSSVDDRD7RD6RD5PGED3/RB5PGEC3/RB6RE10RB7RE11PGED1/RB8

PGEC

1/R

B9

RE

12R

C4

RE

13R

C5

RC

10R

C11

RD

4R

D3

V SS

VDD

RD

2R

D1

RD

0R

B10

RB

11R

E14

RB

12R

E15

RB

13

Legend: Bold indicates pins used in device programming.

= Pins are up to 5V tolerant

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2.4 Program Memory Write/Erase Requirements

The Master Flash program memory on thedsPIC33CHXXXMP508 devices has specific write/erase requirements that must be adhered to for properdevice operation.

Regardless of the method used to program the Flash,a few basic requirements should be met:

• A full 48-bit double instruction word should always be programmed to a Flash location. Either instruction may simply be a NOP to fulfill this requirement. This ensures a valid ECC value is generated for each pair of instructions written.

• Assuming the above step is followed, the last 24-bit location in implemented program space should never be executed. The penultimate instruction must contain a program flow change instruction, such as a RETURN or BRA instruction.

• Any given word in memory must not be written without first erasing the page in which it is located. Thus, the easiest way to conform to this rule is to write all the data in a programming block within one write cycle.

The programming methods specified in this documentcomply with these requirements.

2.5 Memory MapThe Master Flash program memory map extends from000000h to FFFFFEh. Code memory is located at thestart of the memory map. The last locations of imple-mented code memory are reserved for the deviceConfiguration bits.

Table 2-2 lists the code memory size, the number of thewrite blocks and the number of erase blocks present ineach device variant.

Locations, 800000h through 800FFEh, are reserved forexecutive code memory. This region stores theProgramming Executive and the debugging executive.The Programming Executive is used for device program-ming and the debugging executive is used for in-circuitdebugging. This region of memory cannot be used tostore user code. See Section 5.0 “The ProgrammingExecutive” for more information. The special latchesused for device programming are located in the memory,from FA0000h through FA0002h. See Section 3.7“Writing Code Memory”.Locations, FF0000h and FF0002h, are reserved for theDevice ID registers. These bits can be used by theprogrammer to identify which device type is beingprogrammed. They are described in Section 6.0“Device ID”. The Device ID registers read outnormally, even after code protection is applied.

The locations, 801700h-8017FEh, are a One-Time-Programmable (OTP) memory area. This area isdescribed in more detail in Section 2.7 “User OTP(One-Time-Programmable) Memory”.Figure 2-9 through Figure 2-10 show a generic memorymap for all devices. See the “Memory Organization”chapter in the specific device data sheet for moreinformation.

Note: A program memory bit can beprogrammed from ‘1’ to ‘0’ only.

TABLE 2-2: CODE MEMORY SIZE

Device Family User Memory

Limit (Instruction Word)

Write Blocks/No. of Rows

Erase Blocks/No. of Pages

dsPIC33CH64MP50X/20X 00AFFEh (22528) 176 22

dsPIC33CH128MP50X/20X 015FFEh (45056) 352 44

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FIGURE 2-9: MASTER FLASH PROGRAM MEMORY MAP FOR dsPIC33CH64MP50X/20X DEVICES(1)

0x000000

CodeFlash Memory

0x00AF00

(22k Instruction)

0x800000

DEVID

0xFEFFFE0xFF0000

0xFFFFFE

Unimplemented(Read ‘0’s)

Reserved

0x7FFFFE

Con

figur

atio

n M

emor

y Sp

ace

Cod

e M

emor

y Sp

ace

Device Configuration

0x00B0000x00AFFE

Reserved0xFF00020xFF0004

Executive Code Memory

0x8018000x8017FE

OTP Memory

0xF9FFFE0xFA00000xFA00020xFA0004

Write Latches

Reserved

0x8016FCCalibration Data(2,3)

0x800FFE0x801000

0x00AEFE

0x801700

Note 1: Memory areas are not shown to scale.2: Calibration data area must be maintained during programming.3: Calibration data area includes UDID locations.

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FIGURE 2-10: MASTER FLASH PROGRAM MEMORY MAP FOR dsPIC33CH128MP50X/20X DEVICES(1)

0x000000

CodeFlash Memory

0x015F000x015EFE

(44k Instructions)

0x800000

0xFA0000Write Latches

0xFA00020xFA0004

DEVID

0xFEFFFE0xFF0000

0xFFFFFE

0xF9FFFE

Unimplemented(Read ‘0’s)

Reserved

0x7FFFFE

ReservedCon

figur

atio

n M

emor

y Sp

ace

Cod

e M

emor

y Sp

ace

0x0160000x015FFE

Reserved

0xFF00020xFF0004

Executive Code Memory

0x8018000x8017FE

OTP Memory

Device Configuration

0x8016FCCalibration Data(2,3)

0x800FFE0x801000

0x801700

Note 1: Memory areas are not shown to scale.2: Calibration data area must be maintained during programming.3: Calibration data area includes UDID locations.

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2.6 Configuration Bits2.6.1 OVERVIEWThe Configuration bits are stored in the last pagelocation of implemented code memory. These bits canbe set or cleared to select various device configura-tions. The system operation bits for both the Masterand Slave cores are stored here, and determine thepower-on system-level settings for each core. Thesebits include settings for oscillator selection, pin owner-ship and Master/Slave Mailbox register configuration.There are code protection Configuration bits that canbe used to prevent the Master Flash program memoryfrom being read and written.

Table 2-3 lists the Configuration register address rangefor each device. Table 2-4 provides the Configurationregisters map. Refer to the “Special Features”chapter in the specific device data sheet for moreinformation.

2.6.2 CODE-PROTECT CONFIGURATION BITS

The devices implement an intermediate securityfeature defined by the FSEC register. The BootSegment (BS) is the highest privileged segment and theGeneral Segment (GS) is the lowest privilegedsegment. The total user code memory can be split intoBS or GS. The size of the segments is determined bythe BSLIM[12:0] bits. The relative location of the seg-ments within user space does not change, such that theBS (if present) occupies the memory area just after theInterrupt Vector Table (IVT) and the GS occupies thespace just after BS.

The Configuration Segment (or CS) is a small segment(less than a page, typically just one row) within the codememory address space that contains all userconfiguration data.

TABLE 2-3: CONFIGURATION WORD ADDRESSES

Register 64k Address 128k Address

Master/General Configuration Registers

FSEC 00AF00 015F00FBSLIM 00AF10 015F10FSIGN 00AF14 015F14FOSCSEL 00AF18 015F18FOSC 00AF1C 015F1CFWDT 00AF20 015F20FPOR 00AF24 015F24FICD 00AF28 015F28FDMTIVTL 00AF2C 015F2CFDMTIVTH 00AF30 015F30FDMTCNTL 00AF34 015F34FDMTCNTH 00AF38 015F38FDMT 00AF3C 015F3CFDEVOPT 00AF40 015F40FALTREG 00AF44 015F44FMBXM 00AF48 015F48FMBXHS1 00AF4C 015F4CFMBXHS2 00AF50 015F50FMBXHSEN 00AF54 015F54FCFGPRA0 00AF58 015F58FCFGPRB0 00AF60 015F60FCFGPRC0 00AF68 015F68FCFGPRD0 00AF70 015F70FCFGPRE0 00AF78 015F78

Slave Configuration Registers

FS1OSCSEL 00AF80 015F80FS1OSC 00AF84 015F84FS1WDT 00AF88 015F88FS1POR 00AF8C 015F8CFS1ICD 00AF90 015F90FS1DEVOPT 00AF94 015F94FS1ALTREG 00AF98 015F98

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TAR Bit 3 Bit 2 Bit 1 Bit 0

FS BSEN BSS[1:0] BWRP

FB

FS — — — —

FO — FNOSC[2:0]

FO — OSCIOFNC POSCMD[1:0]

FW RWDTPS[4:0]

FP — — — —

FIC — — ICS[1:0]

FD

FD

FD

FD

FD — — — DMTDIS

FD 2 ALTI2C1 r(1) — —

FA — CTXT1[2:0]

FM

FM MBXHSA[3:0]

FM MBXHSE[3:0]

FM HSDEN HSCEN HSBEN HSAEN

FC CPRA[4:0]

FC

FC

FC

FC

FS — S1FNOSC[2:0]

FS — S1OSCIOFNC — —

FS S1RWDTPS[4:0]

FS — — — —

FS — — S1ICS[1:0]

FS S1ALTI2C1 — — —

FS — S1CTXT1[2:0]

LeNo

BLE 2-4: CONFIGURATION REGISTERS MAPegister Name

Bits 23-16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4

Master/General Configuration RegistersEC — AIVTDIS — — — CSS[2:0] CWRP GSS[1:0] GWRP —

SLIM — — — — BSLIM[12:0]

IGN — r(2) — — — — — — — — — — —

SCSEL — — — — — — — — — IESO — — —

SC — — — — XTBST XTCFG[1:0] — — FCKSM[1:0] — —

DT — FWDTEN SWDTPS[4:0] WDTWIN[1:0] WINDIS RCLKSEL[1:0]

OR — — — — — — r(1) — — — — r(1) r(1)

D — — — — — — — — — r(1) — JTAGEN —

MTIVTL — DMTIVTL[15:0]

MTIVTH — DMTIVTH[15:0]

MTCNTL — DMTCNTL[15:0]

MTCNTH — DMTCNTH[15:0]

MT — — — — — — — — — — — — —

EVOPT — — — SPI2PIN — — SMBEN MAXTEMP[1:0] r(1) — — ALTI2C

LTREG — — CTXT4[2:0] — CTXT3[2:0] — CTXT2[2:0]

BXM — MBXM[15:0]

BXHS1 — MBXHSD[3:0] MBXHSC[3:0] MBXHSB[3:0]

BXHS2 — MBXHSH[3:0] MBXHSG[3:0] MBXHSF[3:0]

BXHSEN — — — — — — — — — HSHEN HSGEN HSFEN HSEEN

FGPRA0 — — — — — — — — — — — —

FGPRB0 — CPRB[15:0]

FGPRC0 — CPRC[15:0]

FGPRD0 — CPRD[15:0]

FGPRE0 — CPRE[15:0]

Slave Configuration Registers1OSCSEL — — — — — — — — — S1IESO — — —

1OSC — — — — — — — — — S1FCKSM[1:0] — —

1WDT — S1FWDTEN S1SWDTPS[4:0] S1SDTWIN[1:0] S1WINDIS S1RCLKSEL[1:0]

1POR — — — — — r(1) — — — — — —

1ICD — S1NOBTSWP — S1ISOLAT — — — — — r(1) — — —

1DEVOPT — S1MSRE S1SSRE S1SPI1PIN — — — — — — — — —

1ALTREG — — S1CTXT4[2:0] — S1CTXT3[2:0] — S1CTXT2[2:0]

gend: — = unimplemented bit, read as ‘1’; r = Reserved bitte 1: Bit reserved, maintain as ‘1’.

2: Bit reserved, maintain as ‘0’.

dsPIC33CHXXXMP508 FAMILY

2.7 User OTP (One-Time-Programmable) Memory

The dsPIC33CHXXXMP508 family devices contain 64One-Time-Programmable (OTP) double words, locatedat addresses, 801700h through 8017FEh. Each 48-bitOTP double word can only be written one time.

The OTP Words can be used for storing checksums,code revisions, manufacturing dates, manufacturing lotnumbers or any other application-specific information.For more information regarding OTP programming,please refer to section Section 3.9 “Writing OTPWords”.

Note: The OTP area is not cleared by anyerase command. This memory can bewritten only once.

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3.0 DEVICE PROGRAMMING – ICSPICSP mode is a special programming protocol thatallows you to read and write to the device memory ofthe dsPIC33CHXXXMP508 devices. The ICSP modeis the most direct method used to program the device,which is accomplished by applying control codes andinstructions, serially to the device, using the PGECxand PGEDx pins. ICSP mode also has the ability toread the contents of the executive memory to deter-mine if the Programming Executive is present, and towrite the Programming Executive to executive memoryif it is missing and then, Enhanced ICSP mode will beused.

In ICSP mode, the system clock is taken from thePGECx pin, regardless of the device’s Oscillator Con-figuration bits. All instructions are shifted serially into aninternal buffer, then loaded into the Instruction Register(IR) and executed. No program fetching occurs frominternal memory. Instructions are fed in 24 bits at atime. PGEDx is used to shift data in, and PGECx isused as both the serial shift clock and the CPUexecution clock.

3.1 Overview of the Programming Process

Figure 3-1 shows a high-level overview of the ICSPprogramming process. After entering ICSP mode, thefirst action is to Bulk Erase the code memory. Next, thecode memory is programmed, followed by the deviceConfiguration bits. Code memory (including the Config-uration bits) is then verified to ensure that programmingwas successful. Then, programming the code-protectConfiguration bits can be done if required.

FIGURE 3-1: HIGH-LEVEL ICSP™ PROGRAMMING FLOW

Note 1: During ICSP operation, the operatingfrequency of PGECx must not exceed5 MHz.

2: ICSP mode is slower than EnhancedICSP mode for programming.

Start

Perform BulkErase of Code Memory

Program Code Memory,

Verify Code Memory,

End

Enter ICSP™

Program Code-Protect

Exit ICSP

Configuration Wordsand OTP Words

Configuration Wordsand OTP Words

Configuration Bits

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3.2 Entering ICSP ModeAs shown in Figure 3-2, entering ICSP Program/Verifymode requires three steps:

1. MCLR is briefly driven high, then low (P21).2. A 32-bit key sequence is clocked into PGEDx.

The interval of at least P18 must elapse beforepresenting the key sequence on PGEDx.

3. MCLR is held low during a specified period, P19,and then driven high.

4. After a P7 + 5 * P1 delay, five clock pulses mustbe generated on the PGECx pin.

The key sequence is a specific 32-bit pattern,‘0100 1101 0100 0011 0100 1000 0101 0001’(more easily remembered as 4D434851h inhexadecimal). The device will enter ICSP mode only ifthe sequence is valid. The Most Significant bit (MSb) ofthe most significant nibble must be shifted in first.

On successful entry, the program memory can beaccessed and programmed in serial fashion.

FIGURE 3-2: ENTERING ICSP™ MODE

3.3 ICSP OperationUpon entry into ICSP mode, the CPU is Idle. Executionof the CPU is governed by an internal state machine. A4-bit control code must be clocked in using PGECx andPGEDx, and this control code is used to command theCPU (see Table 3-1).

The SIX control code is used to send instructions to theCPU for execution and the REGOUT control code isused to read data out of the device through the VISIregister.

TABLE 3-1: CPU CONTROL CODES IN ICSP™ MODE

Note: If a capacitor is present on the MCLR pin, thehigh time for entering ICSP mode can vary.

MCLR

PGEDx

PGECx

VDD

P6

P14

b31 b30 b29 b28 b27 b2 b1 b0b3...

Program/Verify Entry Code = 4D434851h

P1AP1B

P18

P19

0 1 0 0 1 0 0 0 1

P7VDD VDD

P21P1 * 5

1 2 3 4 5

4-Bit Control Code Mnemonic Description

0000 SIX Shift in 24-bit instruction and execute.

0001 REGOUT Shift out the VISIregister.

0010-1111 N/A Reserved.

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3.3.1 SIX SERIAL INSTRUCTION EXECUTION

The SIX control code allows execution of thedsPIC33 family assembly instructions. When the SIXcode is received, the CPU is suspended for 24 clockcycles, as the instruction is then clocked into the inter-nal buffer. Once the instruction is shifted in, the statemachine allows it to be executed over the next four

PGECx clock cycles. While the received instruction isexecuted, the state machine simultaneously shifts inthe next 4-bit command (see Figure 3-4).

FIGURE 3-3: SIX SERIAL EXECUTION

3.3.1.1 Differences Between Execution of SIX and a Normal Instruction

There are some differences between executing instruc-tions normally and using the ICSP SIX command. As aresult, the code examples in this specification may notmatch those for performing the same functions duringnormal device operation.

The important differences are:

• Two-word instructions require two SIX operationsto clock in all of the necessary data. Examples of two-word instructions are GOTO andCALL.

• Two-cycle instructions require two SIX operationsto complete. The first SIX operation shifts in the instruction andbegins to execute it. A second SIX operation, whichshould shift in a NOP to avoid losing data, providesthe CPU clocks required to finish executing theinstruction. Examples of two-cycle instructions are Table Read(TBLRD) and Table Write (TBLWT) instructions.

• Must provide NOP instruction during Stall toaccount for pipeline changes.A CPU Stall occurs when an instruction modifies aregister that is used for Indirect Addressing by theinstruction immediately following the CPU Stall.During normal operation, the CPU will automati-cally force a NOP while the new data are read.While using ICSP, the CPU stalls under the sameconditions, but an instruction needs to be providedto generate the clocks to get through the Stall

cycle. Therefore, any indirect references to arecently modified register should be preceded witha NOP.For example, the instructions, MOV #0x0, W0,followed by, MOV[W0], W1, must have a NOPinserted in between. If a two-cycle instruction modifies a register, which isused indirectly, it will require two following NOPs: oneto execute the second half of the instruction and theother NOP stalls the CPU to correct the pipeline. For example, instructions such as, TBLWTL [W0++],[W1], should be followed by 2 NOPs.

• The device Program Counter (PC) continues toautomatically increment during ICSP instructionexecution, even though the Flash memory is notbeing used. As a result, the PC may be incrementedso that it points to invalid memory locations. Examples of invalid memory spaces are unimple-mented Flash addresses or the vector space(location: 0x0 to 0x1FF). If the PC points to these locations, the device willreset, possibly interrupting the ICSP operation. Toprevent this, instructions should be periodicallyexecuted to reset the PC to a safe space. Theoptimal method of achieving this is to perform a“GOTO 0x200” instruction.

Note: Data bits on PGEDx are latched on therising edge of the PGECx clock.

P4

2 3 1 2 3 23 24 1 2 3 4

P1

PGECxP4A

PGEDx

24-Bit Instruction FetchExecute PC – 1,

1

0 0

Fetch SIX

4 5 6 7 8 18 19 20 21 2217

LSb X X X X X X X X X X X X X X MSb

PGEDx = Input

P2

P3P1B

P1A

0 0 0 0

Control Code

4

0 0

Execute 24-BitInstruction, Fetch

Next Control Code

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3.3.2 REGOUT SERIAL INSTRUCTIONEXECUTION

The REGOUT control code allows for data to beextracted from the device in ICSP mode. It is used toclock the contents of the VISI register, out of the device,over the PGEDx pin. After the REGOUT control code isreceived, the CPU is held Idle for eight cycles. Afterthese eight cycles, an additional 16 cycles are requiredto clock the data out (see Figure 3-4).

The REGOUT code is unique as the PGEDx pin is aninput when the control code is transmitted to thedevice. However, after the control code is processed,the PGEDx pin becomes an output as the VISI registeris shifted out.

FIGURE 3-4: REGOUT SERIAL EXECUTION

Note 1: After the contents of VISI are shifted out,the dsPIC33CHXXXMP508 devices main-tain PGEDx as an output until the first risingedge of the next clock is received.

2: Data changes on the falling edge andlatches on the rising edge of PGECx.For all data transmissions, the LeastSignificant bit (LSb) is transmitted first.

1 2 3 4 1 2 7 8PGECx

P4

PGEDx

PGEDx = Input

Execute Previous Instruction, CPU Held in Idle Shift Out VISI Register[15:0]

P5

PGEDx = Output

1 2 3 1 2 3 4

P4A

11 13 15 161412

No Execution Takes Place,Fetch Next Control Code

0 0 0 0 0

PGEDx = Input

MSb1 2 3 41

4 5 6

LSb 141312... 11100

Fetch REGOUT Control Code

0

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3.4 Flash Memory Programming in ICSP Mode

3.4.1 PROGRAMMING OPERATIONSFlash memory write and erase operations arecontrolled by the NVMCON register. Programming isperformed by setting NVMCON to select the typeof erase operation (Table 3-2) or write operation(Table 3-3) and initiating the programming by settingthe WR control bit (NVMCON[15]).

The PGECx clock is required to complete theprogramming operation. The WR control bit is clearedby hardware when the operation is finished. Refer toSection 8.0 “AC/DC Characteristics and TimingRequirements” for detailed information about themaximum time required for various programmingoperations.

TABLE 3-2: NVMCON ERASE OPERATIONS

TABLE 3-3: NVMCON WRITE OPERATIONS

3.4.2 STARTING AND STOPPING A PROGRAMMING CYCLE

For protection against accidental operations, the erase/write initiation sequence must be written to theNVMKEY register to allow any erase or program oper-ation to proceed. The two instructions following thestart of the programming sequence should be NOPs. Tostart an erase or write sequence, the following stepsmust be completed:

1. Write 55h to the NVMKEY register.2. Write AAh to the NVMKEY register.3. Set the WR bit in the NVMCON register.4. Execute three NOP instructions.The WR bit can be polled to generate enough clockcycles for the programming operation and to determineif the erase or write cycle has been completed.

NVMCONValue Erase Operation

400Eh Bulk Erase of user memory only (does not erase Device ID, Programming Executive memory and OTP Words).

4003h Page Erase of program or Programming Executive memory.

NVMCONValue Write Operation

4001h Double-word programming operation.

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REGISTER 3-1: NVMCON: NONVOLATILE MEMORY CONTROL REGISTER (REFERENCE ONLY)

R/SO-0(1) R/W-0(1) R/W-0(1) R/W-0 U-0 U-0 R/W-0 R/W-0WR WREN WRERR NVMSIDL(2) — — RPDF(6) URERR(6)

bit 15 bit 8

U-0 U-0 U-0 U-0 R/W-0(1) R/W-0(1) R/W-0(1) R/W-0(1)

— — — — NVMOP3(3,4) NVMOP2(3,4) NVMOP1(3,4) NVMOP0(3,4)

bit 7 bit 0

Legend: SO = Settable Only bitR = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 WR: Write Control Bit(1)

1 = Initiates a Flash memory program or erase operation; the operation is self-timed and the bit iscleared by hardware once the operation is complete

0 = The program or erase operation is complete and inactivebit 14 WREN: Write Enable bit(1)

1 = Enables Flash program or erase operations0 = Inhibits Flash program or erase operations

bit 13 WRERR: Write Sequence Error Flag bit(1)

1 = An improper program or erase sequence attempt, or termination has occurred (bit is set automaticallyon any set attempt of the WR bit)

0 = The program or erase operation completed normallybit 12 NVMSIDL: NVM Stop in Idle Control bit(2)

1 = Discontinues primary Flash operation when the device enters Idle mode0 = Continues primary Flash operation when the device enters Idle mode

bit 11-10 Unimplemented: Read as ‘0’bit 9 RPDF: Row Programming Data Format Control bit(6)

1 = Row data to be stored in RAM are in a compressed format0 = Row data to be stored in RAM are in an uncompressed format

bit 8 URERR: Row Programming Data Underrun Error Flag bit(6)

1 = Row programming operation has been terminated due to a data underrun error0 = No data underrun has occurred

bit 7-4 Unimplemented: Read as ‘0’

Note 1: These bits can only be reset on a POR.2: If this bit is set, there will be minimal power savings (IIDLE), and upon exiting Idle mode, there is a delay

(TVREG) before Flash memory becomes operational.3: All other combinations of NVMOP[3:0] are unimplemented.4: Execution of the PWRSAV instruction is ignored while any of the NVM operations are in progress.5: Two adjacent words on a 2-word boundary are programmed during execution of this operation.6: Not used in ICSP™ mode.

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bit 3-0 NVMOP[3:0]: NVM Operation Select bits(1,3,4)

1111 = Reserved 1110 = User memory Bulk Erase operation1101 = Reserved 1100 = Reserved 1011 = Reserved 1010 = Reserved 1001 = Reserved 1000 = Reserved 0111 = Reserved 0101 = Reserved 0100 = Reserved 0011 = Memory Page Erase operation0010 = Memory row program operation(6)0001 = Memory double-word operation(5)0000 = Reserved

REGISTER 3-1: NVMCON: NONVOLATILE MEMORY CONTROL REGISTER (REFERENCE ONLY) (CONTINUED)

Note 1: These bits can only be reset on a POR.2: If this bit is set, there will be minimal power savings (IIDLE), and upon exiting Idle mode, there is a delay

(TVREG) before Flash memory becomes operational.3: All other combinations of NVMOP[3:0] are unimplemented.4: Execution of the PWRSAV instruction is ignored while any of the NVM operations are in progress.5: Two adjacent words on a 2-word boundary are programmed during execution of this operation.6: Not used in ICSP™ mode.

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3.5 Erasing Program MemoryFigure 3-5 shows a high-level overview for the BulkErase of code memory.

Table 3-4 provides the ICSP programming process forerasing the program memory.

FIGURE 3-5: BULK ERASE FLOW

Note: Program memory must be erased beforewriting any data to program memory.

Start

End

Set the WR Bit to Initiate Erase

Write 400Eh to NVMCON SFR

Poll the WR Bit until it is Cleared

TABLE 3-4: SERIAL INSTRUCTION EXECUTION FOR BULK ERASE OF CODE MEMORY

Command(Binary)

Data(Hex) Description

Step 1: Exit the Reset vector.0000000000000000000000000000

000000000000000000040200000000000000000000

NOPNOPNOPGOTO 0x200NOPNOPNOP

Step 2: Set the NVMCON register to erase all user program memory.0000000000000000

2400EA88394A000000000000

MOV #0x400E, W10MOV W10, NVMCONNOPNOP

Step 3: Initiate the erase cycle.00000000000000000000000000000000

200551883971200AA1883971A8E729000000000000000000

MOV #0x55, W1MOV W1, NVMKEYMOV #0xAA, W1MOV W1, NVMKEYBSET NVMCON, #WRNOPNOPNOP

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3.6 Page EraseFigure 3-6 shows a high-level overview for erasing apage of code memory.

Table 3-5 provides the ICSP programming details forerasing a page of code memory.

FIGURE 3-6: PAGE ERASE FLOW

Step 4: Generate clock pulses for the code memory Bulk Erase operation to complete until the WR bit is clear.0000000000000000000000010000000000000000000000000000

—

000000803940000000887C40000000

000000000000000000040200000000000000000000

—

NOPMOV NVMCON, W0NOPMOV W0, VISINOPClock out contents of the VISI register.NOPNOPNOPGOTO 0x200NOPNOPNOPRepeat until the WR bit is clear.

TABLE 3-4: SERIAL INSTRUCTION EXECUTION FOR BULK ERASE OF CODE MEMORY (CONTINUED)

Command(Binary)

Data(Hex) Description

Note: For Page Erase operations, the NVMCONvalue must be modified as per Table 3-2.The NVMADR/U registers must point toany of the locations of the page to beerased.

Start

End

Set the WR Bit to Initiate Erase

Write 4003h to NVMCON SFR

Poll the WR Bit until it is Cleared

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TABLE 3-5: SERIAL INSTRUCTION EXECUTION FOR ERASING A PAGE OF CODE MEMORYCommand(Binary)

Data(Hex) Description

Step 1: Exit the Reset vector.0000000000000000000000000000

000000000000000000040200000000000000000000

NOPNOPNOPGOTO 0x200NOPNOPNOP

Step 2: Set the NVMADRU/NVMADR register pair to point to the correct page to be erased.0000000000000000

2xxxx32xxxx4883953883964

MOV #DestinationAddress, W3MOV #DestinationAddress, W4MOV W3, NVMADRMOV W4, NVMADRU

Step 3: Set the NVMCON register to erase the first page of executive memory.0000000000000000

24003A88394A000000000000

MOV #0x4003, W10MOV W10, NVMCONNOPNOP

Step 4: Initiate the erase cycle.00000000000000000000000000000000

200551883971200AA1883971A8E729000000000000000000

MOV #0x55, W1MOV W1, NVMKEYMOV #0xAA, W1MOV W1, NVMKEYBSET NVMCON, #WRNOPNOPNOP

Step 5: Generate clock pulses for the Page Erase operation to complete until the WR bit is clear.0000000000000000000000010000000000000000000000000000

—

000000803940000000887C40000000

000000000000000000040200000000000000000000

—

NOPMOV NVMCON, W0NOPMOV W0, VISINOPClock out contents of the VISI register.NOPNOPNOPGOTO 0x200NOPNOPNOPRepeat until the WR bit is clear.

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3.7 Writing Code MemoryFigure 3-8 shows a high-level overview for writing thecode memory.

Table 3-6 provides the ICSP programming details forwriting the code memory.

Code memory is written two instruction words at a time.Two words are loaded into the write latches, located atFA0000h and FA0002h, using the packed data formatshown in Figure 3-7. The destination address is loadedinto the NVMADR and NVMADRU registers. Next, thewrite cycle is initiated by setting the WREN bit in theNVMCON register. The WR bit in NVMCON will becleared in hardware once the double-word write iscomplete. This process is repeated for all memorylocations to be programmed.

FIGURE 3-7: PACKED INSTRUCTION WORD FORMAT

FIGURE 3-8: PROGRAM CODE MEMORY FLOW

15 8 7 0

LSW1

MSB2 MSB1

LSW2

LSWx: Least Significant 16 bits of instruction wordMSBx: Most Significant Byte of instruction word

Start

Configure Devicefor Writes

All DataWritten?

Yes

Initiate WriteSequence and Poll

WR bit to be Cleared

Load Two Words intoWrite Latches

IncrementWrite Pointer

End

No

Programming Using Two Write Latches

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TABLE 3-6: SERIAL INSTRUCTION EXECUTION FOR PROGRAMMING CODE MEMORY:TWO-WORD LATCH WRITES

Command(Binary)

Data(Hex) Description

Step 1: Exit the Reset vector.0000000000000000000000000000

000000000000000000040200000000000000000000

NOPNOPNOPGOTO 0x200NOPNOPNOP

Step 2: Initialize the TBLPAG register for writing to the latches.00000000

200FAC8802AC

MOV #0xFA, W12MOV W12, TBLPAG

Step 3: Load W0:W2 with the next two packed instruction words to program.000000000000

2xxxx02xxxx12xxxx2

MOV #, W0MOV #, W1MOV #, W2

Step 4: Set the Read Pointer (W6) and Write Pointer (W7), and load the (next set of) write latches.0000000000000000000000000000000000000000000000000000000000000000

EB0300000000EB0380000000BB0BB6000000000000BBDBB6000000000000BBEBB6000000000000BB0B96000000000000

CLR W6NOPCLR W7NOPTBLWTL [W6++], [W7] NOPNOPTBLWTH.B [W6++], [W7++] NOPNOPTBLWTH.B [W6++], [++W7] NOPNOPTBLWTL.W [W6], [W7] NOP NOP

Step 5: Set the NVMADRU/NVMADR register pair to point to the correct address.0000000000000000

2xxxx32xxxx4883953883964

MOV #DestinationAddress, W3MOV #DestinationAddress, W4MOV W3, NVMADRMOV W4, NVMADRU

Step 6: Set the NVMCON register to program two instruction words.00000000000000000000

24001A00000088394A000000000000

MOV #0x4001, W10NOPMOV W10, NVMCONNOPNOP

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Step 7: Initiate the write cycle.00000000000000000000000000000000

200551883971200AA1883971A8E729000000000000000000

MOV #0x55, W1MOV W1, NVMKEYMOV #0xAA, W1MOV W1, NVMKEYBSET NVMCON, #WRNOPNOPNOP

Step 8: Generate clock pulses for the program operation to complete until the WR bit is clear.0000000000000000000000010000000000000000000000000000

—

00000080394000000887C40000000

000000000000000000040200000000000000000000

—

NOPMOV NVMCON, W0NOPMOV W0, VISINOPClock out contents of the VISI register.NOPNOPNOPGOTO 0x200NOPNOPNOPRepeat until the WR bit is clear.

Step 9: Repeat Steps 3-8 until all code memory is programmed.

TABLE 3-6: SERIAL INSTRUCTION EXECUTION FOR PROGRAMMING CODE MEMORY:TWO-WORD LATCH WRITES (CONTINUED)

Command(Binary)

Data(Hex) Description

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3.8 Writing Configuration BitsThe procedure for writing Configuration bits is similar tothe procedure for writing code memory.

To change the values of the Configuration bits once theyhave been programmed, the device must be erased, asdescribed in Section 3.5 “Erasing Program Memory”,and reprogrammed to the desired value.

Table 3-7 provides the ICSP programming details forwriting the Configuration bits.

The code protection can be enabled by programming‘0’ in the code protection Configuration bits. In order toverify the data by reading the Configuration bits afterperforming the write, the code protection bits shouldinitially be programmed to ‘1’ to ensure that theverification can be performed properly. After verificationis finished, the code protection bits can be programmedto ‘0’ by using a word write to the appropriateConfiguration register.

TABLE 3-7: SERIAL INSTRUCTION EXECUTION FOR WRITING CONFIGURATION WORDS

Command(Binary)

Data(Hex) Description

Step 1: Exit the Reset vector.0000000000000000000000000000

000000000000000000040200000000000000000000

NOPNOPNOPGOTO 0x200NOPNOPNOP

Step 2: Initialize the TBLPAG register for writing to the latches.00000000

200FAC8802AC

MOV #0xFA, W12MOV W12, TBLPAG

Step 3: Load W0:W1 with the next two Configuration Words to program.0000000000000000

2xxxx02xxxx12xxxx22xxxx3

MOV #, W0MOV #, W1MOV #, W2MOV #, W3

Step 4: Set the Write Pointer (W3) and load the write latches.00000000000000000000000000000000000000000000000000000000

EB0300000000BB0B00000000000000BB9B01000000000000BB0B02000000000000BB9B03000000000000

CLR W6NOPTBLWTL W0, [W6]NOPNOPTBLWTH W1, [W6++]NOPNOPTBLWTL W2, [W6]NOPNOPTBLWTH W3, [W6++]NOPNOP

Step 5: Set the NVMADRU/NVMADR register pair to point to the correct Configuration Word address.0000000000000000

2xxxx42xxxx5883954883965

MOV #DestinationAddress, W4MOV #DestinationAddress, W5MOV W4, NVMADRMOV W5, NVMADRU

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Step 6: Set the NVMCON register to program two instruction words.00000000000000000000

24001A00000088394A000000000000

MOV #0x4001, W10NOPMOV W10, NVMCONNOPNOP

Step 7: Initiate the write cycle.0000000000000000000000000000000000000000

200551883971200AA1883971A8E729000000000000000000000000000000

MOV #0x55, W1MOV W1, NVMKEYMOV #0xAA, W1MOV W1, NVMKEYBSET NVMCON, #WRNOPNOPNOPNOPNOP

Step 8: Generate clock pulses for the program operation to complete until the WR bit is clear.0000000000000000000000010000000000000000000000000000

—

000000803940000000887C40000000

000000000000000000040200000000000000000000

—

NOPMOV NVMCON, W0NOPMOV W0, VISINOPClock out contents of the VISI register.NOPNOPNOPGOTO 0x200NOPNOPNOPRepeat until the WR bit is clear.

Step 9: Repeat Steps 3-8 until all Configuration registers are programmed.

TABLE 3-7: SERIAL INSTRUCTION EXECUTION FOR WRITING CONFIGURATION WORDS (CONTINUED)

Command(Binary)

Data(Hex) Description

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3.9 Writing OTP WordsThe procedure for writing to user OTP memory is similarto the procedure for writing to user program memory,except that each of the 64 OTP double words can only bewritten once. Both words in each OTP location must bewritten together using the same two-word latch writeprocess used to write code memory.

Writing anything, with the exception of all ‘1’s, to an OTPlocation generates an ECC checksum and renders thatlocation used. Attempting to write to an OTP location thathas already been programmed will cause an ECCchecksum error the next time that location is read. Careshould be taken to avoid writing to OTP locations thathave already been programmed or may need to beprogrammed at a later time. See Figure 2-9 andFigure 2-10 for the location of user OTP memory.

Figure 3-9 shows a high-level overview of the OTPprogramming process.

FIGURE 3-9: OTP PROGRAMMING PROCESS

3.10 Reading OTP WordsThe procedure for reading OTP Words is similar to theprocedure for reading code memory. Since there aremultiple OTP Words, they are read one at a time.

3.11 Reading Code MemoryReading from code memory is performed by executinga series of TBLRD instructions and clocking out the datausing the REGOUT command.Table 3-8 provides the ICSP programming details forreading code memory.

To minimize reading time, the same packed data formatthat the write procedure uses is utilized. SeeSection 3.7 “Writing Code Memory” for more detailson the packed data format.

No

Start

Data to beWritten to

OTP?

Do not Writeto OTP Memory

No

Yes

Read (next) OTPLocation to be

Written

No

Yes

Do not Writeto OTP Memory

OTPLocation

Read All ‘1’s?

Write Datato OTP Location

Yes

All DataWritten?

END

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TABLE 3-8: SERIAL INSTRUCTION EXECUTION FOR READING CODE MEMORYCommand

(Binary)Data(Hex) Description

Step 1: Exit the Reset vector.0000000000000000000000000000

000000000000000000040200000000000000000000

NOPNOPNOPGOTO 0x200NOPNOPNOP

Step 2: Initialize the TBLPAG register and the Read Pointer (W6) for the TBLRD instruction.000000000000

200xx08802A02xxxx6

MOV #, W0MOV W0, TBLPAGMOV #, W6

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Step 3: Initialize the Write Pointer (W7) and store the next four locations of code memory to W0:W5.00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000

EB0380000000BA1B96000000000000000000000000000000BADBB6000000000000000000000000000000BADBD6000000000000000000000000000000BA1BB6000000000000000000000000000000BA1B96000000000000000000000000000000BADBB6000000000000000000000000000000BADBD6000000000000000000000000000000BA0BB6000000000000000000000000000000

CLR W7 NOPTBLRDL [W6], [W7++] NOPNOPNOPNOPNOPTBLRDH.B [W6++], [W7++] NOPNOPNOPNOPNOPTBLRDH.B [++W6], [W7++] NOPNOPNOPNOPNOPTBLRDL [W6++], [W7++] NOPNOPNOPNOPNOPTBLRDL [W6], [W7++] NOPNOPNOPNOPNOPTBLRDH.B [W6++], [W7++] NOPNOPNOPNOPNOPTBLRDH.B [++W6], [W7++] NOPNOPNOPNOPNOPTBLRDL [W6++], [W7] NOPNOPNOPNOPNOP

TABLE 3-8: SERIAL INSTRUCTION EXECUTION FOR READING CODE MEMORY (CONTINUED)Command

(Binary)Data(Hex) Description

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Step 4: Output W0:W5 using the VISI register and REGOUT command.000000000001000000000000000100000000000000010000000000000001000000000000000100000000000000010000

887C40000000

000000887C41000000

000000887C42000000

000000887C43000000

000000887C44000000

000000887C45000000

000000

MOV W0, VISI NOPClock out contents of the VISI register.NOPMOV W1, VISI NOPClock out contents of the VISI register.NOPMOV W2, VISI NOPClock out contents of the VISI register.NOPMOV W3, VISI NOPClock out contents of the VISI register.NOPMOV W4, VISI NOPClock out contents of the VISI register.NOPMOV W5, VISI NOPClock out contents of the VISI register.NOP

Step 5: Reset the device’s internal PC.0000000000000000000000000000

000000000000000000040200000000000000000000

NOPNOPNOPGOTO 0x200 NOPNOPNOP

Step 6: Repeat Steps 3-5 until all desired code memory is read.

TABLE 3-8: SERIAL INSTRUCTION EXECUTION FOR READING CODE MEMORY (CONTINUED)Command

(Binary)Data(Hex) Description

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3.12 Reading Configuration RegistersThe procedure for reading Configuration bits is similarto the procedure for reading code memory. Since thereare multiple Configuration Words, they are read one ata time.

Table 3-9 provides the ICSP programming details forreading the Configuration bits.

TABLE 3-9: SERIAL INSTRUCTION EXECUTION FOR READING CONFIGURATION WORDSCommand

(Binary)Data(Hex) Description

Step 1: Exit the Reset vector.0000000000000000000000000000

000000000000000000040200000000000000000000

NOPNOPNOPGOTO 0x200NOPNOPNOP

Step 2: Initialize the TBLPAG register, the Write Pointer (W7) and the Read Pointer (W6) for the TBLRD instruction.0000000000000000

200xx020F8878802A02xxxx6

MOV #, W0MOV #, W7MOV W0, TBLPAGMOV #, W6

Step 3: Store the Configuration register and send the contents of the VISI register.000000000000000000000000000000000000000000000000000000000001

000000BA8B96000000000000000000000000000000

BA0B96000000000000000000000000000000

NOPTBLRDH [W6], [W7] NOPNOPNOPNOPNOPClock out contents of the VISI register.TBLRDL [W6], [W7]NOPNOPNOPNOPNOPClock out contents of the VISI register.

Step 4: Repeat Steps 1-3 until all Configuration registers are read.

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3.13 Verify Code Memory and Configuration Bits

The verify step involves reading back the code memoryspace and comparing it against the copy held in theprogrammer’s buffer. The Configuration Words areverified with the rest of the code.

The verify process is shown in Figure 3-10. The lowerword of the instruction is read, and then the lowerbyte of the upper word is read and compared againstthe instruction stored in the programmer’s buffer.Refer to Section 3.11 “Reading Code Memory” forimplementation details of reading code memory.

FIGURE 3-10: VERIFY CODE MEMORY FLOW

3.14 Exiting ICSP ModeExiting Program/Verify mode is done by removingVDD from MCLR, as shown in Figure 3-11. The onlyrequirement for exit is that an interval, P16, shouldelapse between the last clock, and the program signalson PGECx and PGEDx before removing VDD.

FIGURE 3-11: EXITING ICSP™ MODE

Note: Because the Configuration Words includethe device code protection bit, codememory should be verified immediatelyafter writing if code protection is to beenabled. This is because the device willnot be readable or verifiable if a deviceReset occurs after the code-protect bithas been cleared.

Read Low Word

Read High Byte

Data?

AllCode Memory

Verified?

No

Yes

No

Start

Yes

End

with Post-Increment

with Post-Increment

FailureReport Error

DoesInstruction Word =

Expected

MCLR

P16

PGEDx = Input

PGECx

VDD

VDD

VDD

P17

PGEDx

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4.0 DEVICE PROGRAMMING – ENHANCED ICSP

This section discusses programming the device throughEnhanced ICSP and the Programming Executive. TheProgramming Executive resides in executive memory(separate from code memory) and is executed whenEnhanced ICSP Programming mode is entered. TheProgramming Executive provides the mechanism for theprogrammer (host device) to program and verify thedsPIC33CHXXXMP508 devices using a simple com-mand set and communication protocol. There are sev-eral basic functions provided by the ProgrammingExecutive:

• Read Memory• Erase Memory• Program Memory• Blank Check

The Programming Executive performs the low-leveltasks required for erasing, programming and verifyinga device. This allows the programmer to program thedevice by issuing the appropriate commands and data.A detailed description for each command is provided inSection 5.2 “Programming Executive Commands”.

4.1 Overview of the Programming Process

Figure 4-1 shows the high-level overview of theprogramming process. First, it must be determined ifthe Programming Executive is present in executivememory, then the Enhanced ICSP mode is entered.The program memory is then erased, and the programmemory and Configuration Words are programmedand verified. Last, the code-protect Configuration bitsare programmed (if required) and Enhanced ICSPmode is exited.

FIGURE 4-1: HIGH-LEVEL ENHANCED ICSP™ PROGRAMMING FLOW

Note: The PE uses the device’s data RAM forvariable storage and program execution.After running the PE, no assumptionsshould be made about the contents ofdata RAM.

Start

End

Program Memory,

Verify Program Memory,

Erase

Program Code-Protect

Exit Enhanced ICSP

Confirm Presence of

Enter Enhanced

Configuration Words

Configuration Bits

Programming Executive

ICSP™ Mode

Program Memory

Configuration Wordsand User OTP Words

and User OTP Words

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4.2 Confirming the Presence of the Programming Executive

Before programming can begin, the programmer mustconfirm that the Programming Executive is stored inexecutive memory. The procedure for this task isshown in Figure 4-2.

First, In-Circuit Serial Programming (ICSP) mode isentered. Then, the unique Application ID Word storedin executive memory is read. If the ProgrammingExecutive is resident, the correct Application ID Word,0xDF, is read and programming can resume as normal.However, if the Application ID Word is not present,the PE must be programmed to executive codememory using the method described in Section 5.0“The Programming Executive”.Section 3.0 “Device Programming – ICSP” describesthe ICSP programming method. Section 4.3 “Readingthe Application ID Word” describes the procedure forreading the Application ID Word in ICSP mode.

FIGURE 4-2: CONFIRMING PRESENCE OF PROGRAMMING EXECUTIVE

Is

Start

Enter ICSP™ Mode

Application IDPresent?

Yes

No

Application IDCheck the

be ProgrammedProg. Executive must

by Reading Address,800BFEh

End

Exit ICSP Mode

Enter Enhanced

Sanity Check

ICSP Mode

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4.3 Reading the Application ID WordThe Application ID Word is stored at the address,800BFEh, in executive code memory. To read thismemory location you must use the SIX control code tomove this program memory location to the VISI regis-ter. Then, the REGOUT control code must be used toclock the contents of the VISI register out of the device.The corresponding control and instruction codes thatmust be serially transmitted to the device to performthis operation are provided in Table 4-1.

After the programmer has clocked out the ApplicationID Word, it must be inspected. If the Application IDhas the value, 0xDF, the Programming Executive isresident in memory and the device can be programmedusing the mechanism described in Section 4.0 “DeviceProgramming – Enhanced ICSP”. However, if theApplication ID has any other value, the ProgrammingExecutive is not resident in memory; it must be loadedinto memory before the device can be programmed.The procedure for loading the ProgrammingExecutive to memory is described in Section 5.0 “TheProgramming Executive”.

TABLE 4-1: SERIAL INSTRUCTION EXECUTION FOR READING THE APPLICATION ID WORDCommand(Binary)

Data(Hex) Description

Step 1: Exit the Reset vector.0000000000000000000000000000

000000000000000000040200000000000000000000

NOPNOPNOPGOTO 0x200NOPNOPNOP

Step 2: Initialize the TBLPAG register and the Read Pointer (W0) for the TBLRD instruction.00000000000000000000000000000000000000000000

2008008802A020BFE020F881000000BA0890000000000000000000000000000000

MOV #0x80, W0 MOV W0, TBLPAGMOV #0xBFE, W0 MOV #VISI, W1 NOP TBLRDL [W0], [W1] NOPNOPNOPNOPNOP

Step 3: Output the VISI register using the REGOUT command.0001 Clock out contents of the VISI register.

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4.4 Entering Enhanced ICSP ModeAs shown in Figure 4-3, entering Enhanced ICSPProgram/Verify mode requires three steps:

1. The MCLR pin is briefly driven high, then low.2. A 32-bit key sequence is clocked into PGEDx.

An interval of at least P18 must elapse beforepresenting the key sequence on PGEDx.

3. MCLR is held within a specified period of time,then driven high.

The key sequence is a specific 32-bit pattern,‘0100 1101 0100 0011 0100 1000 0101 0000’(more easily remembered as 4D434850h in hexa-decimal format). The device will enter Program/Verifymode only if the key sequence is valid. The MostSignificant bit (MSb) of the most significant nibble mustbe shifted in first.

Once the key sequence is complete, VDD must be appliedto MCLR and held at that level for as long as Program/Verify mode is to be maintained. An interval time of atleast time, P19, P7 and P1 * 5, must elapse beforepresenting data on PGEDx. Signals appearing on PGEDxbefore P7 has elapsed will not be interpreted as valid.

4.5 Blank CheckThe term, “Blank Check”, implies verifying that thedevice has been successfully erased and has noprogrammed memory locations. A blank or erasedmemory location is always read as ‘1’. The Device ID registers (FF0000h:FF0002h) can beignored by the Blank Check since this region storesdevice information that cannot be erased. Additionally,all unimplemented memory space and Calibrationregisters should be ignored by the Blank Check.

The QBLANK command is used for the Blank Check. Itdetermines if the code memory is erased by testingthese memory regions. A ‘BLANK’ or ‘NOT BLANK’response is returned. If it is determined that the deviceis not blank, it must be erased before attempting toprogram the chip.

FIGURE 4-3: ENTERING ENHANCED ICSP™ MODE

MCLR

PGEDx

PGECx

VDD

P6P14

b31 b30 b29 b28 b27 b2 b1 b0b3...

Program/Verify Entry Code = 4D434850h

P1AP1B

P18

P19

0 1 0 0 1 0 0 0 0

P7VDD VDD

P21 P1 * 5

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4.6 Code Memory Programming4.6.1 PROGRAMMING METHODOLOGYThere are two commands that can be used forprogramming code memory when utilizing the Program-ming Executive. The PROG2W command programs andverifies two 24-bit instruction words into the programmemory, starting at the specified address. The secondand faster command, PROGP, programs and verifies anentire row of 128 24-bit instruction words to programmemory, starting at the specified address. Pleaseensure that the starting address is on a row boundarywhen using row programming. See Section 5.0 “TheProgramming Executive” for a full description of eachof these commands.

Figure 4-4 and Figure 4-5 show a high-level overviewof the code memory programming process using thePROG2W and PROGP commands.

FIGURE 4-4: FLOWCHART FOR DOUBLE-WORD PROGRAMMING

FIGURE 4-5: FLOWCHART FOR ROW PROGRAMMING

BaseAddress = 0h

Start

FailureReport ErrorEnd

Yes

No

Yes

PASS?

No

BaseAddressCommand to Program

Send PROG2W

Programmed?All Words

BaseAddress + 04hBaseAddress =

PROG2W ResponseIs

BaseAddress = 0h

Start

FailureReport ErrorEnd

Yes

No

Yes

PASS?

No

BaseAddressCommand to Program

Send PROGP

Programmed?All Rows

BaseAddress + 100hBaseAddress =

PROGP ResponseIs

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4.7 Configuration Bits ProgrammingThe Configuration bits are programmed, one 16-bitword at a time, using the PROG2W command. This com-mand specifies the configuration data and address.When Configuration bits are programmed, anyunimplemented bits must be programmed with a ‘1’. Multiple PROG2W commands are required to programall Configuration bits. A flowchart for Configuration bitprogramming is shown in Figure 4-6.

FIGURE 4-6: CONFIGURATION BIT PROGRAMMING FLOW

4.8 Programming VerificationAfter the code memory is programmed, the contents ofthe memory should be verified to ensure that the pro-gramming was successful. Verification requires codememory to be read back and compared against thecopy held in the programmer’s buffer. The READPcommand can be used to read back all theprogrammed code memory and Configuration Words.

Alternatively, the programmer can perform theverification after the entire device is programmed usinga checksum computation.

See Section 7.0 “Checksum Computation” for moreinformation on calculating the checksum.

4.9 Exiting Enhanced ICSP ModeExiting Program/Verify mode is done by removing VDDfrom MCLR, as shown in Figure 4-7. The onlyrequirement for exit is that an interval, P16, shouldelapse between the last clock, and program signals onPGECx and PGEDx, before removing VDD.

FIGURE 4-7: EXITING ENHANCED ICSP™ MODE

Send PROG2WCommand

IsPROG2W Response

PASS?

No

Yes

No

FailureReport Error

Start

End

Yes

LastConfiguration

Word?

ConfigAddress =ConfigAddress +

04h

MCLR

P16

PGEDx

PGEDx = Input

PGECx

VDD

VDD

VDD

P17

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5.0 THE PROGRAMMING EXECUTIVE

5.1 Programming Executive Communication

The programmer and Programming Executive have aMaster-Slave relationship, where the programmer isthe Master programming device and the ProgrammingExecutive is the Slave.

All communication is initiated by the programmer in theform of a command. Only one command at a time can besent to the Programming Executive. In turn, the PE onlysends one response to the programmer after receivingand processing a command. The PE command set isdescribed in Section 5.2 “Programming ExecutiveCommands”. The response set is described inSection 5.3 “Programming Executive Responses”.

5.1.1 COMMUNICATION INTERFACE AND PROTOCOL

The ICSP/Enhanced ICSP interface is a 2-wire SPI,implemented using the PGECx and PGEDx pins. ThePGECx pin is used as a clock input pin and the clocksource must be provided by the programmer. ThePGEDx pin is used for sending command data to, andreceiving response data from, the PE.

FIGURE 5-1: PROGRAMMING EXECUTIVE SERIAL TIMING

Since a 2-wire SPI is used, and data transmissions arebidirectional, a simple protocol is used to control thedirection of PGEDx. When the programmer completesa command transmission, it releases the PGEDx lineand allows the PE to drive this line high. The PE keepsthe PGEDx line high to indicate that it is processing thecommand.

After the PE has processed the command, it bringsPGEDx low (P9B) to indicate to the programmer thatthe response is available to be clocked out. Theprogrammer can begin to clock out the response aftera maximum wait (P9B) and the programmer mustprovide the necessary amount of clock pulses toreceive the entire response from the PE.

After the entire response is clocked out, theprogrammer should terminate the clock on PGECx untilit is time to send another command to the ProgrammingExecutive. This protocol is shown in Figure 5-2.

5.1.2 SPI RATEIn Enhanced ICSP mode, the dsPIC33CHXXXMP508devices operate from the internal Fast RC (FRC) Oscil-lator, which has a nominal frequency of 8 MHz. Thisoscillator frequency yields an effective system clockfrequency of 4 MHz. To ensure that the programmerdoes not clock too fast, it is recommended that a 2 MHzclock be provided by the programmer.

FIGURE 5-2: PROGRAMMING EXECUTIVE – PROGRAMMER COMMUNICATION PROTOCOL

Note: The Programming Executive can beobtained from each device page on theMicrochip website: www.microchip.com.

Note: For Enhanced ICSP, all serial data aretransmitted on the falling edge of PGECxand latched on the rising edge of PGECx.All data transmissions are sent to the MSbfirst using 16-bit mode (see Figure 5-1).

PGECx

PGEDx

1 2 3 11 13 15 161412

LSb14 13 12 11

4 5 6

MSb 123... 45

P2

P3

P1

P1BP1A

1 2 15 16 1 2 15 16

PGECx

PGEDx

PGECx = Input PGECx = Input (Idle)

Host TransmitsLast Command Word

PGEDx = Input PGEDx = Output

P8

1 2 15 16

MSB X X X LSB1 0P9B

PGECx = InputPGEDx = Output

P9A

Programming ExecutiveProcesses Command Host Clocks Out Response

Note: A delay of 25 ms is required between commands.

MSB X X X LSB MSB X X X LSB

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5.1.3 TIME-OUTSThe Programming Executive uses no Watchdog Timeror time-out for transmitting responses to theprogrammer. If the programmer does not follow the flowcontrol mechanism using PGECx, as described inSection 5.1.1 “Communication Interface andProtocol”, it is possible that the ProgrammingExecutive will behave unexpectedly while trying tosend a response to the programmer. Since the PE has

no time-out, it is imperative that the programmercorrectly follows the described communicationprotocol.

As a safety measure, the programmer should use thecommand time-outs identified in Table 5-1. If the com-mand time-out expires, the programmer should resetthe PE and start programming the device again.

TABLE 5-1: PROGRAMMING EXECUTIVE COMMAND SET

Opcode Mnemonic Length(16-bit words) Time-out Description

0x0 SCHECK 1 1 ms Sanity check.0x1 Reserved N/A N/A —0x2 READP 4 1 ms/row Read ‘N’ 24-bit instruction words of the user Flash memory,

Configuration Word or Device ID register, starting from the specified address.

0x3 PROG2W 6 5 ms Program a double instruction word of code memory at the specified address and verify.

0x4 Reserved N/A N/A This command is reserved; it will return a NACK.0x5 PROGP 195 5 ms Program 128 words of program memory at the specified

starting address, then verify.0x6 Reserved N/A N/A This command is reserved; it will return a NACK.0x7 ERASEB 1 125 ms Bulk Erase user memory.0x8 Reserved N/A N/A This command is reserved; it will return a NACK.0x9 ERASEP 3 25 ms Command to erase a page.0xA Reserved N/A N/A This command is reserved; it will return a NACK.0xB QVER 1 1 ms Query the Programming Executive software version.0xC CRCP 5 1s Perform a CRC-16 on the specified range of memory.0xD Reserved N/A N/A This command is reserved; it will return a NACK.0xE QBLANK 5 700 ms Query to check whether the code memory is blank.

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5.2 Programming Executive Commands

The Programming Executive command set is shown inTable 5-1. This table contains the opcode, mnemonic,length, time-out and description for each command.Functional details on each command are provided in thecommand descriptions (see Section 5.2.4 “CommandDescriptions”).

5.2.1 COMMAND FORMATAll Programming Executive commands have a generalformat, consisting of a 16-bit header and any requireddata for the command (see Figure 5-3). The 16-bitheader consists of a 4-bit opcode field, which is used toidentify the command, followed by a 12-bit commandlength field.

FIGURE 5-3: COMMAND FORMAT

The command opcode must match one of those in thecommand set. Any command that is received whichdoes not match the list in Table 5-1 will return a “NACK”response (see Section 5.3.1.1 “Opcode Field”). The command length is represented in 16-bit wordssince the SPI operates in 16-bit mode. The Program-ming Executive uses the command length field todetermine the number of words to read from the SPIport. If the value of this field is incorrect, the commandwill not be properly received by the ProgrammingExecutive.

5.2.2 PACKED DATA FORMATWhen 24-bit instruction words are transferred acrossthe 16-bit SPI interface, they are packed to conservespace using the format shown in Figure 5-4. Thisformat minimizes traffic over the SPI and provides theProgramming Executive with data that are properlyaligned for performing Table Write operations.

FIGURE 5-4: PACKED INSTRUCTION WORD FORMAT

5.2.3 PROGRAMMING EXECUTIVE ERROR HANDLING

The Programming Executive will “NACK” all unsup-ported commands. Additionally, due to the memoryconstraints of the Programming Executive, no checkingis performed on the data contained in the programmercommand. It is the responsibility of the programmer tocommand the Programming Executive with valid com-mand arguments or the programming operation mayfail. Additional information on error handling is providedin Section 5.3.1.3 “QE_Code Field”.

15 12 11 0

Opcode Length

Command Data First Word (if required)

•

•

Command Data Last Word (if required)

15 8 7 0

LSW1

MSB2 MSB1

LSW2

LSWx: Least Significant 16 bits of instruction wordMSBx: Most Significant Byte of instruction word

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5.2.4 COMMAND DESCRIPTIONSAll commands supported by the ProgrammingExecutive are described in Section 5.2.4.1 “SCHECKCommand” through Section 5.2.4.9 “QBLANKCommand”.

5.2.4.1 SCHECK Command

Table 5-2 provides the description for the SCHECKcommand.

TABLE 5-2: COMMAND DESCRIPTION

The SCHECK command instructs the ProgrammingExecutive to do nothing but generate a response. Thiscommand is used as a “Sanity Check” to verify that theProgramming Executive is operational.

Expected Response (2 words):0x10000x0002

5.2.4.2 READP Command

Table 5-3 provides the description for the READPcommand.

TABLE 5-3: COMMAND DESCRIPTION

The READP command instructs the ProgrammingExecutive to read N 24-bit words of code memory,Flash Configuration Words or Device ID registers,starting from the 24-bit address specified by Addr_MSBand Addr_LS. This command can only be used to read24-bit data. All data returned in response to thiscommand use the packed data format described inSection 5.2.2 “Packed Data Format”.Expected Response (2 + 3 * N/2 words for N even):

0x12002 + 3 * N/2Least Significant Program Memory Word 1... Least Significant Data Word N

Expected Response (4 + 3 * (N – 1)/2 words for N odd):0x12004 + 3 * (N – 1)/2Least Significant Program Memory Word 1... MSB of Program Memory Word N (zero-padded)

15 12 11 0Opcode Length

Field Description

Opcode 0x0Length 0x1

Note: This instruction is not required forprogramming but is provided fordevelopment purposes only.

15 12 11 8 7 0Opcode Length

NReserved Addr_MSB

Addr_LS

Field Description

Opcode 0x2Length 0x4N Number of 24-bit instructions to read

(maximum of 32768)Reserved 0x0Addr_MSB MSB of 24-bit source addressAddr_LS Least Significant 16 bits of 24-bit

source address

Note 1: Reading unimplemented memory willcause the Programming Executive toreset. Please ensure that only memorylocations present on a particular deviceare accessed.

2: When the READP command is used toread Device ID registers, the upper byte(bits[23:16]) of each word returned by theProgramming Executive should beignored.

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5.2.4.3 PROG2W Command

Table 5-4 provides the description for the PROG2Wcommand.

TABLE 5-4: COMMAND DESCRIPTION

The PROG2W command instructs the ProgrammingExecutive to program two instruction words of codememory (6 bytes) to the specified memory address.

After the words have been programmed to codememory, the Programming Executive verifies theprogrammed data against the data in the command.

Expected Response (2 words):0x13000x0002

5.2.4.4 PROGP Command

Table 5-5 provides the description for the PROGPcommand.

TABLE 5-5: COMMAND DESCRIPTION

The PROGP command instructs the ProgrammingExecutive to program one row of code memory(128 instruction words) to the specified memoryaddress. Programming begins with the row addressspecified in the command. The destination addressshould be a multiple of 0x100.

The data to program the memory, located in commandwords, D_1 through D_192, must be arranged usingthe packed instruction word format illustrated inFigure 5-4.

After all data have been programmed to code memory,the Programming Executive verifies the programmeddata against the data in the command.

Expected Response (2 words):0x15000x0002

15 12 11 8 7 0Opcode Length

Reserved Addr_MSBAddr_LSDataL_LS

DataH_MSB DataL_MSBDataH_LS

Field Description

Opcode 0x3Length 0x6DataL_MSB MSB of 24-bit data for low instruction

wordDataH_MSB MSB of 24-bit data for high instruction

wordAddr_MSB MSB of 24-bit destination addressAddr_LS Least Significant 16 bits of 24-bit

destination addressDataL_LS Least Significant 16 bits of 24-bit data

for low instruction wordDataH_LS Least Significant 16 bits of 24-bit data

for high instruction word

15 12 11 8 7 0Opcode Length

Reserved Addr_MSBAddr_LS

D_1D_2...

D_N

Field Description

Opcode 0x5Length 0xC3Reserved 0x0Addr_MSB MSB of 24-bit destination addressAddr_LS Least Significant 16 bits of 24-bit

destination addressD_1 16-bit Data Word 1D_2 16-bit Data Word 2... 16-bit Data Word 3 through 191D_192 16-bit Data Word 192

Note: Refer to Table 2-2 for code memory sizeinformation.

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5.2.4.5 ERASEB Command

Table 5-6 provides the description for the ERASEBcommand.

TABLE 5-6: COMMAND DESCRIPTION

The ERASEB command instructs the ProgrammingExecutive to perform a Bulk Erase of the user Flashmemory.

Expected Response (2 words):0x17000x0002

5.2.4.6 ERASEP Command

Table 5-7 provides the description for the ERASEPcommand.

TABLE 5-7: COMMAND DESCRIPTION

The ERASEP command instructs the ProgrammingExecutive to Page Erase [NUM_PAGES] of codememory. The code memory must be erased at an“even” 1024 instruction word address boundary.

Expected Response (2 words):0x19000x0002

5.2.4.7 QVER Command

Table 5-8 provides the description for the QVERcommand.

TABLE 5-8: COMMAND DESCRIPTION

The QVER command queries the version of theProgramming Executive software stored in testmemory. The “version.revision” information is returnedin the response’s QE_Code, using a single byte withthe following format: main version in upper nibble anda revision in the lower nibble (i.e., 0x23 meansVersion 2.3 of the Programming Executive software).

Expected Response (2 words):0x1BMN (where “MN” stands for version M.N)0x0002

5.2.4.8 CRCP Command

Table 5-9 provides the description for the CRCP command.

TABLE 5-9: COMMAND DESCRIPTION

The CRCP command performs a CRC-16 on the range ofmemory specified. This command can substitute for a fullchip verify. Data are shifted in a packed method as shownin Figure 5-4, bytewise, Least Significant Byte (LSB) first.

Example:CRC-CCITT-16 with test data of “123456789” becomes29B1h

Expected Response (3 words):QE_Code: 0x1C00Length: 0x0003CRC Value: 0xXXXX

15 12 11 8 7 0Opcode Length

Field Description

Opcode 0x7Length 0x1

15 12 11 8 7 0

Opcode Length

NUM_PAGES Addr_MSB

Addr_LS

Field Description

Opcode 0x9Length 0x3NUM_PAGES Up to 255Addr_MSB Most Significant Byte of the 24-bit

addressAddr_LS Least Significant 16 bits of the 24-bit

address

15 12 11 0Opcode Length

Field Description

Opcode 0xBLength 0x1

15 12 11 8 7 0

Opcode Length

Reserved Addr_MSB

Addr_LSW

Reserved Size_MSB

Size_LSW

Field Description

Opcode 0xCLength 0x5Addr_MSB Most Significant Byte of 24-bit addressAddr_LSW Least Significant 16 bits of 24-bit addressSize Number of 24-bit locations (address

range divided by 2)

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5.2.4.9 QBLANK Command

Table 5-10 provides the description for the QBLANKcommand.

TABLE 5-10: COMMAND DESCRIPTION

The QBLANK command queries the ProgrammingExecutive to determine if the contents of code memoryare blank (contains all ‘1’s). The size of code memoryto check must be specified in the command.

The Blank Check for code memory begins at [Addr] andadvances toward larger addresses for the specifiednumber of instruction words.

QBLANK returns a QE_Code of F0h if the specifiedcode memory is blank; otherwise, QBLANK returns aQE_Code of 0Fh.

Expected Response (2 words for blank device):0x1EF00x0002

Expected Response (2 words for non-blank device):0x1E0F0x0002

5.3 Programming Executive Responses

The Programming Executive sends a response to theprogrammer for each command that it receives. Theresponse indicates if the command was processedcorrectly. It includes any required response data orerror data.

The Programming Executive response set is shown inTable 5-11. This table contains the opcode, mnemonicand description for each response. The response formatis described in Section 5.3.1 “Response Format”.

TABLE 5-11: PROGRAMMING EXECUTIVE RESPONSE OPCODES

5.3.1 RESPONSE FORMATAll Programming Executive responses have a generalformat, consisting of a two-word header and anyrequired data for the command.

Table 5-12 provides the description of the responseformat.

TABLE 5-12: RESPONSE FORMAT DESCRIPTION

15 12 11 0Opcode Length

Reserved Size_MSBSize_LSW

Reserved Addr_MSBAddr_LSW

Field Description

Opcode 0xELength 0x5Size Length of program memory to check

(in 24-bit words) + Addr_MSAddr_MSB Most Significant Byte of the 24-bit

addressAddr_LSW Least Significant 16 bits of the 24-bit

address

Note: The QBLANK command does not check thesystem operation Configuration bits, sincethese bits are not set to ‘1’ when a ChipErase is performed.

Opcode Mnemonic Description

0x1 PASS Command successfully processed

0x2 FAIL Command unsuccessfully processed

0x3 NACK Command not known

Field Description

Opcode Response opcodeLast_Cmd Programmer command that

generated the responseQE_Code Query code or error codeLength Response length in 16-bit words

(includes 2 header words)D_1 First 16-bit data word (if applicable)D_N Last 16-bit data word (if applicable)

15 12 11 8 7 0

Opcode Last_Cmd QE_Code

Length

D_1 (if applicable)

...

D_N (if applicable)

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5.3.1.1 Opcode FieldThe opcode is a 4-bit field in the first word of theresponse. The opcode indicates how the command wasprocessed (see Table 5-11). If the command wasprocessed successfully, the response opcode is PASS. Ifthere was an error in processing the command, theresponse opcode is FAIL and the QE_Code indicates thereason for the failure. If the command sent to the Pro-gramming Executive is not identified, the ProgrammingExecutive returns a NACK response.

5.3.1.2 Last_Cmd FieldThe Last_Cmd is a 4-bit field in the first word of theresponse and indicates the command that theProgramming Executive processed. Since the Pro-gramming Executive can only process one commandat a time, this field is technically not required. However,it can be used to verify that the Programming Executivecorrectly received the command that the programmertransmitted.

5.3.1.3 QE_Code FieldThe QE_Code is a byte in the first word of theresponse. This byte is used to return data for querycommands and error codes for all other commands.

When the Programming Executive processes one ofthe two query commands (QBLANK or QVER), thereturned opcode is always PASS and the QE_Codeholds the query response data. The format of theQE_Code for both queries is shown in Table 5-13.

TABLE 5-13: QE_Code FOR QUERIES

When the Programming Executive processes anycommand other than a query, the QE_Code representsan error code. Supported error codes are shown inTable 5-14. If a command is successfully processed, thereturned QE_Code is set to 0x0, which indicates thatthere is no error in the command processing. If the verifyof the programming for the PROGW command fails, theQE_Code is set to 0x1. For all other ProgrammingExecutive errors, the QE_Code is 0x02.

TABLE 5-14: QE_Code FOR NON-QUERY COMMANDS

5.3.1.4 Response LengthThe response length indicates the length of theProgramming Executive’s response in 16-bit words.This field includes the two words of the responseheader.

With the exception of the response for the readcommands, the length of each response is only twowords.

The response to the READP command uses the packedinstruction word format, described in Section 5.2.2“Packed Data Format”. When reading an odd numberof Program Memory Words (N odd), the response to theREADP command is (3 * (N + 1)/2 + 2) words. Whenreading an even number of Program Memory Words(N even), the response to the READP command is(3 * N/2 + 2) words.

Query QE_Code

QBLANK 0x0F = Code memory is NOT blank0xF0 = Code memory is blank

QVER 0xMN, where Programming Executive Software Version = M.N(i.e., 0x32 means Software Version 3.2)

QE_Code Description

0x0 No error0x1 Verify failed0x2 Other error

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5.4 Programming the Programming Executive to Memory

5.4.1 OVERVIEWIf it is determined that the Programming Executive isnot present in the executive memory (as described inSection 4.2 “Confirming the Presence of the Pro-gramming Executive”), the Programming Executivemust be programmed to executive memory.

Figure 5-5 shows the high-level process of programmingthe Programming Executive into executive memory.First, the ICSP mode must be entered and the executivememory must be erased. Then, the ProgrammingExecutive is programmed and verified. Finally, ICSPmode is exited.

FIGURE 5-5: HIGH-LEVEL PROGRAMMING EXECUTIVE PROGRAM FLOW

5.4.2 ERASING EXECUTIVE MEMORYThe procedure for erasing each page of executivememory is similar to that of erasing program memoryand is shown in Figure 3-6. It consists of settingNVMCON to 4003h and then executing theprogramming cycle.

Table 5-15 shows the ICSP programming process forerasing the executive code memory.

Note: The Programming Executive can beobtained from each device page on theMicrochip website: www.microchip.com.

Start

End

Program the

Enter ICSP™ Mode

Page Erase All Pages in

Programming Executive

Executive Memory

Exit ICSP Mode

Read/Verify theProgramming Executive

Note: The Programming Executive memorymust always be erased before it isprogrammed, as described in Figure 5-5.

DS70005285E-page 50 2016-2019 Microchip Technology Inc.

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TABLE 5-15: SERIAL INSTRUCTION EXECUTION FOR ERASING ALL PAGES OF EXECUTIVE MEMORY

Command(Binary)

Data(Hex) Description

Step 1: Exit the Reset vector.0000000000000000000000000000

000000000000000000040200000000000000000000

NOPNOPNOPGOTO 0x200NOPNOPNOP

Step 2: Set the NVMADRU/NVMADR register pair to point to the correct page of executive memory to be erased.0000000000000000

2xxxx32xxxx4883953883964

MOV #DestinationAddress, W3MOV #DestinationAddress, W4MOV W3, NVMADRMOV W4, NVMADRU

Step 3: Set the NVMCON register to erase the first page of executive memory.0000000000000000

24003A88394A000000000000

MOV #0x4003, W10MOV W10, NVMCONNOPNOP

Step 4: Initiate the erase cycle.00000000000000000000000000000000

200551883971200AA1883971A8E729000000000000000000

M