DISCOVER: Design and Simulation of Complex Low Volume Electronics

Productionby

Dr Andrew A. West

DISCOVER GROUPPaul Conway Chris Hinde

Diana Segura David WhalleyTony Wilson

Loughborough University

Loughborough University - Wednesday 21 September 2006

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DISCOVER

Industrial ContextThe Challenge Aims and ObjectivesMethodologyDeliverables Current StatusQuestions?

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Industrial Context

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The Challenge

What are the reasons for poor first time yield and long term reliability in complex products?

Defects generated during the manufacturing flow, Lack of formalised process knowledge, Lack of knowledge concerning the implications of design features on manufacturing performance, Lack of in process performance monitoring and analysis,The impact of new materials and components e.g. (lead free legislation) Lack of knowledge of the impact of the adoption of new technology (e.g. novel agile approaches to reflow oven technology).

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Aims and Objectives

Understand the causes of poor manufacturing performance within the low volume electronics manufacturing domain…

Develop a suite of software tools that can enable models of complete design, manufacturing and business processes (throughout the entire product lifecycle) in terms of their propensity to create defects that could cause product failure,Reduce a products manufactured cost and time to market and enhance its quality,Enable simulation of new designs and the impact of design, manufacturing and business strategies,Enable the optimisation of designs and manufacturing processes for yield, quality and reliability.

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Methodology

Activities

Analysis of the causes of poor yield and service failure -design and / or manufacturing processes,Mapping generic electronics design procedures into well-defined process steps, Modelling the defect causing propensity of each process, Developing knowledge-based software tools that capture both the design and manufacturing processes and defect causing propensity, Determining new product and new technology introduction scenarios to enable the software tools to be evaluated,Evaluation of the software tools from functional, human factors and business perspectives.

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Methodology: Work PackagesWP1: Analysis of cause of poor yield and service performanceWP2: Generic Design and Manufacturing Process StepsWP3: Design and Manufacturing Defect – Process MappingWP4: Development of Component-Based (CB) simulation toolWP5: Evaluation of CB simulation tool for design and process optimisationWP6: Dissemination and Exploitation

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Deliverables

A methodology for capturing and describing the linkages between design and manufacturing process variables and yield, product reliability, cost and quality

A component based framework for constructing static (i.e. visual) and dynamic (i.e. enactable via computer-based simulation) process representations

A lifecycle model of a design and production facility capable of simulating process yield and guiding product or process design

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Current Status

ID Task Name Duration Start

1 WP1 Test and service Data Capture 326 days? Mon 16/01/06

10 WP2 Assembly Process Flow Map 194 days? Mon 16/01/06

11 Milestone2 - Initial Processes Mapped 0 days Fri 02/06/06

12 Milestone3 - Completion of process mapping 0 days Fri 13/10/06

13 Scope detail level required 164 days? Mon 16/01/06

14 Iniital process maps for all partners 83 days Wed 08/02/0

15 Capture partner process flows and process variations 160 days Mon 06/02/06

16 Capture partner design rules 33 days Mon 15/05/06

17 Encoding of DFM rules - Goodrich 18 days Mon 15/05/0618 Encoding of DFM rules - Smiths 18 days Mon 15/05/0619 Encoding of DFM rules - STI 11 days Mon 15/05/0620 Iterative cycle of refining rules with expert support 12 days Tue 30/05/0621 Creation of Rule-Based System 10 days Thu 15/06/0622 Develop generic process flow with options (including rework) 140 days Sat 01/04/0

23 WP3 Individual Process step defect modelling 291 days Mon 21/08/06

24 Milestone5 - Define all processes 50% modelled 0 days Fri 02/03/07

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Study of available documentation, visits,

questionnaire, structuredinterview (based on adopted

EM approach)

Processes(Current Practice)

Knowledge of Manufacturing

Electronics

End-UserRequirements

Circuit Designers

Manufacturing Engineers

Maintenance

Testing & Installation

Building

Circ

uit D

esig

ners

Man

ufac

turin

g en

gine

ers

End-

Use

r

InformationTime

Cost

Modelling & Visualisation PhaseKnowledge Elicitation Phase What If Analyses & Assessment Phase

BP Models

Model validation check based on feedback

TO-BE Processes (After Implementing

CBT)

Methods:

FormalisingBusiness Processes

using EM approaches

VisualisingProcesses

using BPM Tools

Comparison

EM : refers to EnGERAM, PERA, GRAI, CIMOSA

terprise Modelling Approaches such as (adopted in this project)

ess Process Modelling Tools such as cture, IThink

BPM : refers to BusinProcessWise, SysytemArchite (adopted in this project)

Simulation and Demonstration of Current Practice

Simulation and Demonstration of Systems after Analysis

Assembly Process Flow - Vision

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Context Diagram

InteractionDiagram

Structure Diagram

Activity Diagram

Domain Processes

Business Processes

Enterprise Activities

Events

Physical Resource

Finance

Human Resource

Information

External Links

Flow of Res./Mat.Flow of Process

Activity

CIMOSA Domain

Non-CIMOSA Domain

Alternative Flow“Rea

l”W

orld

Pro

cess

es

Abstraction Mechanisms

Assembly Process Flow – Constructs

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Assembly Process Flow –Context Diagram

C om plex L O w V olum e E lectronic System s – Process M odelling W olfson School of M echanical

& M anufacturing Engineering

T itle: N umber:

Design by:

Checked by:

Last update:

Diana Segura & Tony W ilson

2Physical Re source FinanceHum an ResourceInform ation Exte rnal L inks Flow of Re s./M at. Flow o f P rocessA ctivityC IM O SA D om ain N on-C IM O SA D om ain Alternative FlowEvent(s)

19/09/2006O verall C ontext D iagram

Context D iagram – G eneric Level V iew

X X X X D iag

P roduct D evelopm ent

D ISC O V E R

P roduct R ealization

Production

D P3: Product Q ualification

D P1: Product D esign

D P2: P rocess D evelopm ent

D P9: TestD P7:

M anufacturing Set-up

D P8: M anufacturing

O perations

D P6: C om m ercia lised D esign to M anf

D P4: V ertica lly Integrated

D esign to M anf

D P5: Para lle l D esign to

M anufacture

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BPx.x.x

BPx.x.x - PxxxProcess Set Up

Required

Verify Process Parameter Input Data File Correlates

With Prod ID

EAX.X.X

Input Process Set-up Parameters

Produce First-off

Verify (Inspect or Test) First-off

BPx.x.x - PxxxProcess Set Up

Validated

Validate Process Set-up As Production Ready

Define Defect Opportunity Cause

Can Defect Opportunity Be Negated

During Set-up

Validated First-Off (Pass Inspection

or Test Stage)

Yes

No

Fail

Pass

Define Set-up Parameter Adjustments

BPx.x.x - PxxxProcess Set Up

With Defect Opportunity Concessions

EAX.X.X

EAX.X.X

EAX.X.XEAX.X.X

EAX.X.X

EAX.X.X

Build Schedule

Product Set-Up Data i.e.EA7.1.1.1 Assembly Drawings

EA7.1.1.2 ECNs EA7.1.1.3 Build StandardEA7.1.1.4 SMT Kiting List

EA7.1.1.5 SMT Layout DrawingsEA7.1.1.6 SMT Process Chemistry ListEA7.1.1.7 SMT Process Chemistry List

EA7.1.1.8 PTH Kiting ListEA7.1.1.9 PTH Layout Drawings

EA7.1.1.10 PTH Process Tooling ListEA7.1.1.11 Mechanical Components Kiting List

EA7.1.1.12 Mechanical Component Layout Draw'sEA7.1.1.13 Mechanical Assembly Tooling List

EA7.1.1.14 Wave Solder Process Chemistry ListEA7.1.1.15 Wave Solder Process Tooling List

EA7.1.1.16 NSP instructions & DrawingsEA7.1.1.17 NSP Chemistry ListEA7.1.1.18 NSP Tooling List

EA7.1.1.19 Test Specs.EA7.1.1.20 Bom

Product Set-Up Data

* Validation Vehicle e.g. Set-up Board, Sticky Board, Profile

Board etc* Production Released Product Tooling

* Process Chemicals* SMT, PHT, Mech Comp Kits etc.

* Verification Equipment e.g. Paste Height/ Volume Measuring Kit,

Magnifiers, SMT Overlays, Comp locator Software, API, AOI, AXI, FPT,

ICT, FCT, etc

BPx.x.x Sub-process - Generic Process Set-up

Assembly Process Flow – Activity Diagram

Generic Manufacturing Set up

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Dissolve Gold Plating in Sacrificial Tin/Lead Bath

Dip Flux Component Leads

Dip Coat Leads in Uncontaminated Tin/Lead

Bath

Do Component

Leads Require Tinning

Dip Flux Component Leads

Company Standard - 0615-009Requirements For Soft Soldered

Electrical Connections EAX.X.X

EAX.X.X.X

EAX.X.X.X

EAX.X.X.X

EAX.X.X.XLiquid Flux & Dip Tank

Liquid Flux & Dip Tank

Tin/Lead & Solder Bath

Tin/Lead & Solder Bath

Yes

DP8 (Manf Ops) / K300 (PTH & Mech Comp Kitting)Manf Op Completed

No

PTH Operator

DP7 (Manf Set-up) /BP7.3.2 - (Sub-

process - PTH Kitting Set-up) Process Set-up

Completed

Assembly Process Flow – Activity Diagram

Lead Tinning

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Generic Ishikawa.igx

Effects:BP9.1 Internal FailuresBP9.2 External Failures

Product Realisation

DP6: Comercialised (i.e. Part Of Or All Of The DTM Sequence Outsourced)

Product Development

DP2: Process Dedvelopment

DP8: Manufacturing Operations

BP8.1 Comp & PCB Prep

DP7: Manufacturing Set-up

BP7.1 Documentation

BP9.1 INTERNAL FAILURES:

Inherent Defects In A Product's Mechanical Integrity That Are Detected During Printed Circuit Assembly & iTest (i.e.Yield)

Inherent Defects In A Product's Mechanical Integrity That Are Detected During Environmental Stress Screening (i.e. Captured Infant Mortalities)

BP9.2EXTERNAL FAILURES:

Inherent Defects In A Product's Mechanical Integrity That Cause Sporadic Early Life Field Failures (i.e Escaping Infant Mortalitiity Failures)

Inherent Deficiencies In A Product's Mechanical Integrity That Cause Systematic Premature In-service Stress Related Wear-out (i.e. Fatigue Resistance Failures

DP3: Product Qualification

DP1: Product Design DP4: Vertically Integrated (i.e. Internal Production Model)

DP5: Parallel (i.e. Production Model Includes Internal & Outsourcing)

BP1.1 DFx Rules

BP2.1Functionality Pre-qualification

BP3.1Process Chemistry Pre-qualification

BP3.2Process ToolingPre-qualification

BP1.2 Product Architecture

BP2.2ReliabilityPre-qualification

BP4.1Internal NPI (New Product Introduction)

BP5.1Internal NPI With External Sub-assembly

BP6.1Eternal NPI

BP6.2New Contract Introduction

BP7.2 PCB Prep

BP7.3 Component Loading

BP7.4 SMT Processes

BP7.5 PTH & Pre-wave

BP7.6 Wave & Post Wave

BP7.7 PCA Test & Rework

BP7.8 PCA Completion

BP7.9 Module Assy & Test

BP7.10 Unit Assy & Test

BP8.2 Side 1 SMT

BP8.3 Side 2 SMT

BP8.4 PTH & Pre-wave Mech CompsBP8.5 Wave Soldering & Post-wave Mech Component Hand Soldering

BP8.6 PCA Test

BP8.7 PCA Completion

BP8.9 Unit Assembly & Test

Assembly Process Flow - Cause-Effect Diagram

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Partners Design Rules – Vision

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Partners Design Rules - Knowledge Elicitation

Encoding DFM rules into “IF – THEN” rules (e.g. IF Thinner circuits are required THEN Use dedicated fixtures AND Vacuum clamping)Validation of the rules with expertsLink rules to defect opportunity i.e. effect on reliability Inclusion of defect costs Inclusion of rule metrics Generation of common rules clustering Unification of Vocabulary across industrial partnersComparison with high volume electronicsComparison with International Standards Trial of commercial rule-based software

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Partners Design Rules - Example

ATTRIBUTES / CHECKS RULES AND BEST PRACTICE

>> Solder? Finish >> Solder ? Finish

The outer layers should have a FINISH NOTE, as determined by the Process Department.

IF THE MINIMUM THICKNESS OF TIN-LEAD BEFORE REFUSING/REFLOWING IS BE 0,15um.

THEN THE BOARD IS TO HAVE A 60/40 REFUSED/REFLOWED TIN-LEAD SOLDER FINISH

IF OVER 0,06um TO 0,12um THICK IMMERSION GOLD OR OVER 3um TO 9um THICK ELECTROLESS NICKEL.

THEN THE BOARD TO BE HOT AIR SOLDER LEVELLED USING 60/40 TIN-LEAD FINISH

IF OVER ELECTROLESS NICKEL 3um TO 9um THICK.

THEN GOLD IMMERSION PLATE 0,06 TO 0,12um THICK, FINISH

IF THEN THE BOARD TO BE HOT AIR SOLDER LEVELLED USING 60/40 TIN-LEAD FINISH

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Partners Design Rules – Metrics and Defects

METRICS DEFECTS AND REQUIREMENTS

visual inspection THIS THICKNESS IS CRITICAL TO FACILITATE SUBSEQUENT REFLOW TECHNIQUES ON ASSEMBLY. NOT preferred for future designs (WHY?)

visual inspection this was introduced to overcome soldering issues with Circast gold on Trent 500. NOT preferred for future designs (WHY?)

visual inspection this is the preferred method for PCB’s with vias that may not solder fill and for reflow soldered Surface Mount Cards

visual inspection this is the current standard solder finish for discrete plated through hole PCB

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DISCOVER

Industrial ContextThe Challenge Aims and ObjectivesMethodologyDeliverables Current StatusQuestions?