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Digital Signal Processor (DSP)Digital Signal Processor (DSP)ByBy
Steve D. Wong Steve D. Wong (166/198A)(166/198A)
Ervin Rosario-Figueroa Ervin Rosario-Figueroa (166/198A)(166/198A)
Lana DamLana Dam
Ivan Pierre-LouisIvan Pierre-Louis
Cuong NguyenCuong Nguyen
Spring 2003Spring 2003
San Jose State University
Department of Electrical Engineering
IntroductionIntroduction Design of a 4-Bit Digital Signal Processor Design of a 4-Bit Digital Signal Processor
(DSP) using CMOS Logic. (DSP) using CMOS Logic. DSP is composed of a Multiplier, D Flip DSP is composed of a Multiplier, D Flip
Flop and a Subtractor. Flop and a Subtractor. Up/Down Counter will be used as a test Up/Down Counter will be used as a test
vector for the system. vector for the system.
SpecificationsSpecifications
Functional SpecificationFunctional Specification 4-Bit Multiplier4-Bit Multiplier 4-Bit Full Subtractor4-Bit Full Subtractor D Flip FlopD Flip Flop 4-Bit Up/Down Counter4-Bit Up/Down Counter
Technical SpecificationsTechnical Specifications Design Wn & Wp = 3 Design Wn & Wp = 3 mm Power <= 0.25WattPower <= 0.25Watt
Clock Frequency << 200 MHzClock Frequency << 200 MHzVVDDDD = 5 Volts = 5 Volts