Digital servo processor and Compact Disc decoder (CD7)gerard.paulhac.free.fr/Audio/Doc_723/Documents/SAA7377.pdf · 7.6 FIFO and error corrector 7.6.1 Flags output (CFLG) 7.6.2 C2FAIL

DATA SHEET

Product specificationsFile under Integrated Circuits, IC01

1998 Jul 06

INTEGRATED CIRCUITS

SAA7377Digital servo processor andCompact Disc decoder (CD7)

1998 Jul 06 2

Philips Semiconductors Product specifications

Digital servo processor and Compact Discdecoder (CD7)

SAA7377

CONTENTS

1 FEATURES

2 GENERAL DESCRIPTION

3 QUICK REFERENCE DATA

4 ORDERING INFORMATION

5 BLOCK DIAGRAM

6 PINNING

7 FUNCTIONAL DESCRIPTION

7.1 Decoder part7.1.1 Principle operational modes of the decoder7.1.2 Crystal frequency selection7.1.3 Standby modes7.2 Crystal oscillator7.3 Data slicer and clock regenerator7.4 Demodulator7.4.1 Frame sync protection7.4.2 EFM demodulation7.5 Subcode data processing7.5.1 Q-channel processing7.5.2 EIAJ 3 and 4-wire subcode (CD graphics)

interfaces7.5.3 V4 subcode interface7.6 FIFO and error corrector7.6.1 Flags output (CFLG)7.6.2 C2FAIL7.7 Audio functions7.7.1 De-emphasis and phase linearity7.7.2 Digital oversampling filter7.7.3 Concealment7.7.4 Mute, full scale, attenuation and fade7.7.5 Peak detector7.8 DAC interface7.9 EBU interface7.9.1 Format7.10 KILL circuit7.11 The VIA interface7.12 Spindle motor control7.12.1 Motor output modes7.12.2 Spindle motor operating modes7.12.3 Loop characteristics7.12.4 FIFO overflow

7.13 Servo part7.13.1 Diode signal processing7.13.2 Signal conditioning7.13.3 Focus servo system7.13.4 Radial servo system7.13.5 Off-track counting7.13.6 Defect detection7.13.7 Off-track detection7.13.8 high-level features7.13.9 Driver interface7.13.10 Laser interface7.13.11 Radial shock detector7.14 Microcontroller interface7.14.1 Microprocessor interface (4-wire bus mode)7.14.2 Microcontroller interface (I2C-bus mode)7.14.3 Summary of functions controlled by registers

0 to F7.14.4 Summary of servo commands7.14.5 Summary of servo command parameters

8 LIMITING VALUES

9 OPERATING CHARACTERISTICS

10 OPERATING CHARACTERISTICS(SUBCODE INTERFACE TIMING)

11 OPERATING CHARACTERISTICS (I2S-BUSTIMING)

12 OPERATING CHARACTERISTICS(MICROCONTROLLER INTERFACE TIMING)

13 APPLICATION INFORMATION

14 PACKAGE OUTLINE

15 SOLDERING

15.1 Introduction15.2 Reflow soldering15.3 Wave soldering15.4 Repairing soldered joints

16 DEFINITIONS

17 LIFE SUPPORT APPLICATIONS

18 PURCHASE OF PHILIPS I2C COMPONENTS

1998 Jul 06 3



SAA7377

1 FEATURES

• Single-speed mode

• Full error correction strategy, t = 2 and e = 4

• Full CD graphics interface

• All standard decoder functions implemented digitally onchip

• FIFO overflow concealment for rotational shockresistance

• Digital audio interface (EBU), audio only

• 2 and 4 times oversampling integrated digital filter,including fs mode

• Audio data peak level detection

• Kill interface for DAC deactivation during digital silence

• All TDA1301 (DSIC2) digital servo functions, plus extrahigh-level functions

• Low focus noise

• Improved playability on ABEX TCD-721R, TCD-725 andTCD-714 discs

• Automatic closed loop gain control available for focusand radial loops

• Pulsed sledge support

• Microcontroller loading LOW

• High-level servo control option

• High-level mechanism monitor

• Communication may be via TDA1301/SAA7345compatible bus or I2C-bus

• On-chip clock multiplier allows the use of 8.4672 MHzcrystal.

2 GENERAL DESCRIPTION

The SAA7377 is a single chip combining the functions of aCD decoder IC and digital servo IC. The decoder part isbased on the SAA7345 (CD6) with an improved errorcorrection strategy. The servo part is based on theTDA1301T (DSIC2) with improvements incorporated,extra features have also been added.

Supply of this Compact Disc IC does not convey an impliedlicense under any patent right to use this IC in anyCompact Disc application.

3 QUICK REFERENCE DATA

4 ORDERING INFORMATION

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

VDD supply voltage 3.4 5.0 5.5 V

IDD supply current − 49 − mA

fxtal crystal frequency 8 8.4672 35 MHz

Tamb operating ambient temperature −40 − +85 °CTstg storage temperature −55 − +125 °C

TYPENUMBER

PACKAGE

NAME DESCRIPTION VERSION

SAA7377GP QFP64 plastic quad flat package; 64 leads (lead length 1.6 mm);body 14 × 14 × 2.7 mm

SOT393-1

1998 Jul 06 4



SAA7377

5 BLOCK DIAGRAM

Fig.1 Block diagram.

handbook, full pagewidth

DECODERMICRO-

CONTROLLERINTERFACE VERSATILE PINS

INTERFACE

SUBCODEPROCESSOR

KILL

PEAKDETECT

SERIAL DATAINTERFACE

TIMING

TEST

ADC

VrefGENERATOR

FRONT END

DIGITALPLL MOTOR

CONTROL

AUDIOPROCESSOR

EBUINTERFACE

ERRORCORRECTOR

MICROCONTROLLERINTERFACE

PRE-PROCESSING

CONTROLFUNCTION

CONTROLPART

EFMDEMODULATOR

SRAM

RAMADDRESSER

OUTPUTSTAGES

FLAGS

6

8

9

11

52

51

53

54

15

17

14

18

20

23

29

13

21

22

24

25

50

35

36

38

37

58

5762 63 42 41 40 43

3 4 5 7 10 1 12 16 2 19 32 39 49 56 30 47 59

26

27

28

64

33

34

61

60

31

48

46

45

44

VRL

VRH

Iref

R2

SCL

SDA

RAB

SILD

HFIN

HFREF

ISLICE

TEST1

TEST2

TEST3

SELPLL

CRIN

CROUT

CL16

CL11

CL4

SBSY

SFSY

SUB

RCK

STATUS

RESET

R1

D1 D2 D3 D4 IrefT VSSA1 VSSA3 VDDA2 VSSD2 VSSD4 VDDD2(P)

VSSA2 VDDA1 VSSD1 VSSD3 VDDD1(P) VDDD3(C)

V1 V2 V3 V4 V5 KILL

TEST4

DATA

WCLK

SCLK

DOBM

C2FAIL

MOTO2

MOTO1

LDON

SL

FO

RA

CFLG

SAA7377

MGR291

1998 Jul 06 5



SAA7377

6 PINNING

SYMBOL PIN DESCRIPTION

VSSA1 1(1) analog ground 1

VDDA1 2(1) analog supply voltage 1

D1 3 unipolar current input (central diode signal input)



VRL 6 reference voltage input for ADC


R1 8 unipolar current input (satellite diode signal input)

R2 9 unipolar current input (satellite diode signal input)

IrefT 10 current reference output for ADC calibration

VRH 11 reference voltage output from ADC


SELPLL 13 selects whether internal clock multiplier PLL is used

ISLICE 14 current feedback output from data slicer

HFIN 15 comparator signal input


HFREF 17 comparator common mode input

Iref 18 reference current output pin (nominally 0.5VDD)

VDDA2 19(1) analog supply voltage 2

TEST1 20 test control input 1; this pin should be tied LOW

CRIN 21 crystal/resonator input

CROUT 22 crystal/resonator output


CL16 24 16.9344 MHz system clock output

CL11 25 11.2896 or 5.6448 MHz clock output (3-state)

RA 26 radial actuator output

FO 27 focus actuator output

SL 28 sledge control output


VDDD1(P) 30(1) digital supply voltage 1 for periphery

DOBM 31 bi-phase mark output (externally buffered; 3-state)

VSSD1 32(1) digital ground 1

MOTO1 33 motor output 1; versatile (3-state)

MOTO2 34 motor output 2; versatile (3-state)

SBSY 35 subcode block sync output (3-state)

SFSY 36 subcode frame sync output (3-state)

RCK 37 subcode clock input

SUB 38 P-to-W subcode output bits (3-state)


V5 40 versatile output pin 5

1998 Jul 06 6



SAA7377

Note

1. All supply pins must be connected to the same external power supply voltage.

V4 41 versatile output pin 4

V3 42 versatile output pin 3 (open-drain)

KILL 43 kill output (programmable; open-drain)

TEST4 44 test output pin; this pin should be left unconnected

DATA 45 serial data output (3-state)

WCLK 46 word clock output (3-state)

VDDD2(P) 47(1) digital supply voltage 2 for periphery

SCLK 48 serial bit clock output (3-state)


CL4 50 4.2336 MHz microcontroller clock output

SDA 51 microcontroller interface data I/O line (open-drain output)

SCL 52 microcontroller interface clock line input

RAB 53 microcontroller interface R/W and load control line input (4-wire bus mode)

SILD 54 microcontroller interface R/W and load control line input (4-wire-bus mode)

n.c. 55 not connected


RESET 57 power-on reset input (active LOW)

STATUS 58 servo interrupt request line/decoder status register output (open-drain)

VDDD3(C) 59(1) digital supply voltage 3 for core

C2FAIL 60 indication of correction failure output (open-drain)

CFLG 61 correction flag output (open-drain)

V1 62 versatile input pin 1

V2 63 versatile input pin 2

LDON 64 laser drive on output (open-drain)

SYMBOL PIN DESCRIPTION

1998 Jul 06 7



SAA7377

Fig.2 Pin configuration.


SAA7377

MGR292

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

VSSA1

VDDA1

D1

D2

D3

VRL

D4

R1

R2

IrefT

VRH

VSSA2

SELPLL

ISLICE

HFIN

VSSA3

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

SCLK

VDDD2(P)

WCLK

DATA

TEST4

KILL

V3

V4

V5

VSSD2

SUB

RCK

SFSY

SBSY

MOTO2

MOTO1

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

HF

RE

F

I ref

VD

DA

2

TE

ST

1

CR

IN

CR

OU

T

TE

ST

2

CL1

6

CL1

1

RA

FO SL

TE

ST

3

VD

DD

1(P

)

DO

BM

VS

SD

1

LDO

N

V2

V1

CF

LG

C2F

AIL

VD

DD

3(C

)

ST

AT

US

RE

SE

T

VS

SD

4

n.c.

SIL

D

RA

B

SC

L

SD

A

CL4

VS

SD

3

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

1998 Jul 06 8



SAA7377

7 FUNCTIONAL DESCRIPTION

7.1 Decoder part

7.1.1 PRINCIPLE OPERATIONAL MODES OF THE DECODER

The decoding part operates at single-speed and supportsa full audio specification.

A simplified data flow through the decoder part isillustrated in Fig.6.

7.1.2 CRYSTAL FREQUENCY SELECTION

The SAA7377, which has an internal phase-locked loopclock multiplier, can be used with 33.8688, 16.9344 or8.4672 MHz crystal frequencies by setting register B andSELPLL as shown in Table 1. The internal clock multiplier,controlled by SELPLL, should only be used if a8.4672 MHz crystal, ceramic resonator or external clock ispresent. It should be noted that the CL11 output is a5.6448 MHz clock if a 16.9344 MHz external clock is used.

Table 1 Crystal frequency selection

7.1.3 STANDBY MODES

The SAA7377 may be placed in two standby modesselected by register B (it should be noted that the devicecore is still active)

Standby 1: “CD-STOP” mode. Most I/O functions areswitched off.

Standby 2: “CD-PAUSE” mode. Audio output featuresare switched off, but the motor loop, the motor outputand the subcode interfaces remain active. This is alsocalled a “Hot Pause”.

In the standby modes the various pins will have thefollowing values;

MOTO1 and MOTO2: put in high-impedance, PWMmode (standby 1 and RESET, operating in standby 2).Put in high-impedance, PDM mode (standby 1 andRESET, operating in standby 2).

SCL, SDA, SILD and RAB: no interaction. Normaloperation continues.

SCLK, WCLK, DATA, CL11 and DOBM: 3-state in bothstandby modes. Normal operation continues after reset.

REGISTER B SELPLLCRYSTAL FREQUENCY

(MHz)

00xx 0 33.8688

00xx 1 8.4672

01xx 0 16.9344

CRIN, CROUT, CL16 and CL4: no interaction. Normaloperation continues.

V1, V2, V3, V4, V5, CFLG and C2FAIL: no interaction.Normal operation continues.

7.2 Crystal oscillator

The crystal oscillator is a conventional 2 pin designoperating between 8 and 35 MHz. This oscillator iscapable of operating with ceramic resonators and also withboth fundamental and third overtone crystals. Externalcomponents should be used to suppress the fundamentaloutput of the third overtone crystals as shown in Figs 3and 4. Typical oscillation frequencies required are 8.4672,16.9344 or 33.8688 MHz depending on the internal clocksettings used and whether or not the clock multiplier isenabled.

Fig.3 8.4672 MHz fundamental configuration.

8.4672 MHzCRINCROUT

SAA7377

22 pF22 pF

330 Ω

100 kΩ

OSCILLATOR

MGR293

Fig.4 33.8688 MHz overtone configuration.

OSCILLATOR

33.8688 MHzCRINCROUT

SAA7377

3.3 µH

1 nF10 pF10 pF

330 Ω

100 kΩ

MGR294

1998 Jul 06 9



SAA7377

7.3 Data slicer and clock regenerator

The SAA7377 has an integrated slice level comparatorwhich can be clocked by the crystal frequency clock, or8 times the crystal frequency clock (if SELPLL is set HIGHwhile using an 8.4672 MHz crystal, and register 4 is setto 0xxx). The slice level is controlled by an internal currentsource applied to an external capacitor under the controlof the Digital Phase-Locked Loop (DPLL).

Regeneration of the bit clock is achieved with an internalfully digital PLL. No external components are required andthe bit clock is not output. The PLL has two registers(8 and 9) for selecting bandwidth and equalization.

For certain applications an off-track input is necessary.This is internally connected from the servo part (its polaritycan be changed by the foc_parm1 parameter), but may beinput via the V1 pin if selected by register C. If this flag isHIGH, the SAA7377 will assume that its servo part isfollowing on the wrong track and will flag all incoming HFdata as incorrect.

7.4 Demodulator

7.4.1 FRAME SYNC PROTECTION

A double timing system is used to protect the demodulatorfrom erroneous sync patterns in the serial data.

The master counter is only reset if:

• A sync coincidence detected; sync pattern occurs588 ±1 EFM clocks after the previous sync pattern

• A new sync pattern is detected within ±6 EFM clocks ofits expected position.

The sync coincidence signal is also used to generate thePLL lock signal, which is active HIGH after 1 synccoincidence found, and reset LOW if, during 61consecutive frames, no sync coincidence is found. ThePLL lock signal can be accessed via the SDA or STATUSpins selected by register 2 and 7.

Also incorporated in the demodulator is a Run Length 2(RL2) correction circuit. Every symbol detected as RL2 willbe pushed back to RL3. To do this, the phase error of bothedges of the RL2 symbol are compared and the correctionis executed at the side with the highest error probability.

7.4.2 EFM DEMODULATION

The 14-bit EFM data and subcode words are decoded into8-bit symbols.

Fig.5 Data slicer showing typical application components.

47 pF

22 nF

2.2 kΩ HFIN

HFREF

Iref

ISLICE

22 kΩ

100 nF

2.2 nF

HFinput

crystalclock

D Q

DPLL

1/2VDD

VSSA VSS

VSSA

MGA368 - 1VDD

100 µA

100 µA

1998Jul06

10

Philips S

emiconductors

Product specifications

Digital servo processor and C

ompact D

iscdecoder (C

D7)

SA

A7377

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SUBCODEPROCESSOR

DIGITAL PLL ANDDEMODULATOR

FIFO

ERRORCORRECTOR

FADE/MUTE/INTERPOLATE

DIGITALFILTER

PHASECOMPENSATION

DE-EMPHASISFILTERKILL

1

01

0

1

0

1

0 I2S-BUSINTERFACE

SCLKWCLKDATA

reg 3

reg C

reg 3

reg F

reg A

0 : reg D = xx01

V4 SUBCODEINTERFACE

MICROCONTROLLERINTERFACE

CD GRAPHICSINTERFACE

EBUINTERFACE

SBSYSFSYSUB

DOBM

V4

SDA

output fromdata slicer

1 : reg 3 = xx10(1fs mode)

0 : reg 3 ≠ xx10 1 : no pre-emphasis detected OR reg D = 01xx (de-emphasis signal at V5)0 : pre-emphasis detected AND reg D ≠ 01xx

KILLV3

MGD039

Fig.6 Simplified data flow of decoder functions.

1998 Jul 06 11



SAA7377

7.5 Subcode data processing

7.5.1 Q-CHANNEL PROCESSING

The 96-bit Q-channel word is accumulated in an internalbuffer. The last 16 bits are used internally to perform aCyclic Redundancy Check (CRC). If the data is good, theSUBQREADY-I signal will go LOW. SUBQREADY-I canbe read via the SDA or STATUS pins, selected viaregister 2. Good Q-channel data may be read from SDA.

7.5.2 EIAJ 3 AND 4-WIRE SUBCODE (CD GRAPHICS)INTERFACES

Data from all the subcode channels (P-to-W) may be readvia the subcode interface, which conforms toEIAJ CP-2401. The interface is enabled and configured aseither a 3-wire or 4-wire interface via register F. Thesubcode interface output formats are illustrated in Fig.7,where the RCK signal is supplied by another device suchas a CD graphics decoder.

7.5.3 V4 SUBCODE INTERFACE

Data of subcode channels, Q-to-W, may be read via pin V4if selected via register D. The format is similar to RS232and is illustrated in Fig.8. The subcode sync word isformed by a pause of 200 µs minimum. Each subcode bytestarts with a logic 1 followed by 7 bits (Q-to-W). The gapbetween bytes is variable between 11.3 µs and 90 µs.

The subcode data is also available in the EBU output(DOBM) in a similar format.

Fig.7 EIAJ subcode (CD graphics) interface format.


SBSY

SFSY

RCK

SUB

SFSY

RCK

SUB

SFSY

RCK

SUB

EIAJ 4-wire subcode interface

EIAJ 3-wire subcode interface

SF0 SF1 SF2 SF3 SF97 SF0 SF1

P-W P-W P-W

P-W P-W P-W

P Q R S T U V W

MBG410

SF0 SF1 SF2 SF3 SF97 SF0 SF1

1998 Jul 06 12



SAA7377

Fig.8 Subcode format and timing on pin V4.

W96 1 Q R S T U V W 1 Q

200 µsmin

11.3µs

11.3 µs min90 µs max

MGD038

7.6 FIFO and error corrector

The SAA7377 has a ±8 frame FIFO. The error corrector isa t = 2, e = 4 type, with error corrections on both C1(32 symbol) and C2 (28 symbol) frames. Four symbols areused from each frame as parity symbols. This errorcorrector can correct up to two errors on the C1 level andup to four errors on the C2 level.

The error corrector also contains a flag processor. Flagsare assigned to symbols when the error corrector cannotascertain if the symbols are definitely good. C1 generatesoutput flags which are read after (de-interleaving) by C2,to help in the generation of C2 output flags.

The C2 output flags are used by the interpolator forconcealment of uncorrectable errors. They are also outputvia the EBU signal (DOBM).

7.6.1 FLAGS OUTPUT (CFLG)

The flags output pin CFLG (open-drain) shows the statusof the error corrector and interpolator and is updated everyframe (7.35 kHz). In the SAA7377 chip a 1-bit flag ispresent on the CFLG pin as illustrated in Fig.9. This signalshows the status of the error corrector and interpolator.

The first flag bit, F1, is the absolute time sync signal, theFIFO-passed subcode sync and relates the position of thesubcode sync to the audio data (DAC output). This flagmay also be used in a super FIFO or in the synchronizationof different players. The output flags can be madeavailable at bit 4 of the EBU data format (LSB of the 24-bitdata word), if selected by register A.

Fig.9 Flag output timing diagram.


F1 F2 F3 F4 F5 F6 F7 F8 F1F8

11.3µs 33.9 µs33.9 µs

MGD037

1998 Jul 06 13



SAA7377

Table 2 Output flags

F1 F2 F3 F4 F5 F6 F7 F8 DESCRIPTION

0 x x x x x x x no absolute time sync

1 x x x x x x x absolute time sync

x 0 0 x x x x x C1 frame contained no errors

x 0 1 x x x x x C1 frame contained 1 error

x 1 0 x x x x x C1 frame contained 2 errors

x 1 1 x x x x x C1 frame uncorrectable

x x x 0 0 x x 0 C2 frame contained no errors

x x x 0 0 x x 1 C2 frame contained 1 error

x x x 0 1 x x 0 C2 frame contained 2 errors



x x x 1 1 x x 1 C2 frame uncorrectable

x x x x x 0 0 x no interpolations

x x x x x 0 1 x at least one 1 sample interpolation

x x x x x 1 0 x at least one hold and no interpolations

x x x x x 1 1 x at least one hold and one 1 sample interpolation

7.6.2 C2FAIL

The C2FAIL pin indicates that invalid data has occurred onthe I2S-bus interface. However, due to the structure of thecorrector it is impossible to determine which byte hasfailed. C2FAIL will go LOW for 140 µs when invalid data isdetected, this data may then occur 15 ms before or afterthe pin is activated.

7.7 Audio functions

7.7.1 DE-EMPHASIS AND PHASE LINEARITY

When pre-emphasis is detected in the Q-channelsubcode, the digital filter automatically includes ade-emphasis filter section. When de-emphasis is notrequired, a phase compensation filter section controls thephase of the digital oversampling filter to ≤ ±1° within theband 0 to 16 kHz. With de-emphasis the filter is not phaselinear.

If the de-emphasis signal is set to be available at V5,selected via register D, then the de-emphasis filter isbypassed.

7.7.2 DIGITAL OVERSAMPLING FILTER

The SAA7377 contains a 2 to 4 times oversampling IIRfilter. The filter specification of the 4 times oversamplingfilter is given in Table 3.

These attenuations do not include the sample-and-hold atthe external DAC output or the DAC post filter. When usingthe oversampling filter, the output level is scaled −0.5 dBdown, to avoid overflow on full-scale sine wave inputs(0 to 20 kHz).

Table 3 Filter specification

PASS BAND STOP BAND ATTENUATION

0 to 9 kHz − ≤0.001 dB

19 to 20 kHz − ≤0.03 dB

− 24 kHz ≥25 dB

− 24 to 27 kHz ≥38 dB

− 27 to 35 kHz ≥40 dB

− 35 to 64 kHz ≥50 dB

− 64 to 68 kHz ≥31 dB

− 68 kHz ≥35 dB

− 69 to 88 kHz ≥40 dB

1998 Jul 06 14



SAA7377

7.7.3 CONCEALMENT

A 1-sample linear interpolator becomes active if a singlesample is flagged as erroneous but cannot be corrected.The erroneous sample is replaced by a level midwaybetween the preceding and following samples. Left andright channels have independent interpolators. If morethan one consecutive non-correctable sample is found, thelast good sample is held. A 1-sample linear interpolation isthen performed before the next good sample (see Fig.10).

7.7.4 MUTE, FULL SCALE, ATTENUATION AND FADE

A digital level controller is present on the SAA7377 whichperforms the functions of soft mute, full scale, attenuationand fade; these are selected via register 0:

Mute: signal reduced to 0 in a maximum of 128 steps;3 ms.

Attenuate: signal scaled by −12 dB.

Full scale: ramp signal back to 0 dB level. From mutetakes 3 ms.

Fade: activates a 128 stage counter which allows thesignal to be scaled up/down by 0.07 dB steps

128 = full scale.

120 = −0.5 dB (i.e. full scale if oversampling filterused).

32 = −12 dB.

0 = mute.

7.7.5 PEAK DETECTOR

The peak detector measures the highest audio level(absolute value) on positive peaks for left and rightchannels. The 8 most significant bits are output in theQ-channel data in place of the CRC bits. Bits 81 to 88contain the left peak value (bit 88 = MSB) andbits 89 to 96 contain the right peak value (bit 96 = MSB).The values are reset after reading Q-channel data viaSDA.

Fig.10 Concealment mechanism.

Interpolation Hold Interpolation

MGA372

OK Error OK Error Error Error OK OK

1998 Jul 06 15



SAA7377

7.8 DAC interface

The SAA7377 is compatible with a wide range of digital-to-analog converters (DACs). Nine formats are supported andare given in Table 4. Figures 11 and 12 show the Philips I2S-bus and the EIAJ data formats respectively. All formats areMSB first and fs is 44.1 kHz. The polarity of the WCLK and the data can be inverted; selectable by register 7.

Table 4 DAC interface formats

Note

1. In this mode the first 16 bits contain data, but if any of the fade, attenuate or de-emphasis filter functions are activatedthen the first 18 bits contain data.

REGISTER 3SAMPLE

FREQUENCYNUMBER OF

BITSSCLK (MHz) FORMAT INTERPOLATION

1110 fs 16/18(1) 2.1168 Philips I2S-bus; 16/18 bits(1) yes

0010 fs 16 2.1168 EIAJ 16 bits yes

0110 fs 18 2.1168 EIAJ 18 bits yes

0000 4fs 16 8.4672 EIAJ 16 bits yes

0100 4fs 18 8.4672 EIAJ 18 bits yes

1100 4fs 18 8.4672 Philips I2S-bus; 18 bits yes

0011 2fs 16 4.2336 EIAJ 16 bits yes

0111 2fs 18 4.2336 EIAJ 18 bits yes

1111 2fs 18 4.2336 Philips I2S-bus; 18 bits yes

1998Jul06

16

Philips S

emiconductors



ompact D

iscdecoder (C

D7)

SA

A7377



LEFT CHANNEL DATA (WCLK NORMAL POLARITY)

SCLK

15 14 15 141 0DATA

WCLK

01

MGD036

Fig.11 Philips I2S-bus data format (16-bit word length shown).

SCLK

17 170DATA

WCLK

0

LEFT CHANNEL DATA

MGD035

Fig.12 EIAJ data format (18-bit word length shown).

1998 Jul 06 17



SAA7377

7.9 EBU interface

The bi-phase mark digital output signal at pin DOBM isin accordance with the format defined by the IEC958specification. The DOBM pin can be held LOW andselected via register A.

7.9.1 FORMAT

The digital audio output consists of 32-bit words(‘subframes’) transmitted in bi-phase mark code (twotransitions for a logic 1 and one transition for a logic 0).Words are transmitted in blocks of 384. Table 5 gives theformats.

Table 5 Format

Table 6 Description of Table 5

Table 7 Bit assignment

FUNCTION BITS DESCRIPTION

Sync 0 to 3 −Auxiliary 4 to 7 not used; normally zero

Error flags 4 CFLG error and interpolation flags when selected by register A

Audio sample 8 to 27 first 4 bits not used (always zero). 2’s compliment. LSB = bit 12, MSB = bit 27

Validity flag 28 valid = logic 0

User data 29 used for subcode data (Q-to-W)

Channel status 30 control bits and category code

Parity bit 31 even parity for bits 4 to 30

FUNCTION DESCRIPTION

Sync The sync word is formed by violation of the bi-phase rule and therefore does not contain any data.Its length is equivalent to 4 data bits. The 3 different sync patterns indicate the following situations:sync B: start of a block (384 words), word contains left sample; sync M: word contains left sample(no block start) and sync W: word contains right sample.

Audio sample Left and right samples are transmitted alternately.

Validity flag Audio samples are flagged (bit 28 = 1) if an error has been detected but was uncorrectable. Thisflag remains the same even if data is taken after concealment.

User data Subcode bits Q-to-W from the subcode section are transmitted via the user data bit. This data isasynchronous with the block rate.

Channel status The channel status bit is the same for left and right words. Therefore a block of 384 words contains192 channel status bits. The category code is always CD. The bit assignment is given in Table 7.

FUNCTION BITS DESCRIPTION

Control 0 to 3 copy of CRC checked Q-channel control bits 0 to 3; bit 2 is logic 1 when copypermitted; bit 3 is logic 1 when recording has pre-emphasis

Reserved mode 4 to 7 always zero

Category code 8 to 15 CD: bit 8 = logic 1, all other bits = logic 0

Clock accuracy 28 to 29 set by register A; 10 = level I; 00 = level II; 01 = level III

Remaining 16 to 27 and30 to 191

always zero

1998 Jul 06 18



SAA7377

7.10 KILL circuit

The KILL circuit detects digital silence by testing for anall-zero or all-ones data word in the left or right channelbefore the digital filter. The output is switched active LOWwhen silence has been detected for at least 250 ms, or ifmute is active. Two modes are available which can beselected by register C:

1 pin kill: KILL active LOW indicates silence detected onboth left and right channels.

2 pin kill: KILL active LOW indicates silence detected onleft channel. V3 active LOW indicates silence detectedon right channel.

7.11 The VIA interface

The SAA7377 has five pins that can be reconfigured fordifferent applications (see Table 8).

Table 8 Pin applications

PIN NAMEPIN

NUMBERTYPE

CONTROLREGISTERADDRESS

CONTROLREGISTER

DATAFUNCTION

V1 62 input 1100 xxx1 external off-track signal input

− xxx0 internal off-track signal used, input may be readvia decoder status bit; selected via register 2

V2 63 input − − input may be read via decoder status bit;selected via register 2

V3 42 output 1100 xx0x KILL output for right channel

− x01x output = 0

− x11x output = 1

V4 41 output 1101 0000 4-line motor drive (using V4 and V5)

− xx01 Q-to-W subcode output

− xx10 output = 0

− xx11 output = 1

V5 40 output 1101 01xx de-emphasis output (active HIGH)

− 10xx output = 0

− 11xx output = 1

7.12 Spindle motor control

7.12.1 MOTOR OUTPUT MODES

The spindle motor speed is controlled by a fully integrateddigital servo. Address information from the internal±8 frame FIFO and disc speed information are used tocalculate the motor control output signals. Several outputmodes, selected by register 6, are supported:

• Pulse density, 2-line (true complement output), 1 MHzsample frequency

• PWM output, 2-line, 22.05 kHz modulation frequency

• PWM output, 4-line, 22.05 kHz modulation frequency

• CDV motor mode.

7.12.1.1 Pulse density output mode

In the pulse density mode the motor output pin (MOTO1)is the pulse density modulated motor output signal. A 50%duty factor corresponds with the motor not actuated,higher duty factors mean acceleration, lower meanbraking. In this mode, the MOTO2 signal is the inverse ofthe MOTO1 signal. Both signals change state only on theedges of a 1 MHz internal clock signal. Possibleapplication diagrams are illustrated in Fig.13.

7.12.1.2 PWM output mode (2-line)

In the PWM mode the motor acceleration signal is putin pulse-width modulation form on the MOTO1 output.The motor braking signal is pulse-width modulated on theMOTO2 output. The timing is illustrated in Fig.14. A typicalapplication diagram is illustrated in Fig.15.

1998 Jul 06 19



SAA7377

Fig.13 Motor pulse density application diagrams.

MGA363 - 1

MOTO2

VDD

VSS

MOTO1M

22 kΩ

10 nF

+–

22 kΩ

10 nF

+–

VSS

VSSMOTO1

M

22 kΩ

10 nF

+–

22 kΩ

22 kΩVSS

VDD

VSS

22 kΩ

22 kΩ

Fig.14 2-line PWM mode timing.

rept = 45 µs t 240 nsdead

Accelerate Brake

MOTO1

MOTO2

MGA366

Fig.15 Motor 2-line PWM mode application diagram.

MGA365 - 2VSS

+

M

MOTO1 MOTO2

10 Ω 100 nF

1998 Jul 06 20



SAA7377

7.12.1.3 PWM output mode (4-line)

Using two extra outputs from the versatile pins interface, it is possible to use the SAA7377 with a 4-input motor bridge.The timing is illustrated in Fig.16. A typical application diagram is illustrated in Fig.17.

Fig.16 4-line PWM mode timing.

MOTO1

MOTO2

V4

V5

rept = 45 µs t 240 nsdead

ovlt = 240 ns

Accelerate Brake

MGA367 - 1

Fig.17 Motor 4-line PWM mode application diagram.

MGA364 - 2VSS

+

M

MOTO1

V4

MOTO2

V5

100 nF10 Ω

1998 Jul 06 21



SAA7377

7.12.1.4 CDV/CAV output mode

In the CDV motor mode, the FIFO position will be put inpulse-width modulated form on the MOTO1 pin (carrierfrequency = 300 Hz). The PLL frequency signal will be putin pulse-density modulated form (carrierfrequency = 4.23 MHz) on the MOTO2 pin. The integratedmotor servo is disabled in this mode.

The PWM signal on MOTO1 corresponds to a totalmemory space of 20 frames, therefore the nominal FIFOposition (half full) will result in a PWM output of 60%.

7.12.2 SPINDLE MOTOR OPERATING MODES

The operation modes of the motor servo is controlled byregister 1 (see Table 9).

In the SAA7377 decoder there is an anti-wind-up mode forthe motor servo, selected via register 1. When theanti-wind-up mode is activated the motor servo integratorwill hold if the motor output saturates.

7.12.2.1 Power limit

In start mode 1, start mode 2, stop mode 1 and stopmode 2, a fixed positive or negative voltage is applied tothe motor.

This voltage can be programmed as a percentage of themaximum possible voltage, via register 6, to limit currentdrain during start and stop. The following power limits arepossible;

100% (no power limit), 75%, 50%, or 37% of maximum.

7.12.3 LOOP CHARACTERISTICS

The gain and crossover frequencies of the motor controlloop can be programmed via registers 4 and 5.The following parameter values are possible;

Gains: 3.2, 4.0, 6.4, 8.0, 12.8, 16, 25.6 and 32

Crossover frequency f4: 0.5 Hz, 0.7 Hz, 1.4 Hz, 2.8 Hz

Crossover frequency f3: 0.85 Hz, 1.71 Hz, 3.42 Hz.

7.12.4 FIFO OVERFLOW

If FIFO overflow occurs during Play mode (e.g. as a resultof motor rotational shock), the FIFO will be automaticallyreset to 50% and the audio interpolator tries to conceal asmuch as possible to minimise the effect of data loss.

Table 9 Operating modes

MODE DESCRIPTION

Start mode 1 The disc is accelerated by applying a positive voltage to the spindle motor. No decisions areinvolved and the PLL is reset. No disc speed information is available for the microcontroller.

Start mode 2 The disc is accelerated as in start mode 1, however the PLL will monitor the disc speed. When thedisc reaches 75% of its nominal speed, the controller will switch to jump mode. The motor statussignals selectable via register 2 are valid.

Jump mode Motor servo enabled but FIFO kept reset at 50%, integrator is held. The audio is muted but it ispossible to read the subcode.

Jump mode 1 Similar to jump mode but motor integrator is kept at zero. Used for long jumps where there is a largechange in disc speed.

Play mode FIFO released after resetting to 50%. Audio mute released.

Stop mode 1 Disc is braked by applying a negative voltage to the motor. No decisions are involved.

Stop mode 2 The disc is braked as in stop mode 1 but the PLL will monitor the disc speed. As soon as the discreaches 12% (or 6%, depending on the programmed brake percentage, via register E) of itsnominal speed, the MOTSTOP status signal will go HIGH and switch the motor servo to Off mode.

Off mode Motor not steered.

1998 Jul 06 22



SAA7377

Fig.18 Motor servo mode diagram.

MGA362 - 2

G

f4f BW3f

7.13 Servo part

7.13.1 DIODE SIGNAL PROCESSING

The photo detector in conventional two-stage three-beamcompact disc systems normally contains six discretediodes. Four of these diodes (three for single Foucaultsystems) carry the central aperture signal (CA) while theother two diodes (satellite diodes) carry the radial trackinginformation. The CA signal is processed into an HF signal(for the decoder function) and LF signal (information for thefocus servo loop) before it is supplied to the SAA7377.

The analog signals from the central and satellite diodesare converted into a digital representation usinganalog-to-digital converters (ADCs). The ADCs aredesigned to convert unipolar currents into a digital code.The dynamic range of the input currents is adjustablewithin a given range, which is dependent on the value ofthe external resistor connected to pin IrefT. The maximumcurrent for the central diodes and satellite diodes is givenin the following formulae;

µA

µA

The VRH voltage is internally generated by control circuitrywhich ensures that the VRH voltage is adjusted dependingon the spread of internal capacitors, using the reference

Iin max central,( )2.4 10

6×RIrefT

------------------------

=

Iin max satell ite,( )1.2 10

6×RIrefT

------------------------

=

current generated by the external resistor on IrefT. In theapplication VRL is connected to VSSA1. The maximum inputcurrents for a range of resistors is given Table 10.

Table 10 Maximum current input

This mode of VRH automatic adjustment can be selectedby the preset latch command.

Alternatively, the dynamic range of the input currents canbe made dependent on the ADC reference voltages VRLand VRH. The maximum current for the central diodes andsatellite diodes is given in the following formulae;

RIrefT (kΩ)DIODE INPUT CURRENT RANGE

D1 TO D4 (µA) R1 AND R2 (µA)

220 10.909 5.455

240 10.000 5.000

270 8.889 4.444

300 8.000 4.000

330 7.273 3.636

360 6.667 3.333

390 6.154 3.077

430 5.581 2.791

470 5.106 2.553

510 4.706 2.353

560 4.286 2.143

620 3.871 1.935

1998 Jul 06 23



SAA7377

µA

µA

Where fsys = 4.2336 MHz.

VRH is generated internally, and there are 32 levels whichcan be selected under software control via the preset latchcommand. With this command the VRH voltage can be setto 2.5 V then modified, decremented one level orincremented, by re-sending the command the requirednumber of times. In the application VRL is connected toVSSA1.

7.13.2 SIGNAL CONDITIONING

The digital codes retrieved from the ADCs are applied tologic circuitry to obtain the various control signals. Thesignals from the central aperture diodes are processed toobtain a normalised focus error signal.

where the detector set-up is assumed as shown in Fig.19.

In the event of single Foucault focusing method, the signalconditioning can be switched under software control suchthat the signal processing is as follows;

Iin max central,( ) fsys VRH VRL–( ) 1.0 106–×××=

Iin max satell ite,( ) fsys VRH VRL–( ) 0.5 106–×××=

FEnD1 D2–D1 D2+----------------------

D3 D4–D3 D4+----------------------–=

FEn 2D1 D2–D1 D2+----------------------×=

The error signal, FEn, is further processed by aproportional integral and differential (PID) filter section.

A Focus OK (FOK) flag is generated by means of thecentral aperture signal and an adjustable reference level.This signal is used to provide extra protection for thetrack-loss (TL) generation, the focus start-up procedureand the drop out detection.

The radial or tracking error signal is generated by thesatellite detector signals R1 and R2. The radial error signalcan be formulated as follows;

where the index ‘s’ indicates the automatic scalingoperation which is performed on the radial error signal.This scaling is necessary to avoid non-optimum dynamicrange usage in the digital representation and reduces theradial bandwidth spread. Furthermore, the radial errorsignal will be made free from offset during start up of thedisc.

The four signals from the central aperture detectors,together with the satellite detector signals generate a trackposition signal (TPI) which can be formulated as follows;

TPI = sign [(D1 + D2 + D3 + D4) − (R1 + R2) × sum_gain]

Where the weighting factor sum_gain is generatedinternally by the SAA7377 during initialization.

REs R1 R2–( ) re_gain R1 R2–( ) re_offset×+×=

Fig.19 Detector arrangement.


D3

D1

D2

SATELLITEDIODE R1

SATELLITEDIODE R2

D1

D3

D2

D4

SATELLITEDIODE R1

SATELLITEDIODE R2

D1

D2

D3

D4

SATELLITEDIODE R1

SATELLITEDIODE R2

single Foucault astigmatic focus double Foucault

MBG422

1998 Jul 06 24



SAA7377

7.13.3 FOCUS SERVO SYSTEM

7.13.3.1 Focus start-up

Five initially loaded coefficients influence the start-upbehaviour of the focus controller. The automaticallygenerated triangle voltage can be influenced by3 parameters; for height (ramp_height) and DC offset(ramp_offset) of the triangle and its steepness(ramp_incr).

For protection against false focus point detections twoparameters are available which are an absolute level onthe CA-signal (CA_start) and a level on the FEn signal(FE_start). When this CA level is reached the FOK signalbecomes true.

If the FOK signal is true and the level on the FEn signal isreached, the focus PID is enabled to switch on when thenext zero crossing is detected in the FEn signal.

7.13.3.2 Focus position control loop

The focus control loop contains a digital PID controllerwhich has 5 parameters which are available to the user.These coefficients influence the integrating (foc_int),proportional (foc_lead_length, part of foc_parm3) anddifferentiating (foc_pole_lead, part of foc_parm1) action ofthe PID and a digital low-pass filter (foc_pole_noise, partof foc_parm2) following the PID. The fifth coefficientfoc_gain influences the loop gain.

7.13.3.3 Drop-out detection

This detector can be influenced by one parameter(CA_drop). The FOK signal will become false and theintegrator of the PID will hold if the CA signal drops belowthis programmable absolute CA level. When the FOKsignal becomes false it is assumed, initially, to be causedby a black dot.

7.13.3.4 Focus loss detection and fast restart

Whenever FOK is false for longer than approximately3 ms, it is assumed that the focus point is lost. A fastrestart procedure is initiated which is capable of restartingthe focus loop within 200 to 300 ms depending on theprogrammed coefficients of the microcontroller.

7.13.3.5 Focus loop gain switching

The gain of the focus control loop (foc_gain) can bemultiplied by a factor of 2 or divided by a factor of 2 duringnormal operation. The integrator value of the PID iscorrected accordingly. The differentiating (foc_pole_lead)

action of the PID can be switched at the same time as thegain switching is performed.

7.13.3.6 Focus automatic gain control loop

The loop gain of the focus control loop can be correctedautomatically to eliminate tolerances in the focus loop.This gain control injects a signal into the loop which is usedto correct the loop gain. Since this decreases the optimumperformance, the gain control should only be activated fora short time (for example, when starting a new disc).

7.13.4 RADIAL SERVO SYSTEM

7.13.4.1 Level initialization

During start-up an automatic adjustment procedure isactivated to set the values of the radial error gain (re_gain),offset (re_offset) and satellite sum gain (sum_gain) for TPIlevel generation. The initialization procedure runs in aradial open loop situation and is ≤ 300 ms. This start-uptime period may coincide with the last part of the motorstart-up time period.

Automatic gain adjustment: as a result of thisinitialization the amplitude of the RE signal is adjusted towithin ±10% around the nominal RE amplitude.

Offset adjustment: the additional offset in RE due to thelimited accuracy of the start-up procedure is less than± 50 nm.

TPI level generation: the accuracy of the initializationprocedure is such that the duty factor range of TPIbecomes 0.4 < duty factor < 0.6 (definition of dutyfactor = TPI HIGH/TPI period).

7.13.4.2 Sledge control

The microcontroller can move the sledge in both directionsvia the steer sledge command.

7.13.4.3 Tracking control

The actuator is controlled using a PID loop filter with userdefined coefficients and gain. For stable operationbetween the tracks, the S-curve is extended over ± 0.75 ofthe track. On request from the microcontroller, S-curveextension over ± 2.25 tracks is used, automaticallychanging to access control when exceeding those2.25 tracks.

Both modes of S-curve extension make use of atrack-count mechanism. In this mode, track countingresults in an ‘automatic return-to-zero track’, to avoidmajor music rhythm disturbances in the audio output forimproved shock resistance.

1998 Jul 06 25



SAA7377

The sledge is continuously controlled, or provided withstep pulses to reduce power consumption using thefiltered value of the radial PID output. Alternatively, themicrocontroller can read the average voltage on the radialactuator and provide the sledge with step pulses to reducepower consumption. Filter coefficients of the continuoussledge control can be preset by the user.

7.13.4.4 Access

The access procedure is divided into two different modes(see Table 11), depending on the requested jump size.

Table 11 Access modes

Note

1. Microcontroller presettable.

The access procedure makes use of a track countingmechanism, a velocity signal based on a fixed number oftracks passed within a fixed time interval, a velocity setpoint calculated from the number of tracks to go and a userprogrammable parameter indicating the maximum sledgeperformance.

If the number of tracks remaining is greater than thebrake_distance then the sledge jump mode should beactivated, or, the actuator jump should be performed.The requested jump size together with the required sledgebreaking distance at maximum access speed defines thebrake_distance value.

During the actuator jump mode, velocity control with a PIcontroller is used for the actuator. The sledge is thencontinuously controlled using the filtered value of the radialPID output. All filter parameters (for actuator and sledge)are user programmable.

In the sledge jump mode maximum power (userprogrammable) is applied to the sledge in the correctdirection while the actuator becomes idle (the contents ofthe actuator integrator leaks to zero just after the sledgejump mode is initiated).

ACCESSTYPE

JUMP SIZE(1) ACCESSSPEED

Actuator jump 1 - brake_distance decreasingvelocity

Sledge jump brake_distance - 32768 maximumpower tosledge(1)

7.13.4.5 Radial automatic gain control loop

The loop gain of the radial control loop can be correctedautomatically to eliminate tolerances in the radial loop.This gain control injects a signal into the loop which is usedto correct the loop gain. Since this decreases the optimumperformance, the gain control should only be activated fora short time (for example, when starting a new disc).

This gain control differs from the level initialization.The level initialization should be performed first.The disadvantage of using the level initialization withoutthe gain control is that only tolerances from the front-endare reduced.

7.13.5 OFF-TRACK COUNTING

The track position signal (TPI) is a flag which is used toindicate whether the radial spot is positioned on the track,with a margin of ±1⁄4 of the track-pitch. In combination withthe radial polarity flag (RP) the relative spot position overthe tracks can be determined. These signals are, however,afflicted with some uncertainties caused by;

• Disc defects such as scratches and fingerprints

• The HF information on the disc, which is considered asnoise by the detector signals.

In order to determine the spot position with sufficientaccuracy, extra conditions are necessary to generate atrack loss signal (TL) and an off-track counter value. Theseextra conditions influence the maximum speed and thisimplies that, internally, one of the following three countingstates is selected;

1. Protected state: used in normal play situations. A goodprotection against false detection caused by discdefects is important in this state.

2. Slow counting state: used in low velocity track jumpsituations. In this state a fast response is importantrather than the protection against disc defects (if thephase relationship between TL and RP of 1⁄2π radiansis affected too much, the direction cannot then bedetermined accurately).

3. Fast counting state: used in high velocity track jumpsituations. Highest obtainable velocity is the mostimportant feature in this state.

1998 Jul 06 26



SAA7377

7.13.6 DEFECT DETECTION

Fig.20 Block diagram of defect detector.


DECIMATIONFILTER

FASTFILTER

DEFECTGENERATION

PROGRAMMABLEHOLD-OFF

SLOWFILTER

defectoutputsat1

sat2

+

−

MBG421

A defect detection circuit is incorporated into theSAA7377. If a defect is detected, the radial and focus errorsignals may be zeroed, resulting in better playability. Thedefect detector can be switched off, applied only to focuscontrol or applied to both focus and radial controls undersoftware control (part of foc_parm1).

The defect detector (see Fig.20) has programmable setpoints selectable by the parameter defect_parm.

7.13.7 OFF-TRACK DETECTION

During active radial tracking, off-track detection has beenrealised by continuously monitoring the off-track countervalue. The off-track flag becomes valid whenever theoff-track counter value is not equal to zero. Depending onthe type of extended S-curve, the off-track counter is resetafter 0.75 extend or at the original track in the 2.25 trackextend mode.

7.13.8 HIGH-LEVEL FEATURES

7.13.8.1 Interrupt mechanism and STATUS pin

The STATUS pin is an output which is active LOW, itsoutput is selected by register 7 to be either the status bit(active LOW) selected by register 2 (only available in4-wire bus mode) or the interrupt signal generated by theservo part.

8 signals from the interrupt status register are selectablefrom the servo part via the interrupt_mask parameter. Theinterrupt is reset by sending the read high-level statuscommand. The 8 signals are as follows:

1. Focus lost: drop out of longer than 3 ms.

2. Subcode ready.

3. Subcode absolute seconds changed.

4. Subcode discontinuity detected: new subcode timebefore previous subcode time, or more than 10 frameslater than the previous subcode time.

5. Radial error: during radial on-track, no new subcodeframe occurs within time defined by playwatchtimeparameter. During radial jump, less than 4 tracks have

been crossed during time defined by jumpwatchtimeparameter.

6. Autosequencer state change.

7. Autosequencer error.

8. Subcode interface blocked: the internal decoderinterface is being used.

It should be noted that if the STATUS pin output is selectedvia register 2 and either the microcontroller writes adifferent value to register 2 or the decoder interface isenabled then the STATUS output will change.

7.13.8.2 Decoder interface

The decoder interface allows registers 0 to F to beprogrammed and subcode Q-channel data to be read viaservo commands. The interface is enabled/disabled by thepreset latch command (and the xtra_preset parameter).

7.13.8.3 Automatic error handling

Three watchdogs are present:

1. Focus: detects focus drop out of longer than 3 ms, setsfocus lost interrupt, switches off radial and sledgeservos, disables drive to disc motor.

2. Radial play: started when radial servo is on-trackmode and a first subcode frame is found. Detectswhen maximum time between two subcode framesexceeds time set by playwatchtime parameter; thensets radial error interrupt, switches radial and sledgeservos off, puts disc motor in jump mode.

3. Radial jump: active when radial servo in long jump orshort jump modes. Detects when the off-track countervalue decreases by less than 4 tracks between tworeadings (time interval set by jumpwatchtimeparameter); then sets radial jump error, switches radialand sledge servos off to cancel jump.

The focus watchdog is always active, the radial watchdogsare selectable via the radcontrol parameter.

1998 Jul 06 27



SAA7377

7.13.8.4 Automatic sequencers and timer interrupts

Two automatic sequencers are implemented (and must beinitialized after power-on):

1. Autostart sequencer: controls the start-up of focus,radial and motor.

2. Autostop sequencer: brakes the disc and shuts downservos.

When the automatic sequencers are not used it is possibleto generate timer interrupts, defined by thetime_parameter coefficient.

7.13.8.5 High-level status

The read high-level status command can be used to obtainthe interrupt, decoder, autosequencer status registers andthe motor start time. Use of the read high-level statuscommand clears the interrupt status register, andre-enables the subcode read via a servo command.

7.13.9 DRIVER INTERFACE

The control signals (pins RA, FO and SL) for themechanism actuators are pulse density modulated. Themodulating frequency can be set to either 1.0584 MHz(DSD mode) or 2.1168 MHz; controlled via the xtra_presetparameter. An analog representation of the output signalscan be achieved by connecting a first-order low-pass filterto the outputs.

During reset (i.e. RESET pin is held LOW) the RA, FO andSL pins are high impedance.

7.13.10 LASER INTERFACE

The LDON pin (open-drain output) is used to switch thelaser off and on. When the laser is on the output is highimpedance. The action of the LDON pin is controlled by thextra_preset parameter; the pin is automatically driven if thefocus control loop is active.

7.13.11 RADIAL SHOCK DETECTOR

The shock detector (see Fig.21) can be switched on duringnormal track following, and detects within an adjustablefrequency whether disturbances in the radial spot positionrelative to the track exceed an adjustable level (controlledby shock_level). Every time the radial tracking error (RE)exceeds this level the radial control bandwidth is switchedto twice its original bandwidth and the loop gain isincreased by a factor of 4.

The shock detection level is adjustable in 16 steps from0 to 100% of the traverse radial amplitude which is sent toan amplitude detection unit via an adjustable band-passfilter (controlled by sledge_parm1); lower corner frequencycan be set at either 0 or 20 Hz, and upper cornerfrequency at 750 or 1850 Hz. The shock detector isswitched off automatically during jump mode.

Fig.21 Block diagram of radial shock detector.

handbook, full pagewidthRE

MGC914

SHOCKOUTPUT

HIGH-PASS FILTER(0 or 20 Hz)

LOW-PASS FILTER(750 or 1850 Hz)

AMPLITUDEDETECTION

1998 Jul 06 28



SAA7377

7.14 Microcontroller interface

Communication on the microcontroller interface can beset-up in two different modes:

1. 4-wire bus mode: protocol compatible with SAA7345(CD6) and TDA1301 (DSIC2) where:

a) SCL = serial bit clock

b) SDA = serial data

c) RAB = R/W control and data strobe (active HIGH)for writing to registers 0 to F, reading status bitselected via register 2 and reading Q-channelsubcode.

d) SILD = R/W control and data strobe (active LOW)for servo commands.

2. I2C-bus mode: I2C-bus protocol where SAA7377behaves as slave device, activated by settingRAB = HIGH and SILD = LOW where:

a) I2C-bus slave address (write mode) = 30H.

b) I2C-bus slave address (read mode) = 31H.

c) Maximum data transfer rate = 400 kbits/s

It should be noted that only servo commands can be usedtherefore, writing to registers 0 to F, reading decoderstatus and reading Q-channel subcode data must beperformed by servo commands.

7.14.1 MICROCONTROLLER INTERFACE (4-WIRE BUS MODE)

7.14.1.1 Writing data to registers 0 to F

The sixteen 4-bit programmable configuration registers,0 to F (see Table 12), can be written to via themicrocontroller interface using the protocol shown inFig.22.

It should be noted that SILD must be held HIGH; A3 to A0identifies the register number and D3 to D0 is the data; thedata is latched into the register on the LOW-to-HIGHtransition of RAB.

7.14.1.2 Writing repeated data to registers 0 to F

The same data can be repeated several times (e.g. for afade function) by applying extra RAB pulses as shown inFig.23. It should be noted that SCL must stay HIGHbetween RAB pulses.

7.14.1.3 Reading decoder status information on SDA

There are several internal status signals, selected viaregister 2, which can be made available on the SDA line;

SUBQREADY-I: LOW if new subcode word is ready inQ-channel register.

MOTSTART1: HIGH if motor is turning at 75% or moreof nominal speed.

MOTSTART2: HIGH if motor is turning at 50% or moreof nominal speed.

MOTSTOP: HIGH if motor is turning at 12% or less ofnominal speed. Can be set to indicate 6% or less(instead of 12% or less) via register E.

PLL Lock: HIGH if sync coincidence signals are found.

V1: follows input on V1 pin.

V2: follows input on V2 pin.

MOTOR-OV: HIGH if the motor servo output stagesaturates.

FIFO-OV: HIGH if FIFO overflows.

SHOCK: MOTSTART2 + PLL Lock + MOTOR-OV +FIFO-OV + servo interrupt signal + OTD (HIGH if shockdetected).

LA-SHOCK: latched SHOCK signal.

The status read protocol is shown in Fig.24. It should benoted that SILD must be held HIGH.

7.14.1.4 Reading Q-channel subcode

To read the Q-channel subcode direct in the 4-wire busmode, the SUBQREADY-I signal should be selected asstatus signal. The subcode read protocol is illustrated inFig.25.

It should be noted that SILD must be held HIGH; aftersubcode read starts, the microcontroller may take as longas it wants to terminate the read operation; when enoughsubcode has been read (1 to 96 bits), terminate reading bypulling RAB LOW.

Alternatively, the Q-channel subcode can be read using aservo command as follows:

• Use the read high-level status command to monitor thesubcode ready signal.

• Send the read subcode command, and read therequired number of bytes (up to 12).

• Send the read high-level status command; to re-enablethe decoder interface.

7.14.1.5 Behaviour of the SUBQREADY-I signal

When the CRC of the Q-channel word is good, and nosubcode is being read, the SUBQREADY-I status signalwill react as shown in Fig.26.

When the CRC is good and the subcode is being read, thetiming in Fig.27 applies.

1998 Jul 06 29



SAA7377

If t1 (SUBQREADY-I status LOW to end of subcode readis below 2.6 ms, then t2 = 13.1 ms (i.e. the microcontrollercan read all subcode frames if it completes the readoperation within 2.6 ms after the subcode is ready). If thiscriterion is not met, it is only possible to guarantee that t3will be below 26.2 ms (approximately).

If subcode frames with failed CRCs are present, the t2 andt3 times will be increased by 13.1 ms for each defectivesubcode frame.

7.14.1.6 Write servo commands

A write data command is used to transfer data (a numberof bytes) from the microcontroller, using the protocolshown in Fig.28. The first of these bytes is the commandbyte and the following are data bytes; the number(between 1 and 7) depends on the command byte.

It should be noted that RAB must be held LOW; thecommand or data is interpreted by the SAA7377 after theHIGH-to-LOW transition of SILD; there must be aminimum time of 70 µs between SILD pulses.

7.14.1.7 Writing repeated data in servo commands

The same data byte can be repeated by applying extraSILD pulses as shown in Fig.29. SCL must stay HIGHbetween the SILD pulses.

7.14.1.8 Read servo commands

A read data command is used to transfer data (statusinformation) to the microcontroller, using the protocolshown in Fig.30. The first byte written determines the typeof command. After this byte a variable number of bytes canbe read. It should be noted that RAB must be held LOW;after the end of the command byte (LOW-to-HIGHtransition on SILD) there must be a delay of 70 µs beforereading data is started (i.e the next HIGH-to-LOWtransition on SILD); there must be a minimum time of 70 µsbetween SILD pulses.

7.14.2 MICROCONTROLLER INTERFACE (I2C-BUS MODE)

Bytes are transferred over the interface in groups (i.e.servo commands) of which there are two types: write datacommands and read data commands.

The sequence for a write data command (that requires3 data bytes) is as follows;

• Send START condition

• Send address 30H (write)

• Write command byte

• Write data byte 1

• Write data byte 2.

• Write data byte 3

• Send STOP condition.

It should be noted that more than one command can besent in one write sequence.

The sequence for a read data command (that reads 2 databytes) is as follows;


• Send address 30H (write)

• Write command byte



• Send address 31H (read)

• Read data byte 1

• Read data byte 2


It should be noted that the timing constraints specified forthe read and write servo commands must still be adheredto.

1998 Jul 06 30



SAA7377

Fig.22 Microcontroller write protocol for registers 0 to F.

A3 A2 A1 A0 D3 D2 D1 D0

SDA (SAA7377)

SCL (microcontroller)

RAB (microcontroller)

SDA (microcontroller)

MGR295

high-impedance

Fig.23 Microcontroller write protocol for registers 0 to F (repeat mode).

A3 A2 A1 A0 D3 D2 D1 D0

SDA (SAA7377)

MGR296



SDA (microcontroller)

high-impedance

Fig.24 Microcontroller read protocol for decoder status on SDA.

SDA (SAA7377)

MGR297

STATUS



SDA (microcontroller) high-impedance

1998 Jul 06 31



SAA7377

Fig.25 Microcontroller protocol for reading Q-channel subcode.

Q1 Q2 Q3 Qn–1SDA (SAA7377)

MGR298

Qn–2 Qn

STATUS

CRCOK



Fig.26 SUBQREADY-I status timing when no subcode is read.

SDA (SAA7377)

10.8 ms 15.4 ms2.3ms

READ start allowed

high

impedanceCRC OK CRC OK

MGR299



1998 Jul 06 32



SAA7377

Fig.27 SUBQREADY-I status timing when subcode is read.

Q1 Q2 Q3 QnSDA (SAA7377)

t 1

t 2t 3

MGR300



Fig.28 Microcontroller protocol for write servo commands.


D7 D6 D5 D4 D3 D2 D1 D0

SDA (SAA7377)

SILD(microcontroller)


SDA(microcontroller)


SDA(microcontroller) COMMAND DATA1 DATA2 DATA3

command or data byte

high-impedance

microcontroller write (one byte: command or data)

microcontroller write (full command)MGR301

1998 Jul 06 33



SAA7377

Fig.29 Microcontroller protocol for repeated data in write servo commands.




microcontroller write (full command)

COMMAND DATA1

MBG413

Fig.30 Microcontroller protocol for read servo commands.


DATA1 DATA2 DATA3

COMMAND



SCL(microcontroller)


SDA (SAA7377)

SDA (SAA7377) D7 D6 D5 D4 D3 D2 D1 D0

data byte

microcontroller read (one data byte)

microcontroller read (full command)

MGR302

1998 Jul 06 34



SAA7377

7.14.3 SUMMARY OF FUNCTIONS CONTROLLED BY REGISTERS 0 TO F

Table 12 Registers 0 to F

REGISTER ADDRESS DATA FUNCTION INITIAL (1)

0(fade andattenuation)

0000 0000 mute reset

0010 attenuate −0001 full scale −0100 step down −0101 step up −

1(motor mode)

0001 x000 motor off mode reset

x 001 motor stop mode 1 −x010 motor stop mode 2 −x011 motor start mode 1 −x100 motor start mode 2 −x101 motor jump mode −x111 motor play mode −x110 motor jump mode 1 −1xxx anti-windup active −0xxx anti-windup off reset

2(status control)

0010 0000 status = SUBQREADY-I reset

0001 status = MOTSTART1 −0010 status = MOTSTART2 −0011 status = MOTSTOP −0100 status = PLL Lock −0101 status = V1 −0110 status = V2 −0111 status = MOTOR-OV −1000 status = FIFO overflow −1001 status = shock detect −1010 status = latched shock detect −1011 status = latched shock detect reset −

3(DAC output)

0011 1100 I2S-bus; 18-bit; 4fs mode reset

1111 I2S-bus; 18-bit; 2fs mode −1110 I2S-bus; 16-bit; fs mode −0000 EIAJ; 16-bit; 4fs −0011 EAIJ; 16-bit; 2fs −0010 EIAJ; 16-bit; fs −0100 EIAJ; 18-bit; 4fs −0111 EIAJ; 18-bit; 2fs −0110 EIAJ; 18-bit; fs −

1998 Jul 06 35



SAA7377

4(motor gain)

0100 x000 motor gain G = 3.2 reset

x001 motor gain G = 4.0 −x010 motor gain G = 6.4 −x011 motor gain G = 8.0 −x100 motor gain G = 12.8 −x101 motor gain G = 16.0 −x110 motor gain G = 25.6 −x111 motor gain G = 32.0 −0xxx disable comparator clock divider reset

1xxx enable comparator clock divider; only if SELLPLL set HIGH −5(motor bandwidth)

0101 xx00 motor f4 = 0.5 Hz reset

xx01 motor f4 = 0.7 Hz −xx10 motor f4 = 1.4 Hz −xx11 motor f4 = 2.8 Hz −00xx motor f3 = 0.85 Hz reset

01xx motor f3 = 1.71 Hz −10xx motor f3 = 3.42 Hz −

6(motor outputconfiguration)

0110 xx00 motor power maximum 37% reset

xx01 motor power maximum 50% −xx10 motor power maximum 75% −xx11 motor power maximum 100% −00xx MOTO1, MOTO2 pins 3-state reset

01xx motor PWM mode −10xx motor PDM mode −11xx motor CDV mode −

7(DAC output andstatus control)

0111 xx00 interrupt signal from servo at STATUS pin reset

xx10 status bit from decoder status register at STATUS pin −x0xx DAC data normal value reset

x1xx DAC data inverted value −0xxx left channel first at DAC (WCLK normal) reset

1xxx right channel first at DAC (WCLK inverted) −8 (PLL loop filterbandwidth)

see Table 13

9(PLL equalization)

1001 0011 PLL loop filter equalization reset

0001 PLL 30 ns over-equalization −0010 PLL 15 ns over-equalization −0100 PLL 15 ns under-equalization −0101 PLL 30 ns under-equalization −


1998 Jul 06 36



SAA7377

Note

1. The initial column shows the power-on reset state.

A(EBU output)

1010 x010 level II clock accuracy (<1000 ppm) reset

x011 level I clock accuracy (<50 ppm) −x110 level III clock accuracy (>1000 ppm) −x111 EBU off - output LOW −0xxx flags in EBU off reset

1xxx flags in EBU on −B(speed control)

1011 00xx 33.8688 MHz crystal present, or 8.4672 MHz crystal withSELPLL set HIGH

reset

01xx 16.9344 MHz crystal present −xx00 standby 1:’CD-STOP’ mode reset

xx10 standby 2:’CD-PAUSE’ mode −xx11 operating mode −

C(versatile pinsinterface)

1100 xxx1 external off-track signal input at V1 −xxx0 internal off-track signal used (V1 may be read via STATUS) reset

xx0x kill-L at KILL output, kill-R at V3 output −001x V3 = 0; single KILL output reset

011x V3 = 1; single KILL output −D(versatile pinsinterface)

1101 0000 4-line motor (using V4 and V5) −xx01 Q-to-W subcode at V4 −xx10 V4 = 0 −xx11 V4 = 1 reset

01xx de-emphasis signal at V5, no internal de-emphasis filter −10xx V5 = 0 −11xx V5 = 1 reset

E 1110 0100 motor brakes to 12% reset

0101 motor brakes to 6% −F(subcodeinterface)

1111 x000 subcode interface off reset

x100 subcode interface on −0xxx 4-wire subcode reset

1xxx 3-wire subcode −


1998 Jul 06 37



SAA7377

Table 13 Loop filter bandwidth

Note

1. The initial column shows the power-on reset state.

REGISTER ADDRESS DATA

FUNCTION

INITIAL (1)LOOPBANDWIDTH

(Hz)

INTERNALBANDWIDTH

(Hz)

LOW-PASSBANDWIDTH

(Hz)

8(PLL loop filterbandwidth)

1000 0000 1640 525 8400 −0001 3279 263 16800 −0010 6560 131 33600 −0100 1640 1050 8400 −0101 3279 525 16800 −0110 6560 263 33600 −1000 1640 2101 8400 −1001 3279 1050 16800 reset

1010 6560 525 33600 −1100 1640 4200 8400 −1101 3279 2101 16800 −1110 6560 1050 33600 −

1998 Jul 06 38



SAA7377

7.14.4 SUMMARY OF SERVO COMMANDS

A list of the servo commands are given in Table 14. It should be noted that these are not fully backwards compatible withDSIC2.

Table 14 CD7 servo commands

Notes

1. These commands only available when internal decoder interface is enabled.

2. <peak_l> and <peak_r> bytes are clocked out LSB first.

3. Decoder status flag information in <dec_stat> is only valid when the internal decoder interface is enabled.

COMMANDS CODE BYTES PARAMETERS

Write commands

Write_focus_coefs1 17H 7 <foc_parm3> <foc_int> <ramp_incr> <ramp_height> <ramp_offset><FE_start> <foc_gain>

Write_focus_coefs2 27H 7 <defect_parm> <rad_parm_jump> <vel_parm2> <vel_parm1><foc_parm1> <foc_parm2> <CA_drop>

Write_focus_command 33H 3 <foc_mask> <foc_stat> <shock_level>

Focus_gain_up 42H 2 <foc_gain> <foc_parm1>

Focus_gain_down 62H 2 <foc_gain> <foc_parm1>

Write_radial coefs 57H 7 <rad_length_lead> <rad_int> <rad_parm_play> <rad_pole_noise><rad_gain> <sledge_parm2> <sledge_parm_1>

Preset_Latch 81H 1 <chip_init>

Radial_off C1H 1 ‘1CH’

Radial_init C1H 1 ‘3CH’

Short_jump C3H 3 <tracks_hi> <tracks_lo> <rad_stat>

Long_jump C5H 5 <brake_dist> <sledge_U_max> <tracks_hi> <tracks_lo> <rad_stat>

Steer_sledge B1H 1 <sledge_level>

Preset_init 93H 3 <re_offset> <re_gain> <sum_gain>

Write_decoder_reg(1) D1H 1 <decoder_reg_data>

Write_parameter A2H 2 <param_ram_addr> <param_data>

Read commands

Read_Q_subcode(1)(2) 0H up to 12 <Q_sub1..10> <peak_l> <peak_r>

Read_status 70H up to 5 <foc_stat> <rad_stat> <rad_int_lpf> <tracks_hi> <tracks_lo>

Read_hilevel_status(3) E0H up to 4 <intreq> <dec_stat> <seq_stat> <motor_start_time>

Read_aux_status F0H up to 3 <re_offset> <re_gain> <sum_gain>

1998 Jul 06 39



SAA7377

7.14.5 SUMMARY OF SERVO COMMAND PARAMETERS

Table 15 Servo command parameters

PARAMETERRAM

ADDRESSAFFECTS

PORVALUE

DETERMINES

foc_parm_1 − focus PID − end of focus lead

defect detector enabling

foc_parm_2 − focus PID − focus low-pass

focus error normalising

foc_parm_3 − focus PID − focus lead length

minimum light level

foc_int 14H focus PID − focus integrator crossover frequency

foc_gain 15H focus PID 70H focus PID loop gain

CA_drop 12H focus PID − sensitivity of drop-out detector

ramp_offset 16H focus ramp − asymmetry of focus ramp

ramp_height 18H focus ramp − peak-to-peak value of ramp voltage

ramp_incr − focus ramp − slope of ramp voltage

FE_start 19H focus ramp − minimum value of focus error

rad_parm_play 28H radial PID − end of radial lead

rad_pole_noise 29H radial PID − radial low-pass

rad_length_lead 1CH radial PID − length of radial lead

rad_int 1EH radial PID − radial integrator crossover frequency

rad_gain 2AH radial PID 70H radial loop gain

rad_parm_jump 27H radial jump − filter during jump

vel_parm1 1FH radial jump − PI controller crossover frequencies

vel_parm2 32H radial jump − jump pre-defined profile

speed_threshold 48H radial jump − maximum speed in fastrad mode

hold_mult 49H radial jump 00H sledge bandwidth during jump

brake_dist_max 21H radial jump − maximum sledge distance allowed in fast actuatorsteered mode

sledge_long_brake 58H radial jump 7FH brake distance of sledge

sledge_Umax − sledge − voltage on sledge during long jump

sledge_level − sledge − voltage on sledge when steered

sledge_parm_1 36H sledge − sledge integrator crossover frequency

sledge_parm_2 17H sledge − sledge low-pass frequencies

sledge gain

sledge operation mode

sledge_pulse1 46H pulsed sledge − pulse width

sledge_pulse2 64H pulsed sledge − pulse height

defect_parm − defect detector − defect detector setting

shock_level − shock detector − shock detector operation

playwatchtime 54H watchdog − radial on-track watchdog time

jumpwatchtime 57H watchdog − radial jump watchdog time-out

1998 Jul 06 40



SAA7377

radcontrol 59H watchdog − enable/disable automatic radial off feature

chip_init − set-up − VRH level setting

enable/disable decoder interface

xtra_preset 4AH set-up 38H laser on/off

RA, FO and SL PDM modulating frequency

microcontroller communication to decoder part

cd6cmd 4DH decoder interface − decoder part commands

interrupt_mask 53H STATUS pin − enabled interrupts

seq_control 42H autosequencer − autosequencer control

focus_start_time 5EH autosequencer − focus start time

motor_start_time1 5FH autosequencer − motor start 1 time

motor_start_time2 60H autosequencer − motor start 2 time

radial_init_time 61H autosequencer − radial initialization time

brake_time 62H autosequencer − brake time

RadCmdByte 63H autosequencer − radial command byte

osc_inc 68H focus/radial AGC − AGC control

frequency of injected signal

phase_shift 67H focus/radial AGC − phase shift of injected signal

level1 69H focus/radial AGC − amplitude of signal injected

level2 6AH focus/radial AGC − amplitude of signal injected

agc_gain 6CH focus/radial AGC − focus/radial gain

PARAMETERRAM

ADDRESSAFFECTS

PORVALUE

DETERMINES

1998 Jul 06 41



SAA7377

8 LIMITING VALUESIn accordance with the Absolute Maximum Rating System (IEC 134).

Notes

1. All VDD and VSS connections must be made externally to the same power supply.

2. Equivalent to discharging a 100 pF capacitor via a 1.5 kΩ series resistor with a rise time of 15 ns.

3. Equivalent to discharging a 200 pF capacitor via a 2.5 µH series inductor.

9 OPERATING CHARACTERISTICSVDD = 3.4 to 5.5 V; VSS = 0 V; Tamb = −10 to +70 °C; unless otherwise specified.

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

VDD supply voltage note 1 −0.5 +6.5 V

VI(max) maximum Input voltage (any input) −0.5 VDD + 0.5 V

VO output voltage (any output) −0.5 +6.5 V

VDDdiff difference between VDDA and VDDD − ± 0.25 V

IO output current (continuous) − ± 20 mA

IIK DC input diode current (continuous) − ± 20 mA

Tamb operating ambient temperature −40 +85 °CTstg storage temperature −55 +125 °CVes electrostatic handling note 2 −2000 +2000 V

note 3 −200 +200 V


Supply

VDD supply voltage 3.4 5.0 5.5 V

IDD supply current VDD = 5 V − 49 − mA

Decoder analog front-end (V DDA = 5 V; VSSA = 0 V; Tamb = 25 °C)

COMPARATOR INPUTS: HFIN AND HFREF

fclk clock frequency note 1 8 − 70 MHz

Vth(sw) switching voltage threshold 1.2 − VDD − 0.8 V

Vtpt HFIN input voltage level − 1.0 − V

REFERENCE GENERATOR: Iref

VIref reference voltage level(pin 18)

− 0.5VDD − V

1998 Jul 06 42



SAA7377

Servo analog part (V DDA = 5 V; VSSA = 0 V; Tamb = 25 °C)

PINS D1 TO D4, R1, R2, VRH, VRL AND IrefT

IrefT input reference current 1.935 − 5.45 µA

RIrefT external resistor on pin 10 220 − 620 kΩVIrefT voltage on reference

current input− 1.2 − V

ID(max) maximum input current forcentral diode input signal

note 2 3.871 − 10.9 µA

IR(max) maximum input current forsatellite diode input signal

note 2 1.935 − 5.45 µA

VRL LOW level reference voltage 0 0 0 V

VRH HIGH level referencevoltage

output state 0; note 3 − 0.5 − V

output state v; note 3 −30% 0.5 × 10v/44.4 +30% V

output state 31;note 3

− 2.5 − V

(THD+N)/S total harmonic distortion plusnoise

at 0 dB; note 4 − −50 −45 dB

S/N signal-to-noise ratio − 55 − dB

PSRR power supply ripple rejectionat VDDA2

note 5 − 45 − dB

Gtol gain tolerance note 6 −12 0 +12 %

∆Gv variation of gain betweenchannels

− − 2 %

αcs channel separation − 60 − dB

Digital inputs

INPUTS: RESET, V1, V2, SELPLL (CMOS INPUT WITH PULL-UP RESISTOR AND HYSTERESIS)

Vthr(sw) switching voltage thresholdrising

− − 0.8VDDD V

Vthf(sw) switching voltage thresholdfalling

0.2VDDD − − V

Vhys hysteresis voltage − 0.33VDDD − V

RI(pu) input pull-up resistance Vi = 0 V − 50 − kΩCin input capacitance − − 10 pF

tresL reset pulse width(active LOW)

RESET only 1 − − µs

INPUTS: SCL, RAB, SILD AND RCK (CMOS INPUT)

VIL LOW level input voltage −0.3 − 0.3VDD V

VIH HIGH level input voltage 0.7VDD − VDD + 0.3 V

ILI input leakage current Vi = 0 − VDD −10 − +10 µA

Cin input capacitance − − 10 pF


1998 Jul 06 43



SAA7377

Digital outputs

OUTPUT: CL4

VOL LOW level output voltage IOL = 1 mA 0 − 0.4 V

VOH HIGH level output voltage IOH = −1 mA VDDD − 0.4 − VDDD V

CL load capacitance − − 25 pF

tr output rise time CL = 20 pF;0.8 to (VDDD − 0.8)

− − 20 ns

tf output fall time CL = 20 pF;(VDDD − 0.8) to 0.8

− − 20 ns

OUTPUT: CL16


VOH HIGH level output voltage IOH = −1 mA VDDD − 0.4 − VDDD V


tr output rise time CL = 20 pF;0.8 − (VDDD − 0.8)

− − 15 ns

tf output fall time CL = 20 pF;(VDDD − 0.8) − 0.8

− − 15 ns

OUTPUTS: V4 AND V5

VOL LOW level output voltage VDDD = 4.5 to 5.5 V;IOL = 10 mA

0 − 1.0 V

VDDD = 3.4 to 5.5 V;IOL = 5 mA

0 − 1.0 V

VOH HIGH level output voltage VDDD = 4.5 to 5.5 V;IOH = −10 mA

VDDD − 1 − VDDD V

VDDD = 3.4 to 5.5 V;IOH = −5 mA

VDDD − 1 − VDDD V


tr output rise time CL = 20 pF;0.8 − (VDDD − 0.8)

− − 10 ns


− − 10 ns

Open-drain outputs

OUTPUTS: CFLG, C2FAIL, STATUS, KILL, V3 AND LDON (OPEN-DRAIN OUTPUT WITH PROTECTION DIODE TO VDD)


IOL LOW level output current − − 2 mA



− − 30 ns


1998 Jul 06 44



SAA7377

3-state outputs

OUTPUTS: CLK, WCLK, DATA AND CL11


VOH HIGH level output voltage IOH = −1 mA VDD − 0.4 − VDD V


tr output rise time CL = 20 pF;0.8 − (VDD − 0.8)

− − 15 ns

tf output fall time CL = 20 pF;(VDD − 0.8) − 0.8

− − 15 ns

IZO output 3-state leakagecurrent

Vi = 0 − VDD −10 − +10 µA

OUTPUT: CL11

tH output HIGH time (relative toclock period)

Vo = 1.5 V 45 50 55 %

OUTPUTS: RA, FO, SL, SBSY, SFSY AND SUB


VOH HIGH level output voltage IOH = −1 mA VDD − 0.4 − VDD V



− − 20 ns


− − 20 ns

IZO 3-state leakage current Vi = 0 − VDD −10 − +10 µA

OUTPUTS: MOTO1, MOTO2 AND DOBM

VOL LOW level output voltage VDD = 4.5 to 5.5 V;IOL = 10 mA

0 − 1.0 V

VDD = 3.4 to 5.5 V;IOL = 5 mA

0 − 1.0 V

VOH HIGH level output voltage VDD = 4.5 to 5.5 V;IOL = −10 mA

VDD − 1 − VDD V

VDD = 3.4 to 5.5 V;IOL = −5 mA

VDD − 1 − VDD V



− − 10 ns


− − 10 ns

IZO 3-state leakage current Vi = 0 − VDD −10 − +10 µA


1998 Jul 06 45



SAA7377

Notes

1. Highest clock frequency at which data slicer produces 1010 output in analog self-test mode.

2. VRL = 0 V, fsys = 4.2336 MHz. The maximum input current depends on the value of the external resistor connectedto IrefT:

a) For D1 to D4: Imax = 2.4/RIrefT ⇒ 2.4/220 kΩ = 10.9 µA

b) For R1 and R2: Imax = 1.2/RIrefT ⇒ 1.2/20 kΩ = 5.45 µA

3. Internal reference source with 32 different output voltages. Selection is achieved during a calibration period or viathe serial interface. The values given are for an unloaded VRH.

4. VRH = 2.5 V and VRL = 0 V, measuring bandwidth: 200 Hz to 20 kHz, fi(ADC) = 1 kHz.

5. fripple = 1 kHz, Vripple = 0.5 V (p-p).

6. Gain of the ADC is defined as GADC = fsys/Imax (counts/µA); thus digital output = Ii × GADC where;

a) Digital output = the number of pulses at the digital output in counts/s and Ii = the DC input current in µA.

b) The maximum input current depends on the system frequency (fsys = 4.2336 MHz) and on VRH − VRL.

c) The gain tolerance is the deviation from the calculated gain regarding note 2.

7. It is recommended that the series resistance of the crystal or ceramic resonator is ≤60 Ω.

Digital input/output

INPUT/OUTPUT: SDA [CMOS INPUT/OPEN-DRAIN I2C-BUS OUTPUT (WITH PROTECTION DIODE TO VDDD)]

VIL LOW level input voltage −0.3 − 0.3VDDD V

VIH HIGH level input voltage 0.7VDDD − VDDD + 0.3 V

IZO 3-state leakage current Vi = 0 − VDDD −10 − +10 µA



IOL LOW level output current − − 4 mA



− − 15 ns

Crystal oscillator

INPUT: CRIN (EXTERNAL CLOCK)

VIL LOW level input voltage −0.3 − 0.3VDD V

VIH HIGH level input voltage 0.7VDD − VDD + 0.3 V

ILI input leakage current −10 − +10 µA


OUTPUT: CROUT; see Figs 3 and 4

fxtal crystal frequency note 7 8 8.4672 35 MHz

gm mutual conductance at100 kHz

− 10 − mA/V

Gv small signal voltage gain Gv = gm × RO − 18 − V/V

Cfb feedback capacitance − − 5 pF

Cout output capacitance − − 10 pF


1998 Jul 06 46



SAA7377

10 OPERATING CHARACTERISTICS (SUBCODE INTERFACE TIMING)VDD = 3.4 to 5.5 V; VSS = 0 V; Tamb = −10 to +70 °C; unless otherwise specified.


Subcode interface timing; see Fig.31

INPUT: RCK

tH input clock HIGH time 2 4 6 µs

tL input clock LOW time 2 4 6 µs

tr input clock rise time − − 80 ns

tf input clock fall time − − 80 ns

tdC delay time SFSY to RCK 10 − 20 µs

OUTPUTS: SBSY, SFSY AND SUB (CL = 20 pF)

tBcy block cycle 12.0 13.3 14.7 ms

tBW SBSY pulse width − − 300 µs

tFcy frame cycle 122 136 150 µs

tFW SFSY pulse width (3-wire mode only) − − 366 µs

tFH SFSY HIGH time − − 66 µs

tFL SFSY LOW time − − 84 µs

tdPAC delay time SFSY to SUB (P data)valid

− − 1 µs

tdAC delay time RCK falling to SUB − − 0 µs

thD hold time RCK to SUB − − 0.7 µs

1998 Jul 06 47



SAA7377

handbook, full pagewidth tW(SBSY)

tW(SFSY)

tr

VDD – 0.8 V

VDD – 0.8 V

tSFSYL

tSFSYH

Tcy(block)

tcy(frame)

tf

td(SFSY−RCK)

td(SFSY−SUB) th(RCK−SUB) td(RCK−SUB)

SBSY

SFSY

RCK

SUB

SFSY(4-wire mode)

SFSY(3-wire mode)

0.8 V

0.8 V

0.8 V

MBG414

Fig.31 Subcode interface timing diagram.

1998 Jul 06 48



SAA7377

11 OPERATING CHARACTERISTICS (I 2S-BUS TIMING)VDD = 3.4 to 5.5 V; VSS = 0 V; Tamb = −10 to +70 °C; unless otherwise specified


I2S-bus timing; see Fig.32

CLOCK OUTPUT: SCLK (CL = 20 pF)

Tcy output clock period sample rate = fs − 472.4 − ns

sample rate = 2fs − 236.2 − ns

sample rate = 4fs − 118.1 − ns

tCH clock HIGH time sample rate = fs 166 − − ns

sample rate = 2fs 83 − − ns


tCL clock LOW time sample rate = fs 166 − − ns



OUTPUTS: WCLK AND DATA (CL = 20 pF)

tsu set-up time sample rate = fs 95 − − ns



th hold time sample rate = fs 95 − − ns



Fig.32 I2S-bus timing diagram.

DDV – 0.8 V

0.8 V

DDV – 0.8 V

0.8 V

t CH

MGD026

t CL

clock period Tcy

SCLK

WCLKDATA

t ht su

1998 Jul 06 49



SAA7377

12 OPERATING CHARACTERISTICS (MICROCONTROLLER INTERFACE TIMING)VDD = 3.4 to 5.5 V; VSS = 0 V; Tamb = −10 to +70 °C; unless otherwise specified.

Notes

1. Negative set-up time means that the data may change after clock transition.


Microcontroller interface timing (4-wire bus mode; writing to registers 0 to F; reading Q-channel subcode anddecoder status); see Figs 33 and 34

INPUTS SCL AND RAB

tCL input LOW time 500 − − ns

tCH input HIGH time 500 − − ns

tr rise time − − 480 ns

tf fall time − − 480 ns

READ MODE (CL = 20 pF)

tdRD delay time RAB to SDA valid − − 50 ns

tPD propagation delay SCL to SDA 700 − 980 ns

tdRZ delay time RAB to SDA high-impedance − − 50 ns

WRITE MODE ((CL = 20 pF)

tsuD set-up time SDA to SCL note 1 700 − − ns

thD hold time SCL to SDA − − 980 ns

tsuCR set-up time SCL to RAB 260 − − ns

tdWZ delay time SDA high-impedance to RAB 0 − − ns

Microcontroller interface timing (4-wire bus mode; servo commands); see Figs 35 and 36

INPUTS SCL AND SILD

tL input LOW time 710 − − ns

tH input HIGH time 710 − − ns

tr rise time − − 240 ns

tf fall time − − 240 ns

READ MODE (CL = 20 pF)

tdLD delay time SILD to SDA valid − − 25 ns

tPD propagation delay SCL to SDA − − 950 ns

tdLZ delay time SILD to SDA high-impedance − − 50 ns

tsCLR set-up time SCL to SILD 480 − − ns

thCLR hold time SCL to SILD 830 − − ns

WRITE MODE (CL = 20 pF)

tsD set-up time SDA to SCL 0 − − ns

thD hold time SCL to SDA 950 − − ns

tsCL set-up time SCL to SILD 480 − − ns

thCL hold time SILD to SCL 120 − − ns

tdPLP delay between two SILD pulses 70 − − µs

tdWZ delay time SDA high-impedance to SILD 0 − − ns

1998 Jul 06 50



SAA7377

Fig.33 4-wire bus microcontroller timing; read mode (Q-channel subcode and decoder status information).

SDA (SAA7377)

SCL

RAB

tr tf tCH

tCLtPD

tdRD

tdRZ

tr tf

DDV – 0.8 V

0.8 V

DDV − 0.8 V

0.8 V

DDV − 0.8 V

0.8 Vhigh-impedance

MGR303

Fig.34 4-wire bus microcontroller timing; write mode (registers 0 to F).


SCL

RAB

t rt f

DDV – 0.8 V

0.8 V

DDV – 0.8 V

0.8 V

t hDtCL

t CH

t dWZ

MBG405

t r t f

DDV – 0.8 V

0.8 Vt CL

tCH

t suCR

t suD

SDA (microcontroller) high-impedance

1998 Jul 06 51



SAA7377

Fig.35 4-wire bus microcontroller timing; read mode (servo commands).


tdLD

thCLRtsCLR

tPD tdLZ

0.8 V

0.8 V

0.8 V

VDD − 0.8 V

VDD − 0.8 V

VDD – 0.8 V

SILD

SCL

SDA(SAA7377)

MGR304

Fig.36 4-wire bus microcontroller timing (servo commands) write mode.


tdPLP

tLtsCL

tdWZ

thCL

tH

thD

tsD tL

0.8 V

0.8 V

0.8 V

VDD - 0.8 V

VDD – 0.8 V

VDD – 0.8 V

SILD

SCL


MBG416

1998Jul06

52

Philips S

emiconductors



ompact D

iscdecoder (C

D7)

SA

A7377


13A

PP

LICAT

ION

INF

OR

MAT

ION

hand

book

, ful

l pag

ewid

th

53 52 51 50

100 nF

100 nF

100 nF

100 nF

100 nF

4964 63 62 61 60 59 58 57 56 55 54

28 29 30 31 3217 18 19 20 21 22 23 24 25 26 27

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

1

7

6

3

1

4

5

2

9

(1)

(3)

LDON

D2

D3D4

D1

D5

D6

RFE

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

TDA1300

(2)

SAA7377

to DOBMtransformer

to poweramplifiers

22 nF

2.2 Ω

VSSA1VDDA1

VDDA

VDD

D1

D2

HF

RE

FLD

ON

D3

VRLD4

R1

R2

IrefTVRHVSSA2SELPLL

ISLICE

HFIN

VSSA3VDDA

I ref

VD

DA

2T

ES

T1

CR

IN

CR

OU

T

TE

ST

2

CL1

6

CL1

1

RA

FO

SL

TE

ST

3

VD

DD

1(P

)

DO

BM

VS

SD

1

V2

V1

CF

LG

C2F

AIL

VD

DD

3CS

TA

TU

S

RE

SE

T

VS

SD

4n.

c.

SIL

D

RA

B

SC

L

SD

A

CL4

VS

SD

3

VDDD

VDDD2(P)

VDDD

WCLK

SCLK

DATA

TEST4

KILL

V3

V4

V5

VSSD2SUB

RCK

SFSY

SBSY

MOTO2

MOTO1

to DAC

to CDgraphics

2.2 Ω

2.2 Ω

2.2Ω

4.7 kΩ

4.7 kΩ

270kΩ

22kΩ

2.2 kΩ

100 nF

microcontrollerinterface

33 µF

33 µF

+V

+V

+V +V

220 pF

220 pF

47 pF

220 pF

220 pF

220 pF

220 pF

100 kΩ

100 kΩ

2.2 nF

MOTORINTERFACE

100 nF

MGR305

Fig.37 Typical SAA7377 application diagram.

(1) The diagram is for 5 V application. For 3.4 Vapplication an additional resistor of 150 kΩ should beconnected between pin 18 and ground.

(2) For crystal oscillator circuit see Figs 3 and 4.

(3) The connections to TDA1300 are shown for singleFoucault mechanisms.

1998 Jul 06 53



SAA7377

14 PACKAGE OUTLINE

UNIT A1 A2 A3 bp c E(1) e HE L Lp Zywv θ

REFERENCESOUTLINEVERSION

EUROPEANPROJECTION ISSUE DATE

IEC JEDEC EIAJ

mm 0.250.10

2.752.55 0.25

0.450.30

0.230.13

14.113.9 0.8

17.4516.95

1.20.8

70

o

o0.16 0.100.161.60

DIMENSIONS (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

1.030.73

SOT393-1 MS-02296-05-2197-08-04

D(1) (1)(1)

14.113.9

HD

17.4516.95

EZ

1.20.8

D

e

θ

E A1A

Lp

detail X

L

(A )3

B

16

y

c

EHA2

D

ZD

A

ZE

e

v M A

1

64

49

48 33

32

17

X

bp

DH

bp

v M B

w M

w M

0 5 10 mm

scale

pin 1 index

QFP64: plastic quad flat package; 64 leads (lead length 1.6 mm); body 14 x 14 x 2.7 mm SOT393-1

Amax.

3.00

1998 Jul 06 54



SAA7377

15 SOLDERING

15.1 Introduction

There is no soldering method that is ideal for all ICpackages. Wave soldering is often preferred whenthrough-hole and surface mounted components are mixedon one printed-circuit board. However, wave soldering isnot always suitable for surface mounted ICs, or forprinted-circuits with high population densities. In thesesituations reflow soldering is often used.

This text gives a very brief insight to a complex technology.A more in-depth account of soldering ICs can be found inour “IC Package Databook” (order code 9398 652 90011).

15.2 Reflow soldering

Reflow soldering techniques are suitable for all QFPpackages.

The choice of heating method may be influenced by largerplastic QFP packages (44 leads, or more). If infrared orvapour phase heating is used and the large packages arenot absolutely dry (less than 0.1% moisture content byweight), vaporization of the small amount of moisture inthem can cause cracking of the plastic body. For moreinformation, refer to the Drypack chapter in our “QualityReference Handbook” (order code 9397 750 00192).

Reflow soldering requires solder paste (a suspension offine solder particles, flux and binding agent) to be appliedto the printed-circuit board by screen printing, stencilling orpressure-syringe dispensing before package placement.

Several methods exist for reflowing; for example,infrared/convection heating in a conveyor type oven.Throughput times (preheating, soldering and cooling) varybetween 50 and 300 seconds depending on heatingmethod. Typical reflow peak temperatures range from215 to 250 °C.

15.3 Wave soldering

Wave soldering is not recommended for QFP packages.This is because of the likelihood of solder bridging due toclosely-spaced leads and the possibility of incompletesolder penetration in multi-lead devices.

CAUTION

Wave soldering is NOT applicable for all QFPpackages with a pitch (e) equal or less than 0.5 mm.

If wave soldering cannot be avoided, for QFPpackages with a pitch (e) larger than 0.5 mm, thefollowing conditions must be observed:

• A double-wave (a turbulent wave with high upwardpressure followed by a smooth laminar wave)soldering technique should be used.

• The footprint must be at an angle of 45 ° to the boarddirection and must incorporate solder thievesdownstream and at the side corners.

During placement and before soldering, the package mustbe fixed with a droplet of adhesive. The adhesive can beapplied by screen printing, pin transfer or syringedispensing. The package can be soldered after theadhesive is cured.

Maximum permissible solder temperature is 260 °C, andmaximum duration of package immersion in solder is10 seconds, if cooled to less than 150 °C within6 seconds. Typical dwell time is 4 seconds at 250 °C.

A mildly-activated flux will eliminate the need for removalof corrosive residues in most applications.

15.4 Repairing soldered joints

Fix the component by first soldering two diagonally-opposite end leads. Use only a low voltage soldering iron(less than 24 V) applied to the flat part of the lead. Contacttime must be limited to 10 seconds at up to 300 °C. Whenusing a dedicated tool, all other leads can be soldered inone operation within 2 to 5 seconds between270 and 320 °C.

1998 Jul 06 55



SAA7377

16 DEFINITIONS

17 LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of theseproducts can reasonably be expected to result in personal injury. Philips customers using or selling these products foruse in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from suchimproper use or sale.

18 PURCHASE OF PHILIPS I2C COMPONENTS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.

Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.

Product specification This data sheet contains final product specifications.

Short-form specification The data in this specification is extracted from a full data sheet with the same typenumber and title. For detailed information see the relevant data sheet or data handbook.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one ormore of the limiting values may cause permanent damage to the device. These are stress ratings only and operationof the device at these or at any other conditions above those given in the Characteristics sections of the specificationis not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use thecomponents in the I2C system provided the system conforms to the I2C specification defined byPhilips. This specification can be ordered using the code 9398 393 40011.

Internet: http://www.semiconductors.philips.com

Philips Semiconductors – a worldwide company

© Philips Electronics N.V. 1998 SCA60

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changedwithout notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any licenseunder patent- or other industrial or intellectual property rights.

Middle East: see Italy

Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,Tel. +31 40 27 82785, Fax. +31 40 27 88399

New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,Tel. +64 9 849 4160, Fax. +64 9 849 7811

Norway: Box 1, Manglerud 0612, OSLO,Tel. +47 22 74 8000, Fax. +47 22 74 8341

Pakistan: see Singapore

Philippines: Philips Semiconductors Philippines Inc.,106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474

Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA,Tel. +48 22 612 2831, Fax. +48 22 612 2327

Portugal: see Spain

Romania: see Italy

Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,Tel. +7 095 755 6918, Fax. +7 095 755 6919

Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762,Tel. +65 350 2538, Fax. +65 251 6500

Slovakia: see Austria

Slovenia: see Italy

South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000,Tel. +27 11 470 5911, Fax. +27 11 470 5494

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Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,Tel. +46 8 5985 2000, Fax. +46 8 5985 2745

Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,Tel. +41 1 488 2741 Fax. +41 1 488 3263

Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1,TAIPEI, Taiwan Tel. +886 2 2134 2865, Fax. +886 2 2134 2874

Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,Tel. +66 2 745 4090, Fax. +66 2 398 0793

Turkey: Talatpasa Cad. No. 5, 80640 GÜLTEPE/ISTANBUL,Tel. +90 212 279 2770, Fax. +90 212 282 6707

Ukraine : PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461

United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421

United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,Tel. +1 800 234 7381

Uruguay: see South America

Vietnam: see Singapore

Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,Tel. +381 11 625 344, Fax.+381 11 635 777

For all other countries apply to: Philips Semiconductors,International Marketing & Sales Communications, Building BE-p, P.O. Box 218,5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825

Argentina: see South America

Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113,Tel. +61 2 9805 4455, Fax. +61 2 9805 4466

Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 160 1010,Fax. +43 160 101 1210

Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6,220050 MINSK, Tel. +375 172 200 733, Fax. +375 172 200 773

Belgium: see The Netherlands

Brazil: see South America

Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,51 James Bourchier Blvd., 1407 SOFIA,Tel. +359 2 689 211, Fax. +359 2 689 102

Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,Tel. +1 800 234 7381

China/Hong Kong: 501 Hong Kong Industrial Technology Centre,72 Tat Chee Avenue, Kowloon Tong, HONG KONG,Tel. +852 2319 7888, Fax. +852 2319 7700

Colombia: see South America

Czech Republic: see Austria

Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S,Tel. +45 32 88 2636, Fax. +45 31 57 0044

Finland: Sinikalliontie 3, FIN-02630 ESPOO,Tel. +358 9 615800, Fax. +358 9 61580920

France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex,Tel. +33 1 40 99 6161, Fax. +33 1 40 99 6427

Germany: Hammerbrookstraße 69, D-20097 HAMBURG,Tel. +49 40 23 53 60, Fax. +49 40 23 536 300

Greece: No. 15, 25th March Street, GR 17778 TAVROS/ATHENS,Tel. +30 1 4894 339/239, Fax. +30 1 4814 240

Hungary: see Austria

India: Philips INDIA Ltd, Band Box Building, 2nd floor,254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025,Tel. +91 22 493 8541, Fax. +91 22 493 0966

Indonesia: PT Philips Development Corporation, Semiconductors Division,Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510,Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080

Ireland: Newstead, Clonskeagh, DUBLIN 14,Tel. +353 1 7640 000, Fax. +353 1 7640 200

Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053,TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007

Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3,20124 MILANO, Tel. +39 2 6752 2531, Fax. +39 2 6752 2557

Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku,TOKYO 108-8507, Tel. +81 3 3740 5130, Fax. +81 3 3740 5077

Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,Tel. +82 2 709 1412, Fax. +82 2 709 1415

Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,Tel. +60 3 750 5214, Fax. +60 3 757 4880

Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,Tel. +9-5 800 234 7381

Printed in The Netherlands 545102/00/01/pp56 Date of release: 1998 Jul 06 Document order number: 9397 750 04003