Digital logic.pdf

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ICS 2205 DIGITAL LOGIC

Digital electronics: A field of science which deals with discrete quantities which are

either 0 or 1.

Analogue electronics: Deals with continuously varying quantities with respect to

time.

Features of Analogue Electronics:

0 Ӆ 2Ӆ 3Ӆ 4Ӆ

i. Varies continuously with time i.e. amplitude

ii. Mostly typical of nature e.g. speech, light energy

iii. Has been used for over 100 years

iv. It is wavy in nature

Features of Digital Electronics:

0

0 1 0 1 0 1

time

i. They are discrete i.e. they occur in 0’s and 1’s

ii. Typical of technology

iii. Has been used for around 50 years; when transistors came into existence

Advantages of Digital over Analogue:

i. Easier to process information/signal i.e. ease of manipulation

ii. Use of very large scale integration integrated circuits

iii. Take up small space as they are very small in size

iv. They are programmable i.e. Programmable Logic Devices (PLD’s) like

PROM

v. Not costly compared to analogue

vi. Durable

vii. More accurate

viii. Portable

ix. More secure

x. Not mechanical

xi. Not affected by noise


Applications of Digital Electronics:

i. Communication and entertainment

ii. Medicine

iii. Industrial applications

iv. Instrumentation

v. Defense

vi. Robotics

vii. Astronomy

viii. Biometrics

Disadvantages of Digital Electronics:

i. Require skills to operate

ii. Initial cost of design is high

iii. Can pose as a health hazard in some cases

Analogue

Filter

ADC DAC

Port filter

Analogue


NUMBER SYSTEMS: This is the process of counting using unique symbols.

TYPES OF NUMBER SYSTEMS AND THEIR CHARACTERISTICS

1. Decimal Number System

It has 10 unique symbols which range from 0 – 9

It is to base 10 (Radix 10)

Position value of a given digit is important e.g. 555

5 5 5

Hundredths Tens Ones

5 x 102 5 x 10

1 5 x 10

0

Decimal weights are in such a way that;

From the decimal to the left we start with 100

and decimal point to the right is started with 10-1

Counting is started from

1st No, 2

nd No, …….. 10

th No 2

nd 1

st 2

nd 10

th 3

rd 10

th

0 1 9 1 0 1 9 1 9

Maximum

10th

10th

2nd

1st 1

st

9 9 1 0 0

2. Binary Number System

It has 2 unique symbols i.e. 0 and 1

Its usually to base 2 (Radix 2)

Position value of a given digit is important e.g. 111

1 1 1

1 x 22 1 x 2

1 1 x 2

0


From the binary points to the left 20

and binary points to the right 2-1

e.g. 101.1101

Counting

1st No ……. 2

nd No 2

nd 1

st…… 2

nd 2

nd 2

nd 1

st 1

st

0 1 1 0 1 1 1 1 1

Maximum

2nd

2nd

2nd

2nd

1st 1

st 1

st 2

nd 2

nd 2

nd 2

nd

1 1 1 1 0 0 0 1 1 1 1

1 0 1. 1 1 0 1

20

2-1


3. Octal Number System

Has 8 unique symbols

Its usually to base 8

Position value of digit is important


o From octal point to the left 80

o Octal point to the right 8-1

e.g. 66.45

Counting

1st No ……. 8

th No 2

nd 1

st…… 2

nd 8

th 3

rd 1

st…. 3

rd 8

th

0 7 1 0 1 7 2 0 2 7

Maximum

8th

8th

2nd

1st 1

st

7 7 1 0 0

4. Hexadecimal Number System

Has 16 unique symbols i.e. 0 – 9 , A – F

Base 16 (Radix 16)

position value of digit is important e.g. 777

7 7 7

7 x 162 7 x 16

1 7 x 16

0


From hexadecimal to the left 160

Hexadecimal to the right 16-1

e.g. 689.A73

Counting

1st No ……. 16

th No 2

nd 1

st…… 2

nd 16

th

0 15 1 0 1 F

Maximum

16th

16th

2nd

1st 1

st

F F 1 0 0

6 6. 4 5

80

8-1

6 8 9. A 7 3

160

16-1


INTERCONVERSIONS

1. Decimal to Binary / Integer Values

a) Weights Method

Procedure

i. Take the binary weights up to slightly more than the number given.

ii. Divide the decimal weight by the number given then indicate how many times

either 0 or 1 and take the remainder to the next weight.

iii. Continue till the remainder is 0

Example 1

Convert 139 to binary

139 139 11 11 11 11 3 3 1

256 128 64 32 16 8 4 2 1

0 1 0 0 0 1 0 1 1

13910 = 100010112

Example 2


156 156 28 28 28 12 4 0 0

256 128 64 32 16 8 4 2 1

0 1 0 0 1 1 1 0 0

15610 = 100111002

b) Divide by 2 Method

Procedure

i. Take the number, divide by 2 and indicate the remainders

ii. The remainders are read from down-up

Example 1


13910 = 100010112

2 139 Remainders

2 69 1

2 34 1

2 14 0

2 8 1

2 4 0

2 2 0

2 1 0

2 0 1


Decimal Pointed Values / Fractional Values

Procedure

i. Multiply the number by 2

ii. Take the integer value as the binary equivalent (carry)

iii. For the pointed value continue multiplying by 2 till the fractional value is 0

iv. The integer values are written up-down to give the result

Example 1

Convert 0.625 to binary

0.62510 = 0.1012

NB: 0.625 x 2 = 1.25

Where 1 = Integer Value (Carry)

And 0.25 = Pointed Value

Example 2

Convert 0.728 to binary

0.72810 ~ 0.101112

Binary to Decimal

Integer Values

Procedure

i. Indicate the weights to the corresponding binary digits

ii. Cross out the weights that have zero above them

iii. Sum up the weights that have 1’s above them

Example 10010112

1 0 0 1 0 1 1

64 32 16 8 4 2 1

64 + 8 + 2 + 1 = 75

10010112 = 7510

2 0.625 Carry

2 0.25 1

2 0.5 0

2 0.0 1

2 0.728 Carry

2 0.456 1

2 0.912 0

2 0.824 1

2 0.648 1

2 0.296 1

2 0.592 0



Procedure

i. Indicate the weights to the corresponding binary digits

ii. Cross out the weights that have zero above them

iii. Sum up the weights that have 1’s above them

Example: Convert 0.11012 to Decimal

NB:

Decimal to Octal / Integer Values

Weights Method

Procedure

i. Take the binary weights up to slightly more than the number given.

ii. Divide the decimal weight by the number given then indicate how many times

either 0 or 1 and take the remainder to the next weight.

iii. Continue till the remainder is 0

Example 3010 to Octal

0 0 0 0 0

1 0 0 0 1

2 0 0 1 0

3 0 0 1 1

4 0 1 0 0

5 0 1 0 1

6 0 1 1 0

7 0 1 1 1

8 1 0 0 0

9 1 0 0 1

A 10 1 0 1 0

B 11 1 0 1 1

C 12 1 1 0 0

D 13 1 1 0 1

E 14 1 1 1 0

F 15 1 1 1 1


Divide by 8 Method

Procedure

i. Take the number, divide by 8 and indicate the remainders

ii. The remainders are read from down-up

Example: Convert 3010 to Octal

3010 = 368


Procedure

i. Multiply the number by 8

ii. Take the integer value as the binary equivalent (carry)

iii. For the pointed value continue multiplying by 8 till the fractional value is 0

iv. The integer values are written up-down to give the result

Example

Convert 0.3610 to Octal

0.3610 ~ 0.270248

Octal to Decimal

Weights Method

Example: Convert 7748 to Decimal

7 7 4

82 8

1 8

0

7 x 82 + 7 x 8

1 + 4 x 8

0 = 448 + 56 + 4

7748 = 50810

8 30 Remainder

8 3 6

8 0 3

8 0.36 Carry

8 0.88 2

8 0.04 7

8 0.32 0

2 0.56 2

2 0.48 4



Example: Convert 0.0328 to Decimal

0. 0 3 2

8-1

8-2

8-3

3 x 8-2

+ 2 x 8-3

0.0328 = 0.05110

Binary to Octal

Procedure

i. Group the binary digits into groups of 3

ii. Then convert to decimal

iii. Conversion is done integer from point to left whereas for fraction from point

to right

Example: Convert 1110110.1011 to Octal

0 0 1 1 1 0 1 1 0. 1 0 1 1 0 0

1 6 6. 5 4

1110110.1011 = 166.548

Octal to Binary

Procedure

Convert the number to groups of 3 bits

Example: Convert 2107.318 to Binary

2 1 0 7. 3 1

010 001 000 111. 011 001

2107.318 = 010001000111.0110012


Hexadecimal to Decimal

Procedure

i. Put the weights under their respective position value

ii. Cancel the ones under 0 and multiply the rest with their respective numbers

iii. Sum them up after getting the product

Example: Convert 38.9F to Decimal

3 8. 9 F

161 16

0 16

-1 16

-2

3 x 161

+

8 x 160

+ 9 x 16-1

+

15 x 16-2

48 + 8. + 0.5625 + 0.05859

38.9F = 56.06210910

Decimal to Hexadecimal

Example 89.2510

89.2510 = 5916

Fractional to Hexadecimal

Example 0.25

0.25 = 0.416

Hexadecimal to Binary

Procedure

i. Convert each hexadecimal digit to a group of 4 bits

ii. Then combine them to give a string of bits (binary)

Example: Convert 48.26B16 to Binary

Hexadecimal Binary

4 0100

8 1000

2 0010

6 0110

B 1011

48.26B16 = 01001000.0010011010112

16 89 Remainder

16 5 9

0 5

16 0.25 Carry

0 4


Binary to Hexadecimal

Procedure

i. Group the bits to groups of 4 bits

ii. Convert them to decimal equivalent and combine the digits left

iii. Grouping of integers starts from the binary point to the left whereas fractional

starts from the binary point to the right

iv. Add insignificant bits either to the leftmost

Example: Convert 110110.0101012

0 0 1 1 0 1 1 0. 0 1 0 1 0 1 0 0

3 6. 5 4

110110.0101012 = 36.5416

Hexadecimal to Octal

Procedure

i. First convert the hexadecimal number to binary

ii. Group the bits in groups of 3 to convert them into Octal

Example: Convert 65D.AC316 to Octal

0 1 1 0 0 1 0 1 1 1 0 1. 1 0 1 0 1 1 0 0 0 0 1 1

3 1 3 5. 5 3 0 3

65D.AC316 = 3135.53038

Octal to Hexadecimal

Procedure

i. Convert the Octal number to binary

ii. Thereafter convert it to hexadecimal

Example: Convert 763.548 to Hexadecimal

1 1 1 1 1 0 0 1 1. 1 0 1 1 0 0

1 F 3. B

763.548= 1F3.B16


BINARY OPERATIONS

1) Addition

2) Subtraction

3) Multiplication

4) Division

1. Addition

Binary Addition

It involves adding two binary numbers

Example: adding a single bit

A B Addition

0 0 0

0 1 1

1 0 1

1 1 0 Carry 1 = 1 0

Example: adding a string of bits

A = 1 0 1 1 1 0 1 . 1 1 0 1 +

B = 1 1 1 0 0 1 1 . 0 1 1 1

1 0 1 0 0 0 1 . 0 1 0 0

2. Binary Subtraction

Methods of Subtraction

i) Direct Subtraction

ii) Subtraction using 1’s compliments

iii) Subtraction using 2’s compliments

iv)

Example: subtracting a single bit

A B Addition

0 0 0

0 1 1 Borrow 1

1 0 1

1 1 0

Direct Subtraction

Example 1: subtracting a string of bits

A = 1 1 0 0 1 . 1 0 1 -

B = 1 0 1 1 1 . 1 1 1

0 0 0 0 1 . 1 1 0


Example 1: subtracting a string of bits

A = 1 0 0 0 0 -

B = 1 1 1 1

0 0 0 0 1

Subtraction using compliments

1’s Compliment

Procedure

i. Invert the binary number i.e. invert all the bits individually

ii. Where there is 1 change it to 0 and vice versa

1’s Compliment

Example: 1 0 1 1 02 0 1 0 0 1

2’s Compliment

Procedure

i. First obtain 1’s compliment

ii. Add a 1 to the Least Significant Bit

Example: 1 0 1 1 0 0 1 0 0 1 0 0 1 1 0 1 1’s Compliment

+ 1

1 0 0 1 1 1 0 2’s Compliment

Procedure

i. Take the binary and check for the first 1 from the LSB

ii. Arrange the binary bits the way they appear including the first bit

iii. Compliment the rest

Example 1: 1 0 1 1 0 0 1 0

0 1 0 0 1 1 1 0 2’s Compliment

Example 2: 1 0 0 1 0 0 0 0

0 1 1 0 0 0 0 0 2’s Compliment


Subtraction using 1’s Compliment

Procedure

i. Compliment the subtraend and add it to the minuend

ii. If there is a carry take it round and add it to the LSB

iii. The result will be correct and positive

iv. If there is no carry the result is not correct and will be negative

v. Re-compliment and attach a negative

Example 1:

A = 1 0 1 1 0 1 -

B = 1 0 0 0 1 1

0 0 1 0 1 0

1’s compliment for B = 0 1 1 1 0 0

A = 1 0 1 1 0 1 +

B’ = 0 1 1 1 0 0

1 0 0 1 0 0 1 + Result is a POSITIVE so add it

1

0 0 1 0 1 0

Example 2:

B = 1 0 0 0 1 1 -

A = 1 0 1 1 0 1

0 0 1 0 1 0

1’s compliment for A = 0 1 0 0 1 0

A’ = 0 1 0 0 1 0 +

B = 1 0 0 0 1 1

0 1 1 0 1 1 1 + Result is a NEGATIVE so re-compliment

0 0 1 0 0 0

Subtraction using 2’s Compliment

Procedure

i. Obtain the 2’s compliment of the subtraend

ii. Add it to the minuend

iii. If there is a carry discard it; the result is correct and positive

iv. If there is no carry; the result is negative and incorrect

v. Re-compliment it (using 2’s compliment) and attaché a negative

Example 1:

A = 1 0 1 1 0 1

B = 1 0 0 0 1 1

B’ + 1 = 1 1 1 1 0 1 +

A = 1 0 1 1 0 1

1 0 0 1 0 1 0 Discard the carry 1


Example 2:

B = 1 0 0 0 1 1

A = 1 0 1 1 0 1

A’ + 1 = 0 1 0 0 1 1 +

B = 1 0 0 0 1 1

0 1 1 0 1 1 0 Result is a NEGATIVE so re-compliment

0 0 1 0 0 1

Multiplication

Example 1: Multiplying a single bit

A B Result

0 0 0

0 1 0

1 0 0

1 1 1

Example 2: Multiplying a string of bits

A 1 1 0 1. 1 0 1

B 1 0 1 1. 1 1

1 0 1 1 0 1

1 0 1 1 0 1

1 0 1 1 0 1

0 0 0 0 0 0

1 0 1 1 0 1

1 0 1 0 0 0 0 0. 0 0 0 1 1

Division

Whole numbers/integers

Example 1:

Dividend 20 1 0 1 0 0

Divisor 5 1 0 1

100

101√10100

101

000

Done by subtracting the divisor from the dividend and shifting it to the left until the

remainder is 0


Number with binary points

Example 2:

Dividend 1 1 1 . 1 0 1

Divisor 0 .1 1

Procedure

i. First remove the point from both the dividend and divisor by multiplying them

to make them whole numbers (integers).

Dividend 1 1 1 . 1 0 1 x 1000 = 111101

Divisor 0 .1 1 x 1000 110

1010.00101

110√111101

110

110

110

01000

110

1000

11 1.101 ≈ 1010.00101

0.11

Example 3:

Dividend 1 1 1 . 1 1 x 100 = 11111

Divisor 0 .1 x 100 10

1111.1

10√11111

10

11

10

11

10

11

10

10

10

11 1.11 ≈ 1111.1

0.1


BINARY CODES

This is a way of representing symbols using binary numbers

Binary code is given by: -

i. Straight Binary Code

ii. Binary Coded Decimal (BCD)

iii. Excess-3

iv. Gray Code

v. ASCII Code

1. Straight Binary Code

It uses the normal binary representation

A decimal number is converted to its binary equivalent

Example

1410 11102

Advantages of Straight Binary Code

Easier to deal with

Disadvantages of Straight Binary Code

Prone to more errors

2. Binary Coded Decimal (BCD)

Obtained by converting each individual decimal digit to its binary equivalent

in groups of 4-bits.

Combine the bits to obtain a string of bits

Only 0-9 can be converted to binary

10-15 are invalid cases for BCD

Also referred to as 8421 representation

NB:

Decimal BCD

0 0000

1 0001

2 0010

3 0011

4 0100

5 0101

6 0110

7 0111

8 1000

9 1001


Converting from Decimal to BCD

Procedure

i. Convert each individual decimal to binary in groups of 4 and combine them

Example: 45810

4 = 0100

5 = 0101

8 = 1000

45810 = 010001011000BCD

Converting from BCD to Decimal

Procedure

i. Group the given bits in groups of 4-bits

ii. Convert each group to its decimal equivalent

iii. Grouping should be done from Least Significant Bit (LSB) to Most Significant

Bit (MSB)

Example 1: 1 0 0 1 1 0 0 1 0 12

2 6 510

10011001012 = 26510

Example 2: 1 0 0 1 0 1 1 1 0 0 1 02

9 7 210

1001011100102 = 97210

3. Excess-3

Obtained by adding 3 to each decimal digit and converting to binary in groups

of 4-bits

Combine them to form a string of bits

Converting from Decimal to Excess-3

Procedure

i. Add 3 to each digit

ii. Convert to binary

iii. If after adding 3 to the digit you obtain a carry ( beyond 10) still convert the

whole number to binary e.g. 7 + 3, 8 + 3 etc


Example: Convert 27 to Excess-3

2 7

3 3

5 10 convert to binary = 0101 1010

2710 = 01011010Excess-3

Converting from Excess-3 to Decimal

Procedure

i. Group the bits in groups of 4 from the Least Significant Bit

ii. Convert each group to decimal equivalent

iii. Subtract 3 from each digit

iv. 0,1,2,13,14, and 15 are invalid values for Excess-3

Example: 0101 1100 1010

5 12 10

- 3 3 3

2 9 710

010111001010Excess-3 = 29710

4. Gray Code

This represents the numbers in a way that each consecutive number will differ

by 1 in binary form

Example: 1 bit

A

0

1

Example: 2 bits

A B

0 0

0 1

1 1

1 0


Example: 3 bits

Example: 4 bits

Converting from Binary to Gray Code

Procedure

i. Most Significant Bit (MSB) remains the same

ii. 2nd

bit is obtained by adding the MSB bit and the 2nd

bit of binary then discard

the carry

iii. 3rd

bit is obtained by adding 2nd

bit to 3rd

bit of binary also discard the carry

iv. Continue until all the bits are considered

Example: Convert 10112 to Gray Code

10112 = 1110gray code

A B C

0 0 0

0 0 1

0 1 1

0 1 0

1 1 0

1 1 1

1 0 1

1 0 0

A B C D

0 0 0 0

0 0 0 1

0 0 1 1

0 0 1 0

0 1 1 0

0 1 1 1

0 1 0 1

0 1 0 0

1 1 0 0

1 1 0 1

1 1 1 1

1 1 1 0

1 0 1 0

1 0 1 1

1 0 0 1

1 0 0 0


Converting from Gray Code to Binary

Procedure

i. Most Significant Bit (MSB) remains the same

ii. 2nd

bit is obtained by adding the MSB bit of the binary to the 2nd

bit of gray

code then discard the carry

iii. Continue until all the bits are considered

Example: Convert 1110gray code to Binary

1110gray code = 10112

Applications of Gray Code

i. Reduction of errors

ii. Karnaugh Map (K-Map)

5. ASCII CODE

This is an alpha-numeric code

Represents decimal digits and alphabets in binary and other symbols

It’s the standard used in the keyboard

Contains a 7-bit representation

NB:

MSB

LSB 000 001 010 011 100 101 110 111

0000 0 P p

0001 1 A Q a q

0010 2 B R b r

0011 3 C S c s

0100 4 D T d t

0101 5 E U e u

0110 6 F V f v

0111 7 G W g w

1000 8 H X h x

1001 9 I Y i y

1010 J Z j z

1011 K k

1100 L l

1101 M m

1110 N n

1111 O o

Values are read from MSB to LSB

Example: Letter A = 100 0001

Letter J = 100 1010

Arsenal = 1000001 1110010 1110011 1100101 1101110 1100001 1101100


LOGIC GATES

Definition Logic: A way of reasoning to make a decision

In electronics logic stands for a way of representing convention using binary

Types of Logic Conventions:

i. Positive Logic Convention

ii. Negative Logic Convention

1. Positive Logic Convention

0 1

Off On

No Yes

Negative Positive

False True

Low High

Absence Presence

2. Negative Logic Convention

1 0

Gate: A device which makes logic decisions

It gives output depending on the different inputs

Its constructed by using diodes, switches and transistors

It’s the basic building blocks for all digital systems

Truth table

Has inputs and outputs

The output usually depends on different combinations of input

They are used to analyze different gates

Example 1: 1 input and 1 output

Input Output

A F

0 1

1 0

F = A’

Example 2: 2 inputs and 1 output

Inputs Output

A B F

0 0 0

0 1 1

1 0 1

1 1 1

F = A + B


Example 3: 3 inputs and 1 output

Inputs Output

A B C F

0 0 0 0

0 0 1 1

0 1 0 1

0 1 1 1

1 0 0 1

1 0 1 1

1 1 0 1

1 1 1 1

F = A + B + C

BOOLEAN EXPRESSION

This is an equation which represents an output for different inputs

It contains output variables and input variables using the alphabet

It is used to analyze logic gates

It can be obtained from the truth tables

Examples

F = A’

F = A + B

F = AB + CD

TYPES OF GATES

i. Inverter – NOT

ii. OR

iii. AND Basic Gates

iv. XOR

v. XNOR

vi. NOR Universal Gates

vii. NAND

i) Inverter – NOT gate

It is a device that compliments an input

Symbol:

Input (A) Output (F)

Features:

It has a bubble as an output

Has 1-input and 1-output

It inverts an input


Construction using diode

I/P

5V

D

0.6V

4.4V

R

O/Pov

I/P

5V 0.6V

R

O/P

Construction using transistors

RO

B

E

0V

I/P 5V high

Ov low

5v

RC 5v high

2v lowO/PC

SWITCHES

BA

off

Truth table

Input Output

A F

0 1

1 0

ii) OR Gate

A gate which gives an output of 0 only when all inputs are 0


Symbol:

Features:

It has 2 or more inputs

Has 1-output

Construction using diodes

A

B

F

5 v

D 1

D 2

0 v

5 v

5 v

I/PA

I /P B

5 v - h ig h

0 v

0 v

5 v lo w

INPUTS OUTPUT

A B VO

Low Low Low

Low High High

High Low High

High High High

Construction using switches

SA

BulbVS SB

INPUTS OUTPUT

SA SB Bulb

Off Off OFF

Off On ON

On Off ON

On On ON


Truth table

Boolean expression:

F = A + B

iii) AND Gate

A gate which gives a high only when both inputs are high

Symbol:

A

B

F

Features:


Has 1-output

Gives an output of 1 when both inputs are 1

Behaves like a multiplexer


VA

VB

o/p

R

D1

D2

sv

low

low

INPUTS OUTPUT

A B VO

Low Low Low

Low High Low

High Low Low

High High High

Inputs Output

A B F

0 0 0

0 1 1

1 0 1

1 1 1



SA SB

VS

bulb

INPUTS OUTPUT

SA SB Bulb

Open Open OFF

Open Closed OFF

Closed Open OFF

Closed Closed ON

Truth table

Boolean expression:

F = A B

iv) XOR Gate

A gate which gives a high only when either of the inputs is high

Symbol:

A

B

F

Features:


Gives out only 1-output

Gives an output of 1 when either inputs are 1

Inputs Output

A B F

0 0 0

0 1 0

1 0 0

1 1 1



Out put

R

D1

D2

I/P

5v

INPUTS OUTPUT

A B VO

Low Low Low

Low High High

High Low High

High High High


Bulb

SA

SB

VS

INPUTS OUTPUT

SA SB Bulb

Off Off OFF

Off On ON

On Off ON

On On OFF

Truth table

Inputs Output

A B F

0 0 0

0 1 1

1 0 1

1 1 0


Boolean expression:

F = A B

F = A’B + AB’

v) XNOR Gate

A gate which gives an output of 1 only when both inputs are the same

Symbol:

F

A

B

Features:



Gives an output of 1 when either inputs are 0 or 1


VS

SA

SB

Bulb

Selenoid

INPUTS OUTPUT

SA SB Bulb

Off Off ON

Off On OFF

On Off OFF

On On ON


Truth table

Boolean expression:

F = A . B

F = AB + A’B’

vi) NOR Gate

A gate which gives an output of 1 only when all inputs are 0

Symbol:

A

B

F

Features:



Gives an output of 1 when all inputs are 0


VS

SA

SB

Bulb

Selenoid

INPUTS OUTPUT

SA SB Bulb

Off Off ON

Inputs Output

A B F

0 0 1

0 1 0

1 0 0

1 1 1


Off On OFF

On Off OFF

On On OFF

Demorgan’s Theorem

Procedure:

i. Remove the overbar

ii. Change the OR gate to an AND gate or vice versa

iii. Compliment individual variables/literals

Hence F = A + B

Will be same as F = A.B

Equivalent to a Bubbled AND Gate

Truth table

Boolean expression:

F = A + B

vii) NAND Gate

A gate which gives low output only when all inputs are high

Symbol:

Inputs Output

A B F

0 0 1

0 1 0

1 0 0

1 1 1


A

B

F

Features:


It has a bubble


Gives an low output only when all inputs are high


VS

SA

SB

Bulb

Selenoid

INPUTS OUTPUT

SA SB Bulb

Off Off ON

Off On ON

On Off ON

On On OFF

Demorgan’s Theorem

F = A + B

Equivalent to a Bubbled OR Gate

A

BF


Truth table

Boolean expression:

F = A B

NB:

NOR & NAND GATES

These are universal gates

Hence they can be used to implement all the other gates

Exercise

1.

a) Implement all the other gates using the NOR Gate

b) Implement all the other gates using the NAND Gate

c) Implement the following using NOR gates and NAND gates

F = AB + BC + CD

F = ABC + ABC

2. Design a logic diagram for the following Boolean expression

F = ACD + BC + AC

F = ABC + AB + BD

3. Obtain expression for the following logic diagram

A B C

Inputs Output

A B F

0 0 1

0 1 1

1 0 1

1 1 0


BOOLEAN ALGEBRA

Invented by Boole George

Expression which are used to analyze digital circuits

Used to minimize the number of logic gates used to implement a circuit

LAWS OF BOOLEAN ALGEBRA

OR LAWS

A + 0 = A

A + 1 = 1

A + A = A

A + A = 1

AND LAWS

A.0 = 0

A.1 = A

A.A = A

A. A = 0

COMPLEMENTING LAWS

0 = 1

1 = 0

A = 0 A = 1

A = 1 A = 0

COMMUTATIVE LAWS

A + B = B + A

AB = BA

ASSOCIATIVE LAWS

(A+B) + C = A + (B+C)

A(BC) = (AB)C

DISTRIBUTIVE LAWS

(A+B) (A+C) = A + BC

A + AB = A+B

A +AB = A +B

ABSORPTIVE LAWS

A(A+B) = A

A + AB = A

A(A +B) = AB


Prove of Distributive Laws

1. (A+B) (A+C) = A + BC

= AA + AB + AC + BC

= A + AB + AC + BC

= A (1 + B) + AC + BC

= A + AC + BC

= A (1+C) + BC

= A + BC

2. A + AB = A + B

= A.1 + AB

= A (1 + B) + AB

= A + AB + AB

= A+ B (A + A)

= A + B

3. A + AB

= A.1 + AB

= A (1+B) + AC + BC

= A + AB + AB

= A + B (A + A)

= A + B

Using Boolean algebra, simplify the following expressions and implement them using

the minimum number of gates

i) F = AB + AC + ABC

ii) F = ABC + ABC + ABC + ABC +ABC

iii) F= (x+ y) x (y+z) + xy + xz

Proof the following using Boolean algebra

i) F = AB + A + AB = 0

ii) F = AB + AC + ABC (AB+C) = 1


STANDARD FORM OF BOOLEAN EXPRESSION

They are of two types namely:

i. Sum of Products (SOP)

ii. Product of Sum (POS)

1. Sum of Products (SOP)

A combination of literals in multiplication form e.g. ABC, AB, ABCD

Literals in every product appear in compliment or non compliment form

No single bar can cover more than one literal e.g. ABC

Every product will give 1-output for only 1-input combination, the rest will

result to 0

Thus this product is called a Min-term

A product domain represents all the literals/variables at the input

Example

F(A,B,C) = ABC + ABC is a domain of 3 variables A, B & C

SOP is a combination of several products OR’ed together

Example

F(A,B,C) =AB + AC + C

2. Product of Sum (POS)

A combination of literals in summation/addition form e.g. (A+B) (A+C)

Literals in every sum appear in complimented or non complimented form

No single bar can cover more than 1 literal

Every sum will give a 0-output for only 1-input combination; the rest will give

or result to 1

Thus the sum is called a Max-term

A sum domain represents all the literals/variables at the output

Example

F(A,B,C) = (A+B+C)(A+B+C)

POS is a combination of several sums AND’ed together

Standard/Canonical for SOP

Referred to as the Standard Sum of Products (SSOP)

All the literals in the domain must appear in every product

Example:

F(A,B) = AB + AB

F(A,B,C) = ABC + ABC

This form is important in developing the truth table or K-Map for simplification

purposes.


Conversion from SOP to SSOP

Procedure

i. Identify the SOP domain

ii. Identify the missing literal in each product

iii. AND or multiply the literal summed with its compliment and expand

E.g. AB(C+C)

iv. Continue till all the literals appear in each product

v. Eliminate the repeated products

vi. Represented using ∑m

Example:

F(A,B,C) = A + BC + BC

= A(B+B) + (A+A)BC + (A+A)BC

= AB + AB + ABC + ABC + ABC + ABC

= AB(C+C) + AB(C+C) + ABC + ABC + ABC + ABC

= ABC + ABC + ABC + ABC + ABC + ABC + ABC + ABC

= ABC + ABC + ABC + ABC + ABC + ABC

Standard/Canonical for POS

Referred to as the Standard Product of Sums (SPOS)

All the literals in the domain must appear in every sum

E.g. F(A,B) = (A+B)(A+B)

Represented by Πm

Conversion from POS to SPOS

Procedure

i. Identify the POS domain

ii. Identify the missing literal in each term

iii. OR or add the literal multiplied with its compliment and expand

E.g. F(A+B) = (A+B+CC)

iv. Continue till all the literals appear in each term or sum

v. Eliminate the repeated sums


Example:

F(A,B,C) = A(B+C)

= (A+BB) (AA+B+C)

= (A+B) (A+B) (A+B+C) (A+B+C)

= (A+B+CC) (A+B+CC) (A+B+C) (A+B+C)

= (A+B+C) (A+B+C) (A+B+C) (A+B+C) (A+B+C) (A+B+C)

= (A+B+C) (A+B+C) (A+B+C) (A+B+C) (A+B+C)

TRANSFERRING STANDARD FORM OF EXPRESSION TO A TRUTH

TABLE

1. Standard Sum of Product

Procedure

i. Identify the SSOP domain

ii. 2 to the power of the number of literals in the expression will give the number

of combination in the truth table

E.g. 2 literals 22 =4

3 literals 23 = 8

4 literals 24 = 16

iii. Change the literals to their binary equivalent by using the following

A barred literal = 0

A non-barred literal = 1

iv. At the output of each combination obtained indicate a 1

Example:

Transfer the following to a truth table

F(A,B,C) = ABC + ABC + ABC + ABC + ABC

Convert to binary 111 101 011 100 000


Truth table

A B C F

0 0 0 0 1

1 0 0 1

2 0 1 0

3 0 1 1 1

4 1 0 0 1

5 1 0 1 1

6 1 1 0

7 1 1 1 1

F(A,B,C) = ∑m (0,3,4,5,7)

2 Standard Product of Sum

Procedure

i. Identify the SPOS domain

ii. 2 to the power of the number of literals in the expression will give the number

of combination in the truth table

E.g. 2 literals 22 =4

3 literals 23 = 8

4 literals 24 = 16

iii. Change the literals to their binary equivalent by using the following

A barred literal = 1

A non-barred literal = 0

iv. At the output of each combination obtained indicate a 0

Example:

Transfer the following to a truth table

F(A,B,C) = (A+B+C) (A+B+C) (A+B+C)

Convert to binary 000 010 101

Truth table

A B C F

0 0 0 0 0

1 0 0 1

2 0 1 0 0

3 0 1 1

4 1 0 0

5 1 0 1 0

6 1 1 0

7 1 1 1

F(A,B,C) = Πm (0,2,5)


Changing from a truth table to SSOP and SPOS

Wherever there is an output of 1 the combination will give a product and 0

will give a sum

Combine the combinations of 1’s using addition to from SSOP

Combine the combinations of 0’s using addition to from SPOS

Example

Convert the following to SSOP and SPOS using the table below

Truth table

A B C D F

0 0 0 0 0 0

1 0 0 0 1 1

2 0 0 1 0 1

3 0 0 1 1 0

4 0 1 0 0 0

5 0 1 0 1 0

6 0 1 1 0 0

7 0 1 1 1 1

8 1 0 0 0 1

9 1 0 0 1 1

10 1 0 1 0 1

11 1 0 1 1 0

12 1 1 0 0 1

13 1 1 0 1 0

14 1 1 1 0 1

15 1 1 1 1 1

SSOP

F = (A,B,C,D)

= ∑m(1,2,7,8,9,10,12,14,15)

= (ABCD) + (ABCD) + (ABCD) + (ABCD) + (ABCD) + (ABCD) + (ABCD)

0001 0010 0111 1000 1001 1010 1100

(ABCD) + (ABCD)

1110 1111

SPOS

F = (A,B,C,D)

= Πm(0,3,4,5,6,11,13)

= (A+B+C+D) (A+B+C+D) (A+B+C+D) (A+B+C+D) (A+B+C+D)

0000 0011 0100 0101 0110

(A+B+C+D) (A+B+C+D)

1011 1101


INTERCONVERSIONS

From SSOP to SPOS

i. Obtain truth table equivalent for SSOP combinations

ii. The remaining are automatically 0’s which can be obtained as SPOS

From SPOS to SSOP

i. Obtain truth table equivalent for SPOS combinations

ii. The remaining are automatically 1’s which can be obtained as SSOP

Exercise

1. Using the following equations:

i) Obtain SSOP

ii) Convert to SPOS using a truth table

F(A,B,C,D) = AB + CD +BC

F(A,B,C,D) = BCD + A + CD

2. Using the following expressions:

i) Obtain SPOS

ii) Convert to SSOP using a truth table

F(A,B,C,D) = (B+C) (A+D)

F(A,B,C,D) = AB(C+D)

K-MAP SIMPLIFICATION

Karnaugh Map

It’s a representation which uses squares to represent SSOP or SPOS

The number of squares depends on the number of input variables

Example

2-input variables 22 squares



Generally the number of squares = 2 to power the number of input variables

The binary equivalent of the input variables is represented using the gray code

format to get the adjacent squares

The 1’s for SSOP are called Min-terms or Prime Implicants


SSOP Representation

Procedure

i. Identify the min-term

ii. Change the input variables to their binary equivalent

iii. In the table indicate a 1 to correspond with the binary equivalent of the min-

term

General Representation

1. 2-Variable K-Map

A A A

B 0 1

B 0

B 1

2. 3-Varible K-Map

AB

AB AB AB AB

C 00 01 11 10

C 0

C 1

3. 4-Variable K-Map

AB

AB AB AB AB

CD 00 01 11 10

CD 00

CD 01

CD 11

CD 10

0

AB 00

2

AB 10

1

AB 01

3

AB 11

0

ABC 000

2

ABC 010

4

ABC 100

6

ABC 110

1

ABC 001

3

ABC 011

5

ABC 101

7

ABC 111

0

ABCD 0000

4

ABCD 0100

12

ABCD 1100

8

ABCD 1000

1

ABCD 0001

5

ABCD 0101

13

ABCD 1101

9

ABCD 1001

3

ABCD 0011

7

ABCD 0111

15

ABCD 1111

11

ABCD 1011

2

ABCD 0010

6

ABCD 0110

14

ABCD 1110

10

ABCD 1010


Example:

Represent the following expression using K-Map

F(A,B,C) = ∑m(0,2,4,5,7)

AB AB AB AB AB

C 00 01 11 10

C 0

C 1

SPOS Representation

Procedure

i. Identify the max-term

ii. Change input variables to their binary equivalent

iii. In the table indicate a 0 to correspond with the square with the binary

equivalent of the max-term

1. 2-Variable K-Map

A

A A

B 0 1

B 0

B 1

2. 3-Varible K-Map

AB AB AB AB AB

C 00 01 11 10

C 0

C 1

0

1 2

1 4

1

7

1 5

1

0

A+B 00

2

A+B 10

1

A+B 01

3

A+B 11

0

A+B+C 000

2

A+B+C 010

4

A+B+C 100

6

A+B+C 110

1

A+B+C 001

3

A+B+C 011

5

A+B+C 101

7

A+B+C 111


3. 4-Variable K-Map

AB AB AB AB AB

CD 00 01 11 10

CD 00

CD 01

CD 11

CD 10

Example:

Represent the following expression using K-map

F(A,B,C,D) = Πm (1,2,3,5,7,8,12,14)

AB AB AB AB AB

CD 00 01 11 10

CD 00

CD 01

CD 11

CD 10

Simplification using K-map

SSOP

Procedure

i. Indicate 1’s in the corresponding min-term squares

ii. Group the 1’s in groups of 1, 2, 4, 8 and 16 taking the maximum combination

iii. The 1’s to be grouped are those which are adjacent to each other

iv. Obtain the minimum expression from the different groups (prime implicant)

Procedure for obtaining a minimized prime implicant

i. Take those variables which do not change in binary as you move from one

square to the other in the group

ii. The changing variables are omitted

iii. The final expression is obtained by summing the minimized products

0

A+B+C+D 0000

4

A+B+C+D 0100

12

A+B+C+D 1100

8

A+B+C+D 1000

1

A+B+C+D 0001

5

A+B+C+D 0101

13

A+B+C+D 1101

9

A+B+C+D 1001

3

A+B+C+D 0011

7

A+B+C+D 0111

15

A+B+C+D 1111

11

A+B+C+D 1011

2

A+B+C+D 0010

6

A+B+C+D 0110

14

A+B+C+D 1110

10

A+B+C+D 1010

12

0 8

0 1

0 5

0

3

0 7

0

2

0 14

0


Example

Obtain a minimized expression from the following Boolean expressions

i) F(A,B,C) = ∑m(1,3,4,6,7)

AB

AB AB AB AB

C 00 01 11 10

C 0

C 1

F(A,B,C) = AC + AB + AC

ii) F(A,B,C,D) = ∑m(1,2,3,4,5,6,7,8,9,11,12,13)

AB AB AB AB

CD 00 01 11 10

CD 00

CD 01

CD 11

CD 10

F(A,B,C,D) = AC + BD + BC + AC

Simplification using K-map

SPOS

Procedure

i. Indicate a 0 in the corresponding max-term squares

ii. Group the 0’s in groups of 1, 2, 4, 8 and 16 taking the maximum possible

combination

iii. The 0’s to be grouped are the ones which are adjacent to each other

iv. Obtain the minimum expression from the different groups (prime implicant)

Procedure for obtaining a minimized prime implicant

i. Take those variables which do not change in binary as you move from one

square to the other in the group

ii. The changing variables are omitted

iii. The final expression is obtained by summing the minimized products

6

1

4

1

1

1 3

1

7

1

1

1

1

1

1

1

1

1

1

1

1

1


Example:

Obtain a minimized expression from the following Boolean expressions

i) F(A,B,C) = Πm(2,3,5,6,7)

AB AB AB AB AB

C 00 01 11 10

C 0

C 1

F(A,B,C) = B(A + C)

ii) F(A,B,C,D) = Πm(4,6,8,9,11,12,14,15)

AB AB AB AB AB

CD 00 01 11 10

CD 00

CD 01

CD 11

CD 10

F(A,B,C,D) = (B+D) (A+B+C) (A+C+D)

Don’t care steps

i. They are represented using x

ii. They can be either 0’s or 1’s

iii. They are used to minimize expressions

iv. They can’t be grouped on their own

v. For min-terms they are given by ∑x

vi. And for max-terms they are given by Πx

0

0

0

0

0

0

0

0

0

0

0

0

0


Example:

i) F(A,B,C) = ∑m(1,3,4,6,7) + ∑x(0,5)

AB AB AB AB AB

C 00 01 11 10

C 0

C 1

F(A,B,C) = (C + A)

ii) F(A,B,C,D) = ∑m(1,2,3,4,5,6,7,8,9,11,12,13) + ∑x

AB AB AB AB AB

CD 00 01 11 10

CD 00

CD 01

CD 11

CD 10

F(A,B,C,D) = A+C+B

Exercise:

From the following expressions:

i) Obtain the minimized expressions

ii) Draw the logic diagrams for the obtained equation

F(A,B,C,D) = ∑m(0,1,2,3,5,10,11,13) + ∑x(4,14,15)

F(A,B,C,D) = Πm(1,2,5,7,8,10,11) . Πx(0,3,6,14,15)

1

1

1

1

1

1

X

X

1

1

1

1

1

1

1

1

1

1

1

1

X


COMBINATIONAL LOGIC CIRCUITS

These are logic diagrams where the output depends on only present inputs

Made from a combination of gates

Types include:

i. Adders

ii. Subtractors

iii. Multiplexers

iv. Demultiplexers

v. Encoders

vi. Decoders

1. Adders

They add inputs to obtain a sum and a carry out

Types of adders

i. Half Adder Has 2 inputs and 2 outputs

Block Diagram

A

Cout

S

B

Half - adder

A

B

0

1

0 1

1

0

S

A

B

0

1

0 1

1

CO


Logic Diagram

S

CO

AB

Truth table

A B S CO

0 0 0 0

0 1 1 0

1 0 1 0

1 1 0 1

ii. Full Adder

Has 3 inputs and 2 outputs

Block Diagram

A

Cout

S

B Full - adder

Cin

A

B

0

1

00 01

1

S

11 10

1

1

1

A

B

0

1

00 01

1

CO

11 10

11 1


Truth table

A B Ci S CO

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1

Logic Diagram A B CO

S

S0

2. Subtractors

They subtract inputs to obtain a difference and a borrow out

Types of subtractors

i. Half Subtractor Has 2 inputs and 2 outputs

Block Diagram

A

bo

D

B

Half -

subtractor

Truth table

A B D BO

0 0 0 0

0 1 1 1

1 0 1 0

1 1 0 0


D(AB) A

B 0 1

0

1

1

1

BA

b0(AB) A

B 0 1

0

1 1

Logic Diagram

DB

A

bo

ii. Full Subtractor

Has 3 inputs and 2 outputs

Block Diagram

A

b0

D

BFull -

subtractor

bi


Truth table

A B Bi D BO

0 0 0 0 0

0 0 1 1 1

0 1 0 1 1

0 1 1 0 1

1 0 0 1 0

1 0 1 0 0

1 1 0 0 0

1 1 1 1 1

D(A,B,bi) AB

C 00 01 11 10

0

1

1 1

11

bi(A, B, bi) AB

C 00 01 11 10

0

1

1

111

Logic Diagram

D

bi

bi

B

A

Full-subtractor


Multiplexers A device which has several inputs, 1-output and some select lines

It channels only one of the several inputs to the output

Block Diagram

I0

S0

F

In-1

I1

SM-1S1

MUX

n to 1

Number of inputs = n

Number of outputs =1

Number of select lines = m

The relationship between the select lines and inputs is given by:

Inputs – n = 2m

Design a 2 to 1 MUX block diagram

I0

F

I1

MUX

2 to 1

S0 I1 I0

F

Truth table

Inputs Output

S0 I1 I0 F

0 X 0 0

0 X 1 1

1 0 X 0

1 1 X 1


F = S0 I0 + S0 I1

When S0 = 0; Io is selected

When S0 = 1; I1 is selected

I1 and I0 can either be 0 or 1

Design a 4 to 1 MUX block diagram

I0

S 0

F

I1

S 1

4 to 1

M U XI 2

I 4

Truth table

Inputs Output

S1 S0 I3 I2 I1 I0 F

0 0 X X X 0 0

0 0 X X X 1 1

0 1 X X 0 X 0

0 1 X X 1 X 1

1 0 X 0 X X 0

1 0 X 1 X X 1

1 1 0 X X X 0

1 1 1 X X X 1

F = S1 S0 I0 + S1 S0 I1 + S1 S0 I2 + S2 S0 I3

F

S

1

S0 I3 I2 I1 I0

Exercise

i) Design a 8 to 1 MUX

ii) Design a 8 to 1 MUX using 2 to 1 MUX

iii) Design a 8 to 1 MUX using 4 to 1 MUX


3. Demultiplexers

Block Diagram

EN

S1

Inp

ut

Ou

tpu

t

Select lines

DEMUX

F0

F1

FM-1

S0 S2 Sm-1

Number of inputs = 1

Number of outputs =n

Number of select lines = m

The relationship between the select lines and inputs is given by:

2m

= n

Design a 1 to 2 Demux

Block Diagram

1 to 2

DemuxI

SO

F0

F1

Truth table

Inputs Output

S0 I F1 F0

0 0 0 0

0 1 0 1

1 0 0 0

1 1 1 0

F0 = S0 I

F1 = S0 I


F0

F1

S0EN

Design a 1 to 4 Demux

Block Diagram

1 to 2

DemuxI

SO

F0

F1

i0 I1

F2

F3

Truth table

Inputs Output

S1 I0 I F3 F2 F1 F0

0 0 I 0 0 0 1

0 1 I 0 0 1 0

1 0 I 0 1 0 0

1 1 I 1 0 0 0

F0 = S1 S0 I

F1 = S1 S0 I

F2 = S1 S0 I

F3 = S1 S0 I

Exercise

i. Design a 1 to 8 Demux

ii. Design a 1 to 8 Demux using 1 to 2 Demux

iii. Design a 1 to 8 Demux using 1 to 4 Demux

Encoders

Direct several inputs to a few outputs using the following relation

n = 2m

Where n = inputs

and m = ouputs


Block Diagram

I0

I!

In-1FM-1

F1

F0

ENCODER

Design a 2 to 1 encoder

Block Diagram

I0

I1

F02 to 1

encorder

Truth table

Inputs Output

I1 I0 F

0 1 0

1 0 1

F = I

EN I0

F0

F1


Block Diagram

I0

I1

I3

I2

F0

F0

4 to 2

encorder


Truth table

Inputs Output

I3 I2 I1 I0 F1 F0

0 0 0 1 0 0

0 0 1 0 0 1

0 1 0 0 1 0

1 0 0 0 1 1

F0 = I1 + I3

F1 = I2 + I3

Decoders

Direct a few inputs to several outputs using the following relation

2m

= n

Where m = inputs

and n = outputs

Block Diagram

EN

I0

In-1FM-1

F1

F0

DECODER


Block Diagram

EN

I0 F1

F0

DECODER

Truth table

Inputs Outputs

I F1 F0

0 0 1

1 1 0

F0 = I

F1 = I



Block Diagram

F0

F1

F3

F2

I0

I1

2 to 4

Decoder

Truth table

Inputs Output

I1 I0 F3 F2 F1 F0

0 0 0 0 0 1

0 1 0 0 1 0

1 0 0 1 0 0

1 1 1 0 0 0

F0 = I1 I0

F1 = I1 I0

F2 = I1 I0

F3= I1 I0


SEQUENTIAL LOGIC CIRCUITS

InputsCombinational

circuit

Memory

elements

Outputs

A logic circuit whose output depends on the present inputs and past outputs

Made of combinational logic circuits and memory elements

Have feedback

Can store a 1 or a 0

Mostly they have two outputs complimenting each other

Outputs Q and Q

If Q = 1; then Q = 0


They can be timed using a clock

There are of 2 types:

i. Synchronous

ii. Asynchronous

1. Synchronous

All the sequential circuits are controlled by a common clock

The propagation delay of the whole system is equivalent to the propagation

delay of the constituent parts of the system

They are stable

QQ

clk

2. Asynchronous

Not controlled by a common clock

Have a large propagation delay (time shift between input and output)

They are unstable

They are prone to many errors


Flip Flop

These are circuits which can change state according to the inputs

Block Diagram

J

Q

Q

K

SET

CLR

outputsinputs

It has 2 inputs and 2 outputs

Outputs Q and Q



They have feedback

Can also be clocked

Types of Flip Flops

i. RS Flip Flop

ii. JK Flip Flop

iii. D Flip Flop

iv. T Flip Flop

1. RS (Reset Set) Flip Flop

Block Diagram

Q

QSET

CLR

S

R

Logic Diagram using NOR gates

Q

Q

R

S

Truth table

S R Qn+1

0 0 No change

0 1 0 Reset

1 0 1 Set

1 1 Invalid/unstable/racing


NB:

Q Present state

Qn+1 Next state

Racing Changing state continuously

Logic Diagram using NAND gates

Q

Q

R

S

Operation

S R Qn+1

0 0 Invalid

0 1 0 Reset

1 0 1 Set

1 1 No change

Clock signal/Timing signal

It is a signal waveform (digital) used to synchronize the operation of

sequential circuits

Falling edgeRising edgeLevel zero

Level one

It triggers circuits to start operating

Types of triggering

i. Edge triggering

ii. Level triggering

A. Edge triggering

Where a circuit is triggered by a rising (leading) or a falling (trailing) edge

CLKCLK


B. Level triggering

Triggering is done by either a 1 or 0

CLKCLK

Clocked RS Flip Flop

Block Diagram

Q

QSET

CLR

S

R

clock

Logic diagram

clk

Q

Q

R

S

Truth table

Clk S R Qn+1

0 0 0 No change

0 0 1 No change

0 1 0 No change

0 1 1 No change

1 0 0 No change

1 0 1 0 Reset

1 1 0 1 Set

1 1 1 Invalid

2. JK (Jump Kill) Flip Flop

Block Diagram

J

Q

Q

K

SET

CLR

clock


Logic Diagram

K

clk

J

Q

Q

Truth table

Q J K Qn+1

0 0 0 0

0 0 1 0

0 1 0 1

0 1 1 1

1 0 0 1

1 0 1 0

1 1 0 1

1 1 1 0

3. D (Data Latch) Flip Flop

Block Diagram

Q

QSET

CLR

D

clock

Logic diagram

D

clk

Q

Q

Truth table

Q D Qn+1

0 0 0

0 1 1

1 0 0

1 1 1


4. T (Toggle) Flip Flop

Block Diagram

T

clk

Q

Ǭ

Logic diagram

T

clk

Q

Q

Truth table

Q T Qn+1

0 0 0

0 1 1

1 0 1

1 1 0

TRANSITION TABLE AND DIAGRAMS

Used in designing of counters

JK Flip Flop

Used in designing of counters

Transition table

Inputs

Q Qn+1 J K

0 0 0 X

0 1 1 X

1 0 X 1

1 1 X 0


Transition Diagram

10

O/X

1/X

X/O

X/1

5. D Flip Flop

Transition table

Input

Q Qn+1 D

0 0 0

0 1 1

1 0 0

1 1 1

Transition Diagram

10

O

1

1

O T Flip Flop

Transition table

Input

Q Qn+1 T

0 0 0

0 1 1

1 0 1

1 1 0

Transition Diagram

10

O

1

0

1


REGISTERS

Device used to store data

Mostly constructed using flip flops particularly D Flip Flops

Can be used to shift data serially or in parallel

Use a common clock

Types of Registers

i. Serial Input Serial Output (SISO)

They are used to obtain a single bit input and single bit output

ii. Serial Input Parallel Output (SIPO)

They obtain a single input bit and transfer it as several outputs

iii. Parallel Input Serial Output (PISO)

Obtains several input bits and channels them as a single output

Works as a multiplexer

iv. Parallel Input Parallel Output (PIPO)

Obtains several input bits and transfers them to several outputs

Works as a decoder or encoder

Serial Input Parallel Output (SIPO)

They are of 2 types:

i. Shift right register

Moves data/bits from left to right

Mostly they are converted using D Flip Flops

Diagram

Q

QSET

CLR

D

Q

QSET

CLR

D

Q

QSET

CLR

D

QC

QBQA

Input

Operation

Information/data is transferred with every clock pulse from left to right.

If for instance there is an input of 1011 after each clock pulse the bits will be

transferred from one flip flop to another.


E.g. Input 1011

QA QB QC QD

1st Clock Pulse 1 X X X

2nd

Clock Pulse 1 1 X X

3rd

Clock Pulse 0 1 1 X

4th

Clock Pulse 1 0 1 1

5th

Clock Pulse X 1 0 X

ii. Shift left register

Moves data/bits from right to left

Constructed using D Flip Flops

Clocked

Diagram

Q

QSET

CLR

D

D1

Q

QSET

CLR

D

D2

Q

QSET

CLR

D

D3

QDQC QB

Input

Q

QSET

CLR

D

D0

QA

Operation

Information/data is transferred with every clock pulse from right to left.

If for instance there is an input of 1100 after each clock pulse the bits will be

transferred from one flip flop to another.

E.g. Input 1100

QD QC QB QA

1st Clock Pulse X X X 1

2nd

Clock Pulse X X 1 1

3rd

Clock Pulse X 1 1 0

4th

Clock Pulse 1 1 0 0

5th

Clock Pulse 1 0 0 X


COUNTERS

A logic circuit which goes through a sequence and repeats the sequence

E.g. counting from

0 1 2 3 0 1

0

1

2

3

Constructed using flip flops

Has a clock

Types of Counters

i. Synchronous

Features

Have a common clock

Have less propagation time (PT) i.e. time it takes for data to move in circuit

from input to output

Stable

Has very few errors

ii. Asynchronous

Features

Don’t have a common clock

Have more propagation time (PT)

Not stable i.e. in terms of reliability

More prone to errors compared to the synchronous

Synchronous

Design

Procedure

i. Determine the number of steps the counter goes through.

ii. Determine the number of flip flops to be used using a number of states

Formula

2n = N; Number of states

Where n = Number of flip flops

Log2n = Log N

n = Log N

Log 2

iii. Round off to the higher number all the time even if you obtain pointers > 5.

iv. Use transition diagram to obtain inputs to the flip flops to be used

v. Document in a truth table


vi. Draw the logic diagram

Example:

Design a BCD counter

Synchronous and asynchronous using T flip flops

Synchronous

BCD 0 9 goes through

01

2

3

4

56

7

8

9

Number of states = 10 states

Number of flip flops n = Log N = log 10 ≈ 3.32 ≈ 4 flip flops

Log 2 log 2

Truth table

Present State

A B C D

Next State

A B C D

Flip flop inputs

TA TB TC TD

0 0 0 0 0 0 0 1 0 0 0 1

0 0 0 1 0 0 1 0 0 0 1 1

0 0 1 0 0 0 1 1 0 0 0 1

0 0 1 1 0 1 0 0 0 1 1 1

0 1 0 0 0 1 0 1 0 0 0 1

0 1 0 1 0 1 1 0 0 0 1 1

0 1 1 0 0 1 1 1 0 0 0 1

0 1 1 1 1 0 0 0 1 1 1 1

1 0 0 0 1 0 0 1 0 0 0 1

1 0 0 1 0 0 0 0 1 0 0 1

1 0 1 0

1 0 1 1

1 1 0 0

1 1 0 1

1 1 1 0

1 1 1 1


00 01 11 10

00

01

11

10

X

1

X

X

X X

AB

CD

X

11

1

00 01 11 10

00

01

11

10

X

1

X

X

X X

AB

CD

X

11

1

11

1

1

1 1

TD

00 01 11 10

00

01

11

10

X

1

X

X

X X

ABCD

1

X

TB

00 01 11 10

00

01

11

10

X

1

X

X

X X

ABCD

1

X

TB


Q

QSET

CLR

D

Q

QSET

CLR

D

Q

QSET

CLR

D

Q

QSET

CLR

D

A

B

C

D‘I’

Truth table

Present State

A B C D

Next State

A B C D

Flip flop inputs

CA CB CC CD

0 0 0 0 0 0 0 1 0 0 0 1

0 0 0 1 0 0 1 0 0 0 1 1

0 0 1 0 0 0 1 1 0 0 0 1

0 0 1 1 0 1 0 0 0 1 1 1

0 1 0 0 0 1 1 1 0 0 0 1

0 1 0 1 0 1 1 0 0 0 1 1

0 1 1 0 0 1 0 0 0 0 0 1

0 1 1 1 1 0 0 0 1 1 1 1

1 0 0 0 1 0 0 1 0 0 0 1

1 0 0 1 0 0 0 0 1 0 0 1

1 0 1 0

1 0 1 1

1 1 0 0

1 1 0 1

1 1 1 0

1 1 1 1


00 01 11 10

00

01

11

10

X

1

X

X

X

X

X

1

AB

CD

00 01 11 10

00

01

11

10

X

1

X

X

X X

AB

CD

1

00 01 11 10

00

01

11

10

X

1

X

X

X X

AB

CD

X

11

1


Q

QSET

CLR

D

Q

QSET

CLR

D

Q

QSET

CLR

D

Q

QSET

CLR

D

A

B

C

D

Documents

Digital logic.pdf