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Digital LLRF Technology
on a μTCA Platform
Eugene WuNorthwestern University
Mentor: Tim Berenc
Lee Teng Presentations
August 10, 2016
2Eugene Wu - Lee Teng Presentations - August 2016
CavityPA
FWDREV
Digital
Signal
Processing
- Field Control
- Fast Tuner Algorithm
- Slow Tuner Algorithm
- Calibration & Tune-Up
- etc.
PowerAmplifier
Cavity System
IF
LO
CLK
LLRF Controller Up-Converter
DACADC
FWD
REV
CAV
Reference
Down-Converters
ADC
ADC
ADC
IF
CAV
ADC
ADC
Slow ADCs
FastADCs
DAC
DAC
Slow DACs
RF
LO
i.e., Slow& Fast Tunersi.e., vibration
sensors
beam
Motivation
Low-level RF systems regulate the amplitude and phase of an RF cavity
Present APS LLRF systems use analog hardware
Long-term plans to upgrade to digital LLRF technology
Goal of project: evaluate microTCA based hardware for digital applications
3Eugene Wu - Lee Teng Presentations - August 2016
micro Telecommunications Computing Architecture (μTCA)
– Specifications-based hardware platform
– Offers an ecosystem of various modules from multiple vendors
– Used in high energy physics, digital LLRF, military, and
telecommunications
4Eugene Wu - Lee Teng Presentations - August 2016
Hardware Components
Vadatech AMC502 FPGA Carrier w/ Kintex-7 FPGA
– 2 FPGA Mezzanine Card (FMC) Slots
D-TACQ ACQ420 Analog-to-Digital (ADC) FMC
– 16-bit, Four-channel, 2 Mega-samples per second (MSPS)
D-TACQ AO400 Digital-to-Analog (DAC) FMC
– 18-bit, Four-channel, 1 MSPS
5Eugene Wu - Lee Teng Presentations - August 2016
FPGAFMC1
FMC0
CPU
GbE
mic
roT
CA
Backp
lan
e
6Eugene Wu - Lee Teng Presentations - August 2016
FPGA Design
Signal Processing
will go here
First Goal: Get ADC’s and DAC’s working
7Eugene Wu - Lee Teng Presentations - August 2016
AD
C s
eri
al in
terf
ace
DA
C s
eri
al in
terf
ace
ADC and DAC Timing Diagrams
8Eugene Wu - Lee Teng Presentations - August 2016
VHDL Design Acquired reference designs from Vadatech and D-TACQ
Modified to match hardware, wrote new DAC code
– e.g., 160 FMC pins x 2, DAC serial interface
~3600 lines of code
Synthesize design and debug
Use FPGA Integrated Logic Analyzer (ILA) to read internal
signals and debug
ModelSim simulation of DAC testbench
VHDL testbench for simulation/debugging
9Eugene Wu - Lee Teng Presentations - August 2016
Lab Setup
μTCA chassis Function generator and oscilloscope for testing
FMC Front panel connector breakout Full view of lab
Real-time Data from FPGA
10Eugene Wu - Lee Teng Presentations - August 2016
Integrated Logic Analyzer Output
11Eugene Wu - Lee Teng Presentations - August 2016
ADC Data
32K Point FFT
10 kHz full-scale input
on channel 1
𝑁𝑜𝑖𝑠𝑒 = 𝑁𝐹 ∗ 𝐵𝑊 ≅ 223 𝜇𝑉𝑅𝑀𝑆
Noise floor ~ -130 dBV2/Hz
𝑆𝑁𝑅 = 93 𝑑𝐵
Harmonics were found to be
due to signal source
12Eugene Wu - Lee Teng Presentations - August 2016
DAC Output
ADC
Input
DAC
Output
FFT of DAC Output (Stanford Research Systems SR785)
Summary
13Eugene Wu - Lee Teng Presentations - August 2016
Successfully demonstrated use of ADC and DAC modules
on a microTCA FMC carrier for baseband signal acquisition
Future work
– Past application of baseband signal processing was for
AM/PM noise suppression in APS storage ring RF systems
(previous Lee Teng project using proprietary National
Instruments hardware)
– Intent is to migrate noise suppression algorithm to microTCA
– Possibly start on signal processing next week
– Ultimately need to transition into intermediate frequency
signals for full digital LLRF