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Digital Integrated Circuits – EECS 312
http://robertdick.org/eecs312/
Teacher: Robert DickOffice: 2417-E EECSEmail: [email protected]: 734–763–3329Cellphone: 847–530–1824
GSI: Shengshou LuOffice: 2725 BBBEmail: [email protected]
HW engineers SW engineers
0
1
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3
4
5
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8
9
10
200 220 240 260 280 300
Cu
rre
nt
(mA
)
Time (seconds)
Typical Current Draw 1 sec Heartbeat
30 beats per sample
Sampling andRadio Transmission
9 - 15 mA
Heartbeat1 - 2 mA
Radio Receive for
Mesh Maintenance
2 - 6 mA
Low Power Sleep0.030 - 0.050 mA
Year of announcement
1950 1960 1970 1980 1990 2000 2010
Pow
er d
ensi
ty (
Wat
ts/c
m2 )
0
2
4
6
8
10
12
14
Bipolar
CMOS
VacuumIBM 360
IBM 370 IBM 3033
IBM ES9000
Fujitsu VP2000
IBM 3090S
NTT
Fujitsu M-780
IBM 3090
CDC Cyber 205IBM 4381
IBM 3081Fujitsu M380
IBM RY5
IBM GP
IBM RY6
Apache
Pulsar
Merced
IBM RY7
IBM RY4
Pentium II(DSIP)
T-Rex
Squadrons
Pentium 4
Mckinley
Prescott
Jayhawk(dual)
IBM Z9
Transistor dynamic behaviorInverter switch model
Inverter transfer curves and parameter optimizationHomework
Announcement
1 I will be in Montreal on Tuesday presenting a research paper atEmbedded Systems Week.
2 I will lecture at the Friday discussion time and location.
3 Mr. Lu will hold discussion at the Tuesday lecture time slot andlocation.
2 Robert Dick Digital Integrated Circuits
Transistor dynamic behaviorInverter switch model
Inverter transfer curves and parameter optimizationHomework
Review
1 How many metal layers are there in modern processes?
2 What is the problem with isotropic etching?
3 Explain a method of anisotropic etching.
4 Why Cu?
5 Why damascene?
6 What is CMP?
7 What is DRC?
3 Robert Dick Digital Integrated Circuits
Transistor dynamic behaviorInverter switch model
Inverter transfer curves and parameter optimizationHomework
Example low-k dielectric materials
Still active area.
Porous SiO2.
Carbon-doped SiO2.
Polymer.
4 Robert Dick Digital Integrated Circuits
Transistor dynamic behaviorInverter switch model
Inverter transfer curves and parameter optimizationHomework
Synchronous integrated circuit organization
Combinational networks separated by memory elements.
When memory elements clocked, changed signals race throughnext stage.
Clock frequency must be low enough to allow signal to propagatealong worst-case combinational path in circuit.
Derive and explain.
5 Robert Dick Digital Integrated Circuits
Transistor dynamic behaviorInverter switch model
Inverter transfer curves and parameter optimizationHomework
Lecture plan
1. Transistor dynamic behavior
2. Inverter switch model
3. Inverter transfer curves and parameter optimization
4. Homework
6 Robert Dick Digital Integrated Circuits
RC curves
0
1
2
3
4
5
0 2 4 6 8 10
VC
(V
)
Time (s)
f(vi, vf, τ, t) = vf + (vi - vf) e-t/τ
f(0, 5, 1, x)f(5, 0, 1, x)f(0, 5, 5, x)f(5, 0, 5, x)
v(t) = vf + (vi − vf )e−t/RC
Transistor dynamic behaviorInverter switch model
Inverter transfer curves and parameter optimizationHomework
Diode dynamic behavior
t (s)
t (s)
I (A)
Vin (V)
8 Robert Dick Digital Integrated Circuits
Transistor dynamic behaviorInverter switch model
Inverter transfer curves and parameter optimizationHomework
MOSFET capacitances
9 Robert Dick Digital Integrated Circuits
Transistor dynamic behaviorInverter switch model
Inverter transfer curves and parameter optimizationHomework
Gate capacitance
10 Robert Dick Digital Integrated Circuits
Transistor dynamic behaviorInverter switch model
Inverter transfer curves and parameter optimizationHomework
Gate capacitance schematic
Mode CGCB CGCS CGCD CG
Cutoff CoxWL 0 0 CoxWL + 2COWTriode 0 CoxWL/2 CoxWL/2 CoxWL + 2COW
Saturation 0 2/3CoxWL 0 2/3CoxWL + 2COW
CO is the overlap capacitance.
11 Robert Dick Digital Integrated Circuits
Transistor dynamic behaviorInverter switch model
Inverter transfer curves and parameter optimizationHomework
Gate capacitance variation with VGS
12 Robert Dick Digital Integrated Circuits
Transistor dynamic behaviorInverter switch model
Inverter transfer curves and parameter optimizationHomework
Gate capacitance variation with saturation
13 Robert Dick Digital Integrated Circuits
Transistor dynamic behaviorInverter switch model
Inverter transfer curves and parameter optimizationHomework
Diffusion capacitance diagram
14 Robert Dick Digital Integrated Circuits
Transistor dynamic behaviorInverter switch model
Inverter transfer curves and parameter optimizationHomework
Diffusion capacitance expression
Cdiff = Cbot + Csw
Cdiff = CjA + CjswP
Cdiff = CjLSW + Cjsw (2LS + W )
Cbot : Bottom capacitance to substrate.
Csw : Side-wall capacitances for three non-channel sides.
Cj : Junction capacitance constant in F/m2 (base units).
A: Diffusion area.
Cjsw : Junction side-wall capacitance constant in F/m.
P: Perimeter for three non-channel sides.
LS : Length of diffusion region.
W : Width of diffusion region (and transistor).
15 Robert Dick Digital Integrated Circuits
Transistor dynamic behaviorInverter switch model
Inverter transfer curves and parameter optimizationHomework
Junction capacitance
Cjsw is actually the diode capacitance we considered before.
What happens as reverse bias increases?
Can use worst-case approximation.
16 Robert Dick Digital Integrated Circuits
Transistor dynamic behaviorInverter switch model
Inverter transfer curves and parameter optimizationHomework
Capacitance linearization I
Can approximate variable capacitance as fixed capacitance.
Uses fitting.
Ceq =∆Qj
∆VD
Ceq =Qj (Vhigh) − Qj (Vlow )
Vhigh − Vlow
Ceq = KeqCj0
Keq =−φm
0
(Vhigh − Vlow ) (1 −m)
((φ0 − Vhigh)1−m − (φ0 − Vlow )1−m
)
17 Robert Dick Digital Integrated Circuits
Transistor dynamic behaviorInverter switch model
Inverter transfer curves and parameter optimizationHomework
Capacitance linearization II
Cj0: Capacitance when voltage bias of diode is 0 V.
m: Grading coefficient used to model effects of sharp (0.5) orlinear (0.33) junction transition (see Page 82 in textbook).
φ0 = φT ln(
NANDni
2
): Built-in potential, i.e., voltage across
junction due to diffusion at drift–diffusion equalibrium.
18 Robert Dick Digital Integrated Circuits
Transistor dynamic behaviorInverter switch model
Inverter transfer curves and parameter optimizationHomework
Capacitance parameters for default 0.25 µm processtechnology
COX CO Cj
(fF/µm2) (fF/µm) (fF/µm2)
NMOS 6 0.31 2PMOS 6 0.27 1.9
mj φb Cjsw mjsw φbsw
(V) (fF/µm) (V)
NMOS 0.5 0.9 0.28 0.44 0.9PMOS 0.48 0.9 0.22 0.32 0.9
Properties of bottom and sidewall.
19 Robert Dick Digital Integrated Circuits
Transistor dynamic behaviorInverter switch model
Inverter transfer curves and parameter optimizationHomework
Upcoming topics
MOSFET dynamic behavior.
Wires.
CMOS inverters.
20 Robert Dick Digital Integrated Circuits
Transistor dynamic behaviorInverter switch model
Inverter transfer curves and parameter optimizationHomework
Review
What are the five most important to model capacitances forMOSFETs?
Explain their locations/sources.
How do they depend on operating region?
How are drain and source capacitances calculated?
21 Robert Dick Digital Integrated Circuits
Review: diode capacitance
CJ =CJ0
(1 − VD/Φ0)m
m = 0.5 for abrupt junctions, m = 0.33 for linear junctions
Transistor dynamic behaviorInverter switch model
Inverter transfer curves and parameter optimizationHomework
A change to gate insulation
Mark T. Bohr, Robert S. Chau, Tahir Ghani, and Kaizad Mistry.
The High-k Solution.IEEE Spectrum, October 2007.
What was the problem?
What was its cause?
What was the solution?
Key concepts: gate leakage, tunneling, high-κ dielectric, chargetraps, single atomic layer deposition, and threshold voltagecontrol.
23 Robert Dick Digital Integrated Circuits
Transistor dynamic behaviorInverter switch model
Inverter transfer curves and parameter optimizationHomework
Lecture plan
1. Transistor dynamic behavior
2. Inverter switch model
3. Inverter transfer curves and parameter optimization
4. Homework
24 Robert Dick Digital Integrated Circuits
Transistor dynamic behaviorInverter switch model
Inverter transfer curves and parameter optimizationHomework
Simple inverter context
25 Robert Dick Digital Integrated Circuits
Transistor dynamic behaviorInverter switch model
Inverter transfer curves and parameter optimizationHomework
Inverter layout
26 Robert Dick Digital Integrated Circuits
Transistor dynamic behaviorInverter switch model
Inverter transfer curves and parameter optimizationHomework
Implications of cell-based design
Power and ground sharing breaks isolation.
27 Robert Dick Digital Integrated Circuits
Transistor dynamic behaviorInverter switch model
Inverter transfer curves and parameter optimizationHomework
Simplest switch model of inverter
28 Robert Dick Digital Integrated Circuits
Transistor dynamic behaviorInverter switch model
Inverter transfer curves and parameter optimizationHomework
Switch model transient behavior
Repeatedly charging/discharging load C .
tpHL = f (RonCL).
Why?
29 Robert Dick Digital Integrated Circuits
Transistor dynamic behaviorInverter switch model
Inverter transfer curves and parameter optimizationHomework
Inverter switch model tpHL derivation
Both tpHL and tpLH defined as time from 0.5VDD input crossing to0.5VDD output crossing. Assume step function on input.
VC = VDDe−t/RC (1)
Solve for VC = VDD/2.
VDD/2 = VDDe−t/RC (2)
1/2 = e−t/RC (3)
ln (1/2) = −t/RC (4)
t = −RC · −0.69 (5)
t = 0.69RC = 0.69τ (6)
30 Robert Dick Digital Integrated Circuits
Transistor dynamic behaviorInverter switch model
Inverter transfer curves and parameter optimizationHomework
Lecture plan
1. Transistor dynamic behavior
2. Inverter switch model
3. Inverter transfer curves and parameter optimization
4. Homework
31 Robert Dick Digital Integrated Circuits
Transistor dynamic behaviorInverter switch model
Inverter transfer curves and parameter optimizationHomework
NMOSFET I–V characteristics
Review: Is this a velocity-saturated short-channel device? How can you tell?
32 Robert Dick Digital Integrated Circuits
Transistor dynamic behaviorInverter switch model
Inverter transfer curves and parameter optimizationHomework
Inverter load characteristics
33 Robert Dick Digital Integrated Circuits
Transistor dynamic behaviorInverter switch model
Inverter transfer curves and parameter optimizationHomework
CMOS inverter transfer curve
34 Robert Dick Digital Integrated Circuits
Transistor dynamic behaviorInverter switch model
Inverter transfer curves and parameter optimizationHomework
Switching threshold derivation I
Find voltage for which Vin = Vout . Known: Both NMOSFET andPMOSFET saturated at this point. Recall that
IDSAT = µCoxW
L
((VGS − VT )VDSAT − VDSAT
2
2
)(1)
35 Robert Dick Digital Integrated Circuits
Transistor dynamic behaviorInverter switch model
Inverter transfer curves and parameter optimizationHomework
Switching threshold derivation II
Working to find VM . Find VGS at which NMOSFET and PMOSFETID values equal.
= kVDSAT (VGS − VT ) − VDSAT
2(2)
0 = knVDSATn
(VM − VTn − VDSATn
2
)+
kpVDSATp
(VM − VTp −
VDSATp
2
)(3)
36 Robert Dick Digital Integrated Circuits
Transistor dynamic behaviorInverter switch model
Inverter transfer curves and parameter optimizationHomework
Switching threshold derivation III
Solve for VM .
VM =
(VTn + VDSATn
2
)+ r
(VDD + VTp +
VDSATp
2
)1 + r
. (4)
r =kpVDSATp
knVDSATn=νsatpWp
νsatnWn(5)
ν =µξ
1 + ξ/ξc(6)
ν: Charge carrier speed.
ξ: Field strength.
ξc : Field strength at which scattering limits further increase incarrier speed.
37 Robert Dick Digital Integrated Circuits
Transistor dynamic behaviorInverter switch model
Inverter transfer curves and parameter optimizationHomework
Inverter threshold dependence on transistor conductanceratio
38 Robert Dick Digital Integrated Circuits
Transistor dynamic behaviorInverter switch model
Inverter transfer curves and parameter optimizationHomework
Upcoming topics
CMOS inverter dynamic behavior.
Logic gates.
39 Robert Dick Digital Integrated Circuits
Transistor dynamic behaviorInverter switch model
Inverter transfer curves and parameter optimizationHomework
Lecture plan
1. Transistor dynamic behavior
2. Inverter switch model
3. Inverter transfer curves and parameter optimization
4. Homework
40 Robert Dick Digital Integrated Circuits
Transistor dynamic behaviorInverter switch model
Inverter transfer curves and parameter optimizationHomework
Homework assignment
1 October: Read sections 3.3.3, 5.1, 5.2, 1.3.2, and 1.3.3 in
J. Rabaey, A. Chandrakasan, and B. Nikolic. Digital IntegratedCircuits: A Design Perspective.Prentice-Hall, second edition, 2003. Read as much as you can by27 September.
26 October: Extended Homework 1 due date due to difficultygetting help during office hours.
3 October: Lab 2.
41 Robert Dick Digital Integrated Circuits