Dezső Sima September 2008 (Ver. 1.0) Sima Dezső, 2008 5. Synchronous memory modules

Dezső Sima

September 2008

(Ver. 1.0) Sima Dezső, 2008

5. Synchronous

memory modules

Overview

1. Design space of memory modules

4. ECC•

3. Registering•

5. Presence detect •

•

6. Keying

7. Summing up the main features of memory modules•

•

2. Basic features•

8. References•

Layout of memory modules

Registering

(Buffering)

Presence detect

ECC KeyingBasic featuresof memory modules

Figure: Main dimensions of the design space of the layout of memory modules

Layout of memory modules

1. Design space of memory modules (1)

Basic features of memory modules

Module width

(Data/Data+ECC)

Module type No. of ranksprovided on the

module

No. of module sidespopulated

Figure: Basic features of memory modules

2. Basic features (1)

Module types

Figure : Main module types of general use

Memory card

(build up of DIPs)


• attached via the ISA bus or a dedicated bus of the motherherboard

• DRAMs packaged in DIPs1 mounted on a PC-card 2

• used as the main memory or add-on memory in early PCs (8088 or 80286 based).

1 DIP: Dual In-line Package2 PC: Printed Circuit


Memory cards


Figure: 8-Bit ISA PC Memory Card (Gold 5150) [12]

Module types

SIPP

(Single In-linePin Package)


Memory card

(build up of DIPs)



Figure: SIPP module [11]

1 Bytewide

30 pins

Module types

SIPP


(Single In-lineMemory Module)

SIMM


Memory card

(build up of DIPs)



Figure: SIMM modules

FPM/EDO

1-Byte/30-pin

4-Byte/72-pin

FPM

SIMM

72-pin30-pin

Width (Data/Data+parity)

DRAM-type FPMFPM

(32/36-bit)(8/9-bit)

EDO

Voltage 5 V/3.3 V5 V 5 V/3.3 V

Typ. module capacity 2 – 32 MB256 KB – 8 MB 4 – 64 MB

Typ. use in connectionwith the processors

late 386486

early Pentium

286early 386

486Pentium

Figure : Main features of SIMM modules

First introducedin Intel’s chipsets

1993(~1986?) 1995


Module types

SIPP


SIMM


DIMM

(Dual In-lineMemory Module)


Memory card

(built up of DIPs)


SDRAM

DDR

DDR2

DDR3

168-pin

184-pin

240- pin

240-pin

Figure: DIMM modules (8-Byte wide)

Figure : Main features of DIMMs

DIMM

168-pin 240-pin184-pin

Width (Data/Data+ECC)

DRAM-type EDO DDR2DDR

(64/72-bit) (64/72-bit)(64/72-bit)

SDRAMFPM DDR3

Voltage 5 V/3.3 V 1.8 V2.5 V3.3 V5 V/3.3V 1.5 V

Typ. capacity [MB] 1-16 256–4096128 –102416-512 1-16 512–496

Typ. use withthe processors

Pentium (3.3V)

Pentium 4Pentium DCore2 Duo

Pentium 4Pentium (3.3V)Pentium IIPentium III

Pentium (3.3V)

Core2 Duo

DIMM first intro.in Intel’s chipsets

(1996) (2004)(2002)(1996)(1995) (2007)


Module types

SIPP DIMM


SIMM

(Dual In-lineMemory Module)


SODIMM

(Small OutlineDual In-line

Memory Module)


Memory card

(build up of DIPs)



Figure: SO-DIMM modules

SDRAM

DDR2

4 Byte/72 pin

8 Byte/200 pin

Figure : Main features of SODIMM modules

SODIMM


Width (Data)

EDO DDR2DDR

32-bit 64-bit64-bit

EDOFPM DDR3


Typ. capacity [MB] 4-64 256–2048128 –10248-64 4-64 512–4096

Est. year of intro. ~1995 20042002~1996~1994 2007

SDRAM

3.3 V

64-512

1996

64-bit

200-pin


(Data/Data+ECC)

1-byte wide modules 4-byte wide modules 8-byte wide modules

Modules width

(32/36-bits)(8/9-bits) (64/72-bits)

386 (1985) and 486 (1988) based PCs:

4-byte wide data bus

8088-based PCs (1981): 1-byte wide data bus,

80286 based PCs (1984): 2-byte wide data bus

Pentium (1993), and subsequent processors:

8-byte wide data bus

Figure : Memory module widths vs data bus width of the processor bus in x86 processors


Number of memory module sides populated

Memory module populated on both sides

Memory modulepopulated on one side

Figure: Population alternatives of memory modules


• Includes usually one rank • Includes usually two ranks but may include also• just one rank

Number of ranks provided on the memory module

Two ranks Single rank

Figure: Number of ranks provided on the memory module

Both alternatives are used by the manufacturers


Registering

Registering

Registered modules Unregistered modules

Main memories ofdesktops/laptops

Main memories ofservers

Typical use

Figure: Registering alternatives of memory modules

ECC Typically no Typically yes

With module type

3. Registering (1)

DIMM--

Typical use: in servers (Memory capacities: a few tens of GB)

3. Registering (2)

Registered DIMM (RDIMM)

Unregistered DIMMs (UDIMMs)

Typical use: in desktops/laptops (Memory capacities: up to a few GB)

Higher memory capacities need more modules

Higher loading the lines

Signal integrity problems

Buffering address and command lines,Phase locked clocking of the modules

Problems arising while implementing higher memory capacities

Figure:Typical layout of a registered memory module with ECC [24]

• Two register chips, for buffering the address- and command lines• A PLL (Phase locked loop) unit for deskewing clock distribution.

Typical implementation

3. Registering (3)

ECC

RegisterRegister PLL

3. Registering (4)

Figure: Example. Block diagram of a registered DDR DIMM [29]

SDRAM

SDRAM

SDRAM

SDRAM

SDRAM

SDRAM

SDRAM

SDRAM

SDRAM

PI74SSTV16857 Register

PI74SSTV16857 Register

Address/Controlform

Motherboard

Address Controlfrom

Motherboard

PI6CV857PLL

Input Clockfor

Motherboard

Data From / To Motherboard

Number of register chips required

• Synchronous memory modules have about 20 - 30 address and control lines,

• Register chips buffer usually 14 lines,

Typically, two register chips are needed per memory module [29].

3. Registering (5)

Register chips

Aim

• in order to increase the number of supported DIMM slots (max. mem. capacity) needed first of all in servers,• by reducing signal loading in a memory channel.

Buffering address and control lines,

3. Registering (6)

Functional block diagramof a registered SDRAM DIMM [28],with one rank, built up of

• 8 x8 SDRAMs• 1 ECC unit• 1 Register unit• 1 PLL unit and• 1 SPD unit.

U3

DQDQDQDQDQDQDQDQ

DQM CS#

U12

DQDQDQDQDQDQDQDQ

DQM CS#

U4

DQDQDQDQDQDQDQDQ

DQM CS#

U10

DQDQDQDQDQDQDQDQ

DQM CS#

U13

DQDQDQDQDQDQDQDQ

DQM CS#

U1

DQDQDQDQDQDQDQDQ

DQM CS#

U14

DQDQDQDQDQDQDQDQ

DQM CS#

U2

DQDQDQDQDQDQDQDQ

DQM CS#

U11

DQDQDQDQDQDQDQDQ

DQM CS#

REGISTER

PPL

Registering (buffering) the address and control lines

Figure: Registered signals in case of an SDRAM memory module [28]

REGISTER

REGE: Register enable signal

3. Registering (7)

Note: Data (DQ) and data strobe (DQS) signals are not registered.

PLL unit (Phase locked loop unit)

• Clock signals (CK) are sent in parallel with the address and control signals from the memory controller and need to be distributed to the DRAM devices and register units mounted on the module.

• Clock distribution means amplification and branching the clock signal typically up to 9-18 DRAM devices and 2 register units (one/two sided populated modules).

• The circuitry implementing clock distribution causes a skew between the input clock and the clock signals arriving at the DRAM and register chips.

• Clock skew reduces the width of the usable window and thus limits the operation speed.

• A PLL mounted to the memory module deskews the clock and thus improves timing budget and raises operating speed.

The need to deskew the clock signal distributed on the memory module

3. Registering (8)

Figure: The task of clock distribution in case of a double sided registered memory module (actually in case of an SDRAM module) (based on [21])

3. Registering (9)

Figure: Skew due to capacitive loading of the clock line (CK-2)

CK-1

CK-2

Skew

3. Registering (10)

Data

CK

tS

tH

Min. DVW

Available DVW

Data

CK

tS

tH

Min. DVW

Available DVW

Center aligned clock Skewed clock

Figure: Reduction of operation tolerances due to clock skew (ideal signals assumed)

A larger skew would even jeopardize or prevent correct operation

Deskewing of clock distribution is needed

3. Registering (11)

The signal tobe deskewed

Figure: Principle of deskewing by means of a PLL (Based on [20])

The PLL unit compares the phases of the Ref. signal and the signal to be deskewed, generates an error signal and controls the VCO with this error signal.

Operation

VCO: Voltage Controlled Oscillator

Principle of deskewing by means of a PLL (Phase Locked Loop) unit

3. Registering (12)

Figure: Typical clock distribution schemes of one- and two-sided SDRAM modules [28], [41], [21]

3. Registering (13)

PLL PLL

PLL

Note: CK0 is an open ended signal

Figure: Typical clock distribution schemes of two-sided DDR/DDR2 modules [13], [14]

3. Registering (14)

PLLPLL

Note: CK0 is a differential signal

Examples

PLL on an SDRAM modules

Note

• In case of SDRAM devices the clock signal is used to gate in

the address, control and data lines,

• in case of DDR/DDR2/DDR3 devices the clock signal is used to gate in

the address and control lines, whereas the data lines are gated in by the data strobe signals (DQS).

3. Registering (15)

3. Registering (16)

Functional block diagramof a registered SDRAM DIMMwith one rank [28], built up of

• 8 x8 SDRAMs• 1 ECC unit• 1 Register unit and• 1 PLL unit.

U3

DQDQDQDQDQDQDQDQ

DQM CS#

U12

DQDQDQDQDQDQDQDQ

DQM CS#

U4

DQDQDQDQDQDQDQDQ

DQM CS#

U10

DQDQDQDQDQDQDQDQ

DQM CS#

U13

DQDQDQDQDQDQDQDQ

DQM CS#

U1

DQDQDQDQDQDQDQDQ

DQM CS#

U14

DQDQDQDQDQDQDQDQ

DQM CS#

U2

DQDQDQDQDQDQDQDQ

DQM CS#

U11

DQDQDQDQDQDQDQDQ

DQM CS#

REGISTER

PPL

SPD EEPROM A0WP A1 A2

Functional block diagramof a registered DDR3 DIMM with 2 ranks [15], built up of

• 16 x8 DDR3 devices• 2 ECC unit• 1 Register and PLL unit and• 1 Temp. sensor/SPD unit.

3. Registering (17)

U8

DQDQDQDQ

DQDQ

DQDQ

CMU CS#

ZQ

NWTRDQS

DQS#DQSTRDQS#

U15

DQDQDQDQ

DQDQ

DQDQ

CMU CS#NWTRDQS

DQS#DQSTRDQS#

U9

DQDQDQDQ

DQDQ

DQDQ

CMU CS#

ZQ

NWTRDQS

DQS#DQSTRDQS#

U14

DQDQDQDQ

DQDQ

DQDQ

CMU CS#NWTRDQS

DQS#DQSTRDQS#

U10

DQDQDQDQ

DQDQ

DQDQ

CMU CS#

ZQ

NWTRDQS

DQS#DQSTRDQS#

U13

DQDQDQDQ

DQDQ

DQDQ

CMU CS#NWTRDQS

DQS#DQSTRDQS#

U11

DQDQDQDQ

DQDQ

DQDQ

CMU CS#

ZQ

NWTRDQS

DQS#DQSTRDQS#

U12

DQDQDQDQ

DQDQ

DQDQ

CMU CS#NWTRDQS

DQS#DQSTRDQS#

U1

DQDQDQDQ

DQDQ

DQDQ

CMU CS#

ZQ

NWTRDQS

DQS#DQSTRDQS#

U21

DQDQDQDQ

DQDQ

DQDQ

CMU CS#NWTRDQS

DQS#DQSTRDQS#

U2

DQDQDQDQ

DQDQ

DQDQ

CMU CS#

ZQ

NWTRDQS

DQS#DQSTRDQS#

U20

DQDQDQDQ

DQDQ

DQDQ

CMU CS#NWTRDQS

DQS#DQSTRDQS#

U3

DQDQDQDQ

DQDQ

DQDQ

CMU CS#

ZQ

NWTRDQS

DQS#DQSTRDQS#

U19

DQDQDQDQ

DQDQ

DQDQ

CMU CS#NWTRDQS

DQS#DQSTRDQS#

U4

DQDQDQDQ

DQDQ

DQDQ

CMU CS#

ZQ

NWTRDQS

DQS#DQSTRDQS#

U18

DQDQDQDQ

DQDQ

DQDQ

CMU CS#NWTRDQS

DQS#DQSTRDQS#

U5

DQDQDQDQ

DQDQ

DQDQ

CMU CS#

ZQ

NWTRDQS

DQS#DQSTRDQS#

U17

DQDQDQDQ

DQDQ

DQDQ

CMU CS#NWTRDQS

DQS#DQSTRDQS# Temperature senson/

SPD EEPROM A0EVT A1 A2

DDR3SDRAM

DDR3SDRAM

Register

and

PLL

Figure: Integrated register and PLL unit of a DDR3 DIMM [15]

3. Registering (18)

Register

and

PLL

Figure: Overview of a clock distribution circuitry intended for DDR devices [16]

3. Registering (19)

PLL

IN

OUT1

OUT ‘N’

Feedback

SDRAMStack

SDRAMStack

Reg. 1

Reg. 2

Implementation of the clock distrubution circuitry including a PLL unit

The clock distribution circuitry including PLL became standardised by JEDEC in connection with DDR devices in 2000 [17]

10 outputsto the DDR devices

and the registerunit(s)

Phase lock between

FBIN/FBOUT and CK

Output of the feedback loop

Figure: Block diagram of the clock distribution circuitry [17]

Input of the feedback loop

3. Registering (20)

• The PLL unit compares the phases of the output clock signal (FBOUT) and the input clock signal (CK) and generates an error signal which is fed back to control the PLL unit in order to achieve a phase match between FBOUT/FBIN and the incoming clock signal (CK) as close as possible.

• The output of the PLL unit (Yi/Yi#) can be considered as the negatively delayed clock signal (CK).

The operation of the PLL unit

3. Registering (21)

In connection with the main memory PLLs are widely used to deskew signals or to align signal edges, such as

• DDR/DDR2/DDR3 SDRAM devices include PLLs to achieve a phase match of the Data Strobe Signal (DSQ) with the data signals (DQ) in case of data reads,

• DDR/DDR2/DDR3 SDRAM memory controllers use PLLs

Use of PLLs in main memories

to center align write data (DQ) with the data strobe signal (DQS) and align the edges of DQS with CK,

• In multi module memory systems PLLs are utilized to deskew clocking.

• in case of data writes

the device sends edge aligned data (DQ) with the DQS, it is the task of the controller’s PLL to shift DQS edge to the center of the data read.

• in case of data reads

• SDRAM/DDR/DDR2/DDR3 modules include PLLs to deskew clock distribution on the memory card (as discussed above),

3. Registering (22)

3. Registering (23)

Figure: Aligning read and write data in DDR/DDR2/DDR3 devices [19]

Remark

If there are multiple DRAM modules connected to a memory channel an extra PLL is needed to deskew the multi-module memory system

Figure: Deskewing a multi-module memory system by a PLL [29]

PLLorClockBuffer

MemoryControlleror BusRe-driveChip

1 2 43

3. Registering (24)

Figure:Registered memory card with ECC [24]

4. ECC (1)

Module with ECC

ECC

Implemented as SEC-DED (Single Error Corretion Double Error Detection)

Single Error Correction

The minimum number of check-bits (P) for single bit error corection ?

2P ≥ the minimum number of states to be distinguished.

For D data bits P check-bits are taken.

Figure: The code word

Requirement:

Data bits Check bits

4. ECC (2)

ECC basics (as used in SDRAMs)

• D + P states

to specify the bit position of a possible single bit error in the code word for both data and check bits,

• one additional state to specify the „no error” state.

2P ≥ D + P + 1

The minimum number of states to be distinguished:

the minimum number of states to be distinguished is: D + P + 1

to implement single bit error correction the minimum number of check bits (P) needs to satisfy the requirement:

Accordingly:

4. ECC (3)

Double error detection

an additional parity bit is needed to check for an additional error.

Then the minimum number of check-bits (CB) needed for SEC-DED is:

CB = P + 1

2CB-1 ≥ D + CB -1 + 1

Table: The number of check-bits (CB) needed for D data bits

i.e.

Data bits (D) Check bits (CB)

1 2

3:2 3

7:4 4

15:8 5

31:16 6

63:32 7

127:64 8

255:128 9

511:256 10

4. ECC (4)

2CB-1 ≥ D + CB

A constructor matrix [C] defines the check-bits [CB]:

[CB] = [D] × [C]

E.g. The constructor matrix [C] used in [22] is:

4. ECC (5)

Principle of ECC coding

Table: The constructor matrix [C] used in [22] to generate the

check-bits [CB]

(Modified Hamming code)

4. ECC (6)

Calculation of the check-bits [CB] while using the constructor matrix [C] given before:

[CB0] = [D1] [D2] [D3] [D5] [D8] [D9] etc. ++ + + +

.

.

.

[CB7] = [D0] [D1] [D2] [D3] [D4] [D5] etc. ++ + + +

[CB1] = [D0] [D1] [D2] [D4] [D6] [D8] etc. ++ + + +

+ denotes the EXCLUSIVE OR operation

4. ECC (7)

Principle of error detection and correction [23]:

First a generator matrix [G] is constructed from the identity matrix [I] and the constructor matrix [C] as follows:

[G] = [I, C]

E.g. An 8 × 8 identity matrix [I] is:

1 0 0 0 0 0 0 00 1 0 0 0 0 0 00 0 1 0 0 0 0 00 0 0 1 0 0 0 00 0 0 0 1 0 0 00 0 0 0 0 1 0 00 0 0 0 0 0 1 00 0 0 0 0 0 0 1

[I] =

4. ECC (8)

Then the code word vector [D, CB] will be multiplied with the transpose of the generator matrix [G’]1, yielding the syndrome vector [S]:

• if all elements of the syndrome vector are zeros, no error occured,

• else the syndrome vector [S] identifies the error type and location of any single bit errors.

1 The transpose of the matrix [G] is the matrix [G’] where

the lines of the matrix [G] become the rows of the matrix [G’].

E.g. for a code word consisting of 64 bit data and 8 check bits an 8 bit syndrom vector is calculated.

E.g. Interpretation of the syndrome vector [S] in [22]:

Interpretation of the syndrome vector:

4. ECC (9)

[S] = [D, CB] × [G’]

Table: Interpretation of the bits of the syndrome vector [S] in [22] to identify possible errors

4. ECC (10)

A single bit error is then corrected by reverting the erroreneous bit in the identified position, or a double or multiple bit error is reported.

(in memories assuming 64-bit access width)

4. ECC (11)

Implementation of SEC

Figure: Block diagram of a 64-bit SEC-DED error correction/detection unit [22]

4. ECC (12)

Operation (without taking use of the read/write FIFO buffers)

Writing data to memory

Incoming data (SD0-63) are simply forwarded through the latches and multiplexers to the memory (MD0-63). Checkbits are generated and also fowarded to the memory (CBSYN0-7)

Reading data from memory

Memory and checkbit data are latched in (MD0-63/CB0-7). Internal MD checkbits are generated and compared to the incoming checkbits. Syndrome bits are also generated and used to detect and correct errors. Finally, memory data (MD0-63) (corrected if needed and feasible) are forwarded to the memory controller.

ECC operation increases memory latency by about 15-22 ns (time delay between SDin0-63 to MDout0-63 and vice versa).

4. ECC (13)

After turning on the computer the BIOS1 runs the POST2 routine,that among others detects the presence and key features of the subsystems thatmake up the computer, such as the memory.

Early memory modules (starting with SIMM/30 and in larger scale with SIMM/72)

PPD (Parallel Presence Detect)

Subsequent memory modules

(starting with DIMM/168)

SPD (Serial Presence Detect)

1 BIOS: Basic Input/Output System2 POST: Power-On Self-Test

5. Presence detect (1)

Presence detect (PD)

Usually 4-8 pins of the edge connector of the module represent key features, such as memory density, organisation, speed etc.

E.g. For a SIMM/72 module:

65 DQ15 Data 15

66 n/c Not connected

67 PD1 Presence Detect 1




71 n/c Not connected

72 VSS Ground

Pin Use Interpretation . . . . . .


PPD

Coding and interpretation of the present detect (PD) bits:

• PD bits are subdivided into subfields,

• each subfield is binary coded,

• binary code has a given interpretation.

PD4 PD3 Access time

0 0 50, 100 ns

0 1 80 ns

1 0 70 ns

1 1 60 ns

Implementation of the coding:

0: a resistor connects the pin to ground1: no resistor

As new DRAM technologies (such as FPM, EDO, SDRAM) introduce new features:

more and more edge connector pins would be required.


Based on

• an 8-pin EEPROM (Erasable/Programmable Read-Only Memory) of 256-Byte,

• connected via a separate I2C bus to the memory controller.

Figure: 8 pin-SPD EEPROM [26]

Figure: SPD chip on a DDR3 module [25]


SPD

The SPD table is standardized by JEDEC (1997)

Each byte reflects a particular feature and has a numeric (decimal/hexadecimal) value.

Table: Excerpt of an SDRAM SPD table [27]


Relevant features of the memory modules are held in a byte organised table, called the SPD table.

E.g.

(except DDR3 SPD tables, where bytes 0 – 175 are allocated).

Basic table format

Bytes

0 –127: allocated128- 255: free for the user

Coding of the table entries (bytes)

is given in the appropriate JEDEC Module Serial Presence Detect Specification.

E.g. Coding of bytes 3 and 4 of DDR3 SPD tables:


Byte 3 Module type00H Undefined01H Registered DIMM (RDIMM)02H Unregistered DIMM (UDIMM)03H Small Outline DIMM (SODIMM)

Byte 4 Device density

01H 512 Mb02H 1 Gb03H 2 Gb04H 4 Gb

The SPD may also contains manufacturer's data, such manufacturer’s ID, part number, etc.


Different SPD table formats for different DRAM technologies

(FPM/EDO, SDRAM, DDR, DDR2, DDR3)

As DRAM technology evolves

the SPD table needs to hold more and more DRAM features.

SPD table formats for

modules differ significantly.


(FPM/EDO, SDRAM, DDR, DDR2, DDR3)

Table: Sample SPD table for FPM/EDO modules [27]


Table: Sample SPD table for SDRAM modules (1) [27]


Table: Sample SPD table for SDRAM modules (2) [27]


Table: Sample SPD table for DDR3 modules (1) [25]


Table: Sample SPD table for DDR3 modules (2) [25]


Low-speed serial bus, using

• a serial bidirectional clock line (SCL) and• a serial bidirectional data line (SDA).

After powering up the computer, the memory controller reads the content of the SPD table during running the POST routine through this serial bus.


I2C bus (Inter-IC bus)

From the SIMM 72 on both memory modules and sockets have keys (notches) to prevent inserting not fitting modules into the sockets.

Example:

Figure: Module keys on an SDRAM DIMM [1]

Keys

The position and interpretation of the keys is standardised by JEDEC, (in the standards MO-116 for SIMM 72 modules, MO-161 for SDRAM DIMMs etc.)

The keys may indicate supply voltage (5 V/ 3.3 V), module type (like RIMM etc)or presence of SPD.

6. Keying (1)

Keying the modules

72-pin FPM/EDO SIMMs

6. Keying (2)

Examples

Figure: Keying of 72-pin SIMMs (FPM or EDO DRAMs) [2]

168-pin SDRAM DIMMs

6. Keying (3)

Figure: Keying of 168-pin SDRAM DIMMs [3]

184-pin DIMMs

RIMM [5]

DDR [4]

6. Keying (4)

Figure: Keying of 184-pin DIMMs

6. Keying (5)

Figure: 184-pin RIMM module (Rambus DRAM) [18]

DDR2 [6]

DDR3 [7]

FB-DIMM [8]

240-pin DIMMs

6. Keying (6)

Figure: Keying of 240-pin DIMMs

6. Keying (7)

Figure: Keying diferences of DDR and DDR2 modules [9]

Figure: Keying differences of DDR3 (top) and DDR2 (bottom) modules [10]

6. Keying (8)

SIMM

72-pin30-pin

Width (Data/Data+parity)

DRAM-type FPMFPM

(32/36-bit)(8/9-bit)

EDO

Voltage 5 V/3.3 V5 V 5 V/3.3 V

Present detect PPD (4-bit)On a few implementations PPD (4-bit)

Unreg./registered unregisteredunregistered unregistered

Typ. module capacity 2 – 32 MB256 KB – 8 MB 4 – 64 MB

Typ. use in connectionwith the processors

late 386486

early Pentium

286early 386

486Pentium

Figure : Main features of SIMM modules

First introducedin Intel’s chipsets

1993(~1986?) 1995

7. Summing up the main features of memory modules (1)

DIMM


Width (Data/Data+ECC)

DRAM-type EDO DDR2DDR

(64/72-bit) (64/72-bit)(64/72-bit)

SDRAMFPM DDR3


Present detect PPD (8b)SPD (opt)

SPDSDPSPDPPD (8b SPD

Unreg./registered both bothbothbothboth unreg. (yet)

Typ. capacity [MB] 1-16 256–4096128 –102416-512 1-16 512–496

Typ. use withthe processors

Pentium (3.3V)

Pentium 4Pentium DCore2 Duo

Pentium 4Pentium (3.3V)Pentium IIPentium III

Pentium (3.3V)

Core2 Duo

Figure : Main features of DIMMs

DIMM first intro.in Intel’s chipsets

(1996) (2004)(2002)(1996)(1995) (2007)


SODIMM


Width (Data)

EDO DDR2DDR

32-bit 64-bit64-bit

EDOFPM DDR3


Present detect PPD (7b) SPDSDPSPDPPD (7b) SPD

Registered option No NoNo No No No

Typ. capacity [MB] 4-64 256–2048128 –10248-64 4-64 512–4096

Figure : Main features of SODIMM modules

Est. year of intro. ~1995 20042002~1996~1994 2007

SDRAM

3.3 V

SPD

No

64-512

1996

64-bit

200-pin


[1]: 64MB Apple G3 Beige 168p SDRAM DIMM, http://www.memoryx.net/apl168s64.html

[2]: 4, 8 MEG x 32 DRAM SIMMs, Micron, http://www.pjrc.com/mp3/simm/datasheet.html

[3]: 168 Pin, PC133 SDRAM Registered DIMM Design Specification, JEDEC Standard No. 21-C, Page 4.20.2

[4]: 184 Pin Unbuffered DDR SDRAM DIMM Family, JEDEC Standard No. 21-C, Page 4.5.10

[5]: Direct Rambus DRAMM RIMM Module, 512 MB, MC-4R512FKE6D, Elpida, http://pdf1.alldatasheet.com/datasheet-pdf/view/60081/ELPIDA/MC-4R512FKE6D.html

[6]: DDR2 SDRAM UDIMM Features, Micron, http://www.micron.com/products/modules/udimm/partlist

[7]: DDR3 SDRAM UDIMM Features, Micron, http://www.micron.com/products/modules/udimm/partlist

[8]: DDR2 SDRAM FBDIMM Features, Micron, http://www.micron.com/products/modules/fbdimm/partlist

[9]: Torres G., „Memory Tutorial”, July 19, 2005, Hardwaresecrets, http://www.hardwaresecrets.com/article/167/1

[10]: Besedin D., „First look at DDR3”, Digit-life, June 29, 2007, http://www.digit-life.com/articles2/mainboard/ddr3-rmma.html

5. References (1)

[11]: http://www.hardwaresecrets.com/fullimage.php?image=2862

5. References (2)

[12]: http://cgi.ebay.com/Vintage-Microsoft-8-Bit-ISA-PC-RAM-Card-W-Gold-5150_ W0QQitemZ310017171151QQcmdZViewItem

[13]: Datasheet, Micron, http://download.micron.com/pdf/datasheets/modules/ddr/ DDF18C64_128x72D.pdf

[14]: Datasheet, Micron, http://download.micron.com/pdf/datasheets/modules/ddr2/ HTF18C64_128_256x72D.pdf

[15]: Datasheet, Micron, http://download.micron.com/pdf/datasheets/modules/ddr3/ JSF18C256x72PD.pdf

[16]: Supermicro Motherboards, http://www.supermicro.com/products/motherboard/

[17]: Definition of CDCV857 PLL Clock Driver for Registered DDR DIMM Applications, JESD82, JEDEC, July 2000

[18]: http://www.tranzistoare.ro/datasheets2/32/327037_1.pdf

[20]: Van Roon T., „What exactly is a PLL?,” April 2006, http://www.uoguelph.ca/~antoon/gadgets/pll/pll.html

[19]: Haskill, „The Love/Hate relationship with DDR SDRAM Controllers,” Mosaid, Oct. 2006, http://www.mosaid.com/corporate/products-services/ip/ SDRAM_Controller_whitepaper_Oct_2006.pdf

[21]: Interfacing to DDR SDRAM with CoolRunner-II CPLDs, Application Note XAPP384, Febr. 2003, XILINC inc.

http://www.uoguelph.ca/~antoon/gadgets/pll/pll.html

http://www.uoguelph.ca/~antoon/gadgets/pll/pll.html

[23]: Tam S., „Single Error Correction and Double Error Detection,”, XILINX Application Note XAP645 (v.2.2), Aug. 2006, http://www.xilinx.com/support/documentation/ application_notes/xapp645.pdf

[24]: DDR SDRAM Registered DIMM Design Specification, JEDEC Standard No. 21-C, Page 4.20.4-1, Jan. 2002, http://www.jedec.org

[25]: Understanding DDR3 Serial Presence Detect (SPD) Table, July 17, 2007, Simmtester, http://www.simmtester.com/PAGE/news/showpubnews.asp?num=153

[26]: DDR2 DIMM SPD Definition, August 25, 2006, http://docmemory.com/page/news/showpubnews.asp?num=141

[27]: Memory Module Serial Presence-Detect, TN-04-42, Micron, 2002 http://download.micron.com/pdf/technotes/TN_04_42_C.pdf

[22]: 64-bit Flow-Thru Error Detection and Correction Unit, IDT49C466, Integrated Device Technology Inc., 1999, http://www.digchip.com/datasheets/parts/ datasheet/222/IDT49C466.php

5. References (5)

[28]: Datasheet, http://download.micron.com/pdf/datasheets/modules/sdram/ SD9C16_32x72.pdf

[29]: Solanki V., „Design Guide Lines for Registered DDR DIMM Module,” Application Note AN37, Pericom, Nov. 2001, http://www.pericom.com/pdf/applications/AN037.pdf

http://www.xilinx.com/support/documentation/

http://www.digchip.com/datasheets/parts/

http://download.micron.com/pdf/datasheets/modules/sdram/

Documents

Dezső Sima September 2008 (Ver. 1.0) Sima Dezső, 2008 5. Synchronous memory modules