DESIGN, VERIFICATION, TESTABILITY AND RELIABILITY OF …jelemenska/prezentaciaUPSS/... · 2012-09-06 · Embedded systems and SoC s using microcontrollers and microprocessors (8051,

DESIGN, VERIFICATION, TESTABILITY AND RELIABILITY

OF DIGITAL SYSTEMS

Institute of Computer Systems and Networks FIIT STU

Director: Dr. Katarína Jelemenskáe-mail: [email protected]

http://www.fiit.stuba.sk

Faculty of Informatics and Information TechnologiesSlovak University of Technology in Bratislava (FIIT STU)

Activities and Benefits in Digital Systems Design

Institute of Computer Systems and Networks FIIT STU in Bratislava, Slovakia

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The presentation is targeted to whom with interest to cooperate with the Facultyof Informatics and Information Technologies of the Slovak University of Technologyin Bratislava – FIIT STU through:

� joint research, development and applied national and international projects,� real digital circuits and systems design based on bi-lateral cooperation,� establishment of a joint design laboratory or centre with a design company,� consultation in the field design and test of digital systems, embedded systems,� organisation of workshops or conferences related to the mentioned fields,� special lectures done by experts from design companies in the selected courses,� leading diploma thesis,� finding and supporting graduated excelent and skilled students .

FIIT STU is prepared to start collaboration with you.

About FIIT STU ─ http://www.fiit.stuba.sk


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FIIT STU – Faculty of Informatics and Information Technologies – the youngest faculty of the Slovak University of Technology.

Location : Ilkovičova 3, 842 16 Bratislava (Mlynská dolina), Slovakia.

FIIT STU is moving into the new building at the begining 2 013.

Opening the New FIIT STU Building

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Opening ceremony in June 2012 – dean of FIIT STU, representatives of Ministry of Education and companies .

New areas for information technologies education, research, development and new laboratories in Bratisl ava.

Where is FIIT STU located?

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FIIT STU – Mlynská dolina is app. 5 km fromthe historical, cultural and shoping centres in Bratisl ava.

How to get to FIIT STU in Bratislava?

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� plane: to Bratislava airport

to Vienna airport – 25 km from Bratislava

� by train: to Bratislava railway station

� Slovakia is situated in the middle of Europe.� Bratislava is located near Vienna (50 km) and Budapest (180 km).� Arriving possibilities by:

� by boat: from Vienna directly to the Bratislava

FIIT STU: Education – Research – Development

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Educ

atio

n Research

Development

� Bc. student program - 3 years and 4 years.

� MSc. student program - 5 years in total.

� PhD. student program – internal (3 years) and external (5 years).

� Bilateral and multilateral projects.

� Student’s thesis – talented students.

� Student’s mobilities within Europe’s R&D.

� Participation and organization of research conferences.

� Cooperation with On Semiconductor Brno.

� CISCO Academy� FUNTORO Lab� NGN Lab� Individual student’s hardware

development oriented projects.Supportin

g theoretica

l knowledge,

practical sk

ills and te

am work.

……the best comes out fr

om us.

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Human Resources

� Staff:� 16 full time professors and associate professors,

� 42 teachers,� 6 research fellows,

� 18 external part time industry lecturers.

� Students:o Approx. 940 full time.


Student – staff ratio: 20 : 1

99,4 % of graduates are successfully deployed in Slovak industry as well as abroad

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FIIT STU graduates unemployment:

0,6%

Universities in Slovakia


COMPUTER AND COMMUNICATION

SYSTEMS AND NETWORKS

INFORMATICS

COMPUTER AND COMMUNICATION

SYSTEMS AND NETWORKS

1st. level Bachelor degree study

2nd. level Master degree study

3rd. level Doctoral degree study

SOFTWARE ENGINEERING

INFORMATION SYSTEMS

SOFTWARE SYSTEMS

APPLIED INFORMATICS

Education

Accredited study programs by IET community, which i s established in Londonhttp://www.theiet.org/academics/accreditation/int-progs.cfm.


Institutes of FIIT STU

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� Design , modeling , simulation, verification and synthesis ofdigital systems – using proffessional CAD tools, VHDL, Verilog , HandelC , SystemC .

� Testability and reliability of digital systems – methods, architectures including DfT and BIST, test standards and JTAG and IEEE 1500 and six sigma.

� Embedded systems and SoCs using microcontrollers and microprocessors (8051, x86, ARM, soft cores Altera, e tc.) – development of methods, algorithms, and advanced embedded systems applications (RTOS).

� Network and communication systems (NGN).

Institute of Applied Informatics

Institute of Informatics and Software Engineering

Institute of Computer Systems and Networks

targeted mainly to software basedtopics, information systems, web services, artificial intelligence, security, etc.

Institute of Computer Systems and NetworksStaff - design and test courses

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� Full staff :� 1 professor� 5 associate professors � 6 PhD staff� 1 researcher� 21 PhD students – in design, testing, verification of digital systems,

embedded systems and their application, as well asadvanced networks (NGN).

Lectures and individual or team student’s work.

Events

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� Organisation of research events :

� Computer systems architectures and diagnostics – workshop for PhD students.

� Student’s conferences at FIIT STU.

� Cooperation in organization of IEEE Design and Diagnostics of Electronic Circuits and Systems.

Our successful PhD. and MSc. students and their presenta tions.

Design Laboratories

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Embedded SystemsFPGA Design

� XILINX ISE WebPack, MODELSIM) for pro-grammable circuits CPLD and FPGA practical teaching.

� ModelSim� FPGA Advantage� Catapult� DK Design Suite� RC 10 FPGA boards� Supported SW.

Digital systems description

This laboratory is oriented to design of embedded systems,microprocessors and interfacing. The students are involved in design, implementation and verification of microprocessors based applications.

This laboratory is for teachingprogrammable logic devices.The students are involved in design, implementation and verification of applications for programmable logic and gate arrays.

This laboratory is predefined for teaching digital systems design, testing, diagnostics, reliability and reconfigurable digital systems. The students are to prove their practical and theoretical skills on digital systems development.

� Hardware development tools� digital oscilloscopes, logic

analyzers, logic probes� in-circuit emulators� Intel Atom and PXA based

embedded system development kits

� Programmable hardware development kits – Xilinx and Altera FPGAs & CPLDs.

Education – courses for digital design

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Msc. Study Programme

Logic circuits

Computer Architectures

Modeling and Simulation

Diagnostics of Digital Systems

Digital Systems Description

Bc. Study Programme

Microcomputers

Peripheral Devices

Programmable Logic

Architectures of Computer Systems

Digital Systems Design

Digital Systems Testing

Embedded Systems

Reconfigurable Digital Systems

Computing Systems Research

System on Chip Design

Reliability of Digital Systems

Application of Embedded Systems

Applicability of our graduates

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Graduated students from FIIT STU (Computers Systems and Networks study programme ) are prepared for

the following job positions:

� Design Manager

� Lead Designers (FPGA, ASIC, SoC)

� System Designer (SoC, Embedded systems)

� Test Engineer – digital systems

� Product Manager

� etc.

Best Awarded Master Thesis 2010 - 2012

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� Synthesis of VHDL from SIMULINK model.

� Asymmetric Hardware Cipher.

� Hardware Encryption With Public-Key Encryption.

� Experimental Embedded System for Remote Monitoring and Regulation Management.

� Reliable Design of Self-Testing and Repairing Memories.

� Visualization of SystemC Model Simulation.

� Detection and Animation of Dynamic Hazards in Combinational Logic Circuits.

� Automatic Test Pattern Generation for Sequential Circuits using ATALANTA.

� Experimental Embedded System for Remote Monitoring and Regulation Management.

� VHDL Digital Systems Model Visualization.

� Modeling and Diagnostics by Petri Nets.

� Modular operating system for embedded systems.

� Passive USB packet acquisition.

Master Thesis Example (1)

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Title: Synthesis of VHDL from SIMULINK model.

Objectives: Development of a new tool for speeding up the design of embedded systems with focus on high performance and reliability based on the FPGA technology.

Outcomes: A new developed tool enables synthesis of the VHDL from model created in the Mathworks Simulink. There are also contemplated different tools for the FPGA synthesis from high-level languages.

Master Thesis Example (2)

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Title: Securing System with Multiple FPGA Based Hardware Watchdogs

Objectives: Development of embedded hardware architecture to provide advanced security for real-time systems.

Outcomes: A securing device with multiple individually configurable hardware watchdog timers providing extra security for each process and the whole secured system.

A new hardware architecture of multiple hardware watchdog device; implemented in FPGA.

Research – current projects related to design

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� VEGA 1008/12 Design optimization of low-power digital and mixed integr atedcircuits (2012 - 2015)

Objectives: to develop methods for optimal design at the system level together withtesting and verification support.

� VEGA 1/1105/11 Robust MPC for hybrid systems (2011 – 2013) Objectives: to research and development, algorithmization and implementation of robustpredictive control methods for non linear hybrid processes realized on embedded computer systems.

� Development of Center of Excellence for Smart Technologies, Systems , and Services II (ITMS 26240120029)Objectives: to design, create, and put into operation the technological infrastructure that enables to operate the Centre of excellence of research and development for enterprise information source processing and presentation with the application of advanced distributed architectures for parallel processing and high performance computing for complex applications.

Selected publications (1)

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� GRAMATOVá, E., JELEMENSKÁ. K.: Testing, Diagnostics and Verification of Digital System s, Vydavateľstvo STU v Bratislave, 2012, 272 p.

� POHRONSKÁ, M. - KRAJČOVIČ, T.: Embedded System Architecture for Real-time Rule-bas ed Reasoning . In: Second Eastern European Regional Conference on the Engineering of Computer Based Systems. Los Alamitos IEEE Computer Society, 2011, pp. 85-91.

� POHRONSKÁ, M. - KRAJČOVIČ, T.: FPGA Implementation of Multiple Hardware Watchdo g Timers for Enhancing Real-Time Systems Security . In: EUROCON 2011. International Conference on Computer as a Tool Joint with CONFTELE 2011, Lisbon, Portugal, Los Alamitos IEEE Computer Society, 2011, pp. 1-4.

� MACKO, D. - JELEMENSKÁ, K.: VHDL Structural Model Visualization. In: EUROCON 20 11. International Conference on Computer as a Tool Joint with CONFTELE 2011, Lisbon, Portugal, IEEE Computer Society, 2011, pp. 1-4.

� JELEMENSKÁ, K. - SIEBERT, M. - MACKO, D. - ČIČÁK, P.: Logic Circuit Design Verification Support Tool - Fit Board . In: Procedia Social and Behavioral Sciences. Vol. 28, No. 1-4 (2011), WCETR – 2011,World Conference on Educational Technology Researches, Near East University, Cyprus Educational Sciences Association, Nicosia / Kyrenia, North Cyprus, ISSN 1877-0428, pp. 305-310.

� HUDEC, J.: An Efficient Technique for Processor Automatic Func tional Test . In: ITI 2011, Proceedings of the 33rd

International Conference on Information Technology Interfaces, Cavtat / Dubrovnik, Croatia, Zagreb University Computing Centre, 2011, pp. 527-532.

� FLOCHOVÁ, J. - HOLLÝ, J. - ZAPATICKÝ, M. - PIVARČEK, J.: Model Based Implementation of Supervisors and Diagnosers in VHDL Code of Programmable Systems . In: EUROCON 2011. International Conference on Computer as a Tool joint with CONFTELE 2011, Lisbon, Portugal, IEEE Computer Society, 2011, pp. 90-92.

Selected publications(2)

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� JURIKOVIČ, M. - ČIČÁK, P. - JELEMENSKÁ, K.: Parallel Controller Design and Synthesis . In: 7th FPGA world Conference, Copenhagen, Denmark, Academic Proceedings2010, Copenhagen, FPGAworld, 2010, pp. 35-40.

� TUROŇ, J. - JELEMENSKÁ, K.: Contribution to Graphical Representation of SystemC Structural Model Simulation . In: 7th FPGAworld Conference, Copenhagen, Denmark, Copenhagen FPGAworld, 2010, pp. 42-48.

� JURIKOVIČ, M.: Hierarchical Petri Net for Parallel Controller Desi gn and Synthesis . In: Student Research Conference 2010, Vol. 2, 6th Student Research Conference in Informatics and Information Technologies Bratislava, 2010, Supervisor: P. Čičák, pp. 357-364.

� MACKO, D.: Development of Visualization Environment for Suppor ting the Digital System Design . In: Student Research Conference 2010, Vol. 2, 6th Student Research Conference in Informatics and Information Technologies Bratislava, 2010, Supervisor: K. Jelemenská, pp. 419-426.

� MÁNIK, M. - GRAMATOVÁ, E.: Efficient Diagnostics Algorithms for Regular Comput ing Structures .In: Proceedings of the 2011 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2011 pp. 87-91

� POHRONSKÁ, M.: Methods for Implementing Expert Systems in Embedded and Real Time Systems . In: Student Research Conference 2010, Vol. 2, 6th Student Research Conference in Informatics and Information Technologies Bratislava, 2010, Supervisor: T. Krajčovič, pp. 373-380.

� POHRONSKÁ, M. - KRAJČOVIČ, T.: Embedded System Architecture for Real-time Rule-bas ed Reasoning .In: Second Eastern European Regional Conference on the Engineering of Computer Based Systems, 2011, pp. 85-91.

� KRIŠTOFÍK, Š., GRAMATOVÁ, E.: Repair Analysis For Embedded Memories Using Block-Based Re dundancyArchitecture , Proceedings of ICCSE 2012, Londýn, 6. 7. 2012.

Current PhD Thesis

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� Design methods for asynchronous digital circuits (1 PhD student, 2011 – 2014)

� Binary decision diagrams in optimization of multiplexer tree designs

(1 PhD student, 2010 – 2013)

� Verification methods based on in-house specification language for digital design

(2 PhD students, 2010 – 2013, 2011 – 2014).

� Methods and architectures for built-in self test RAM memories

(1 PhD student, 2011 – 2014).

� Functional testing of microprocessors (1 PhD student, 2010 – 2013).

� Algorithms and methods for delay faults testing of digital circuits

(1 PhD student, 2012 – 2015).

� Development methods and architectures of embedded systems for automotive applications (2 PhD students, 2011 – 2014, 2012 – 2015).

� Modular operating systems for embedded platforms (1 PhD student, 2012 – 2015).

Current PhD Thesis

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� Design methods for asynchronous digital circuits (1 PhD student, 2011 – 2014)

� Binary decision diagrams in optimization of multiplexer tree designs

(1 PhD student, 2010 – 2013)

� Verification methods based on in-house specification language for digital design

(2 PhD students, 2010 – 2013, 2011 – 2014).

� Methods and architectures for built-in self test RAM memories

(1 PhD student, 2011 – 2014).

� Functional testing of microprocessors (1 PhD student, 2010 – 2013).

� Algorithms and methods for delay faults testing of digital circuits

(1 PhD student, 2012 – 2015).

� Development methods and architectures of embedded systems for automotive applications (2 PhD students, 2011 – 2014, 2012 – 2015).

� Modular operating systems for embedded platforms (1 PhD student, 2012 – 2015).

PhD Thesis Example (1)

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Title: Implementation of Embedded Expert Systems via Programmable Hardware

Objectives: Analyse the capability of employing a programmable hardware to design expert systems. Develop a method for building embedded expert systems.

Outcomes: Proposal of two methods of FPGA based hardware acceleration of inference mechanism for expert reasoning; definition of a method for embedded expert systems implementation.

Design of a complex development toolchainfor implementing embedded expert systems via programmable hardware.

PhD Thesis Example (2)

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Title : Test Generation for Asynchronous Sequential Circuits

Objectives: to develop and implement a new test pattern generator for asynchronous sequential circuits.

Outcomes: The new effective TPG for asynchronous sequential circuits -TACKLESS has been realised for generating deterministic test sequences. The system identifies hazards before the test generation.

A new fault simulator has been developed for speeding up TPG process.

The results were tested over some benchmarks and compared with the existing ATPG tools.

Our Mission and Vision

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� To become the leading national institution in infomatics and informationtechnologies research and development including digital and embeddedsystems architectures and design and their effective application.

� To become an internationally recognized research and development orientedinstitution with hands on collaboration with leading companies .

� To establish modern laboratories and development centers in a close cooperation with leaders in order to further increase the industry and business experience of our graduates.

� To enable our graduates to work on practical product design and development effort in Slovakia most notably in the area of the design of microprocessor architectures, systems and their appl ications .

Documents

DESIGN, VERIFICATION, TESTABILITY AND RELIABILITY OF …jelemenska/prezentaciaUPSS/... · 2012-09-06 · Embedded systems and SoC s using microcontrollers and microprocessors (8051,