Design of the Front-end Electronics for the GOSSIPO

chip.

Vladimir Gromov

Electronics Technology

NIKHEF, Amsterdam,

the NetherlandsCERN, July the 22th, 2005

Highlights. • Main functionalities of the GOSSIPO.

• Main objectives and principal block diagram of the prototype of the chip .

• Evaluation of the parasitic capacitances at the input of the charge-sensitive preamplifier.

• Injection of the input test signal.

• Design and performance of the charge-sensitive preamplifier.

• Design and performance of the current comparator and output LVDS driver.

• Design and performance of the bias circuit.

• Conclusion and plans.

The GOSSIPO chip.(Gas On Slimmed Silicon Pixel)

Cluster3

Cathode (drift) plane

Micromegas

Cluster2 Cluster1

Silicon wafer with read-out electronics on itInput pixel

1mm,400Volts

50um, 400Volts

20um

10 0 10 20 30 400.15

0.1

0.05

00

0.13

s t( )

4010 t

electron component, Qe=10%

ion component, Qi =90%

0 10 20 30 time,ns

Input current,

nA

Shape of the current signal coming on the pixel pad

The Input signal.

0 5000 1 104

1.5 104

2 104

2.5 104

3 104

0

10

20

30

34

0

P n 2000( ) 32

P n 4000( ) 32

P n 8000( ) 32

n

Twalkjt 1

Tw n( )

300000 n n n 448 Twalkjt 0 448 nSignal, electronsTHR=350e

Gain=8000

Gain=4000

Gain=2000

Time-walk curve

Time-walk vs pulse height distribution

Main features of the GOSSIPO chip. 1. There will no silicon sensor on the chip due to a novel concept of the particle detection that allows

to circumvent major constrains related to that.

2. Low input parasitic capacitance and no need for the detector leakage current compensation at the input are the reasons to expect an outstanding performance of the design.

Objectives for the prototype.

Testing of the performance and the functionality of the Front-end electronics on the bare chip (without InGrid and with InGrid on it).

The design is expected to demonstrate:

a) low-threshold operation (THR=350e).

b) fast pulse response (δ-response peaking time ≈ 36ns , real signal response peaking time ≈ 52ns ).

c) low analog power dissipation (≈ 1.7uW/channel for 1.2V supply).

d) low channel-to-channel threshold dispersion (σTHR ≈140e).

e) low parasitic feedback cross-talk.

Principal block diagram of the GOSSIPO front-end circuit.

Cfb ≈ 1fF

Rfb ≈ 80MΩ

Cpar ≈ 30fFIdet(t)

Cc ≈ 200fF

Vref

Ithr=42nARl ≈ 1kΩRl ≈ 1kΩ

Charge sensitive preamplifier Current Comparator

with DC hysteresis LVDS driver

Bias generator

Channel#1

Channel#2

Channel#3

Channel#4

Cfb ≈ 1fF

Rfb ≈ 80MΩ

Cpar ≈ 30fFIdet(t)

Charge sensitive preamplifier

Voltage follower

Out

puts

Channel#5

Bia

s co

ntro

l

Ron ≈ 2GΩ

Voltage-to-currentconverter

Parasitic capacitances associated with the input pad.

noise peaking time

charge collection

Micromegas

Input pad

Substrate of the wafer

Cp-grid Cp-gridCp-grid

Cp-sub Cp-sub

Cp-p Cp-p

Cpar = Cp-grid + Cp-p + Cp-sub , where Cp-sub is pad-to-substrate capacitance coupling

Cp-grid is pad-to-Micromegas capacitance coupling

Cp-p is pad-to-pad capacitance coupling .

Evaluation of the pad-to-Micromegas parasitic capacitances Cp-grid.

C R d( )2 3.14 0

0

d

z

0

1

rrz

z2 r2 R2

3

2

d d

0 5 106

1 105

1.5 105

2 105

2.5 105

0

0.5

1

1.5

2

2.5

C R 25 106

C R 50 106

C R 75 106

R

C=1.8fF whenR=25um, d=50um

R - is a radius of the pad. The pad is a circle. d - is pad-to-Micromegas distance.0 - is vacuum dielectric constant.

D

Ideal boundless plane

Ideal uniformly charged disk

R

Model for analytical calculations of the pad-to-Micromegas parasitic capacitance.

0 5 10

61 10

51.5 10

52 10

52.5 10

50

5

10

15

20

25

3030

0.86

C R 6 106

C1barek

C2barek

3 1055 10

6 R rk

Evaluation of the pad-to-substrate parasitic capacitances Cp-sub in 0.13um CMOS technology.

≈ 6um

Substrate

RInput pad (LM, copper 0.55um)

MQ, copper 0.55um

M6, copper 0.32um

M5, copper 0.32um

M4, copper 0.32umM3, copper 0.32um

M2, copper 0.32um

M1, copper 0.29umPC

Via 2x2, 0.8um x 0.8um

0 5 10 15 20 25 R , um

Extraction done by DIVA with CDS_coeffgen_Cap

option

Extraction done by DIVA with Raphael_Cap option

Analytical calculation

Cp-sub=27fF R=25um,

Layout of the input pad coupling in0.13um CMOS technology (CMOS8SF, flavour LM 6_2).

30

25

20Cp-sub

15fF

10

5

0

Capacitive parasitics based on the physical design of the layout have been extracted within DIVA Extract rules supplied in the Design Kit. Both available methodologies (CDS_coeffgen_Cap and Raphael_Cap) have been used. Suggested Diva Deck Extraction Methodology (from the PDK User’s guide) - generate a trial test structure which mimic possible design geometries as much as possible. - run extraction tool for both methodologies.- review the capacitance numbers and use the tool that gives the more pessimistic results. Compare the numbers to hand calculations or a 3D field solver.

0 5 106

1 105

1.5 105

2 105

0

0.5

1

1.5

2

2.5

32.9

0

C1 ak

30 106

Crap30x30k1

Ccoeff30x30k1

22 1060 10

6 ak

a1k1

a1k1

Evaluation of the pad-to-pad parasitic capacitances Cp-p in 0.13um CMOS technology.

Model for analytical calculations of the pad-to-pad parasitic capacitance.

Cp_p a b( )4 3.14 0 r

2 10 10

a

2z

0.5

0.5

xz

z2 x2 b2

3

2

d d

ab

bInput pad

Cp-p

Input pad

c=0.55um

where b is dimension of the pad, c is thickness of the pad, a is pad-to-pad distance, ε0 is vacuum dielectric constant, εr is relative permittivity of the medium

Pad-to-pad layout

0 5 10 15 20 a ,um

Analytical calculation on the basis of the model.

Extraction done by DIVA with Raphael_Cap option

Extraction done by DIVA with CDS_coeffgen_Cap

option

Evaluation of the input pad-to-pad capacitances in 0.13um CMOS technology (CMOS8SF, flavour LM 6_2). Large pads (b=30um)

2.5

2Cp-p

1.5fF

1

0.5

0

Injection of the input test signal.

Cpar

* = Cpar + Cin , therefore Cin<< Cpar= 30fF

Cfb ≈ 1fF

Rfb ≈ 80MΩ

Cpar ≈ 30fFUpulse(t)

Charge sensitive preamplifier

Rt=50Ω Cin ≈ 3fF

Uin ≈ 20mV Qin=Cin Uin≈ 0.06fC (350e)

Vertical Parallel Plate (VPP) capacitor in LM layer.

Cfringe=3.2fF

Active pad

d=550um

a=1800nm

40um

Test input

!!! Accuracy of the fringe capacitors. !!! Accuracy of the fringe capacitors. Δa=50nm, Δa/a=3% (lithography accuracy) Δa=50nm, Δa/a=3% (lithography accuracy)

±± 25% 25% Δd=± Δd=±140140nm, Δd/d=±nm, Δd/d=± 25% (LM layer thickness accuracy)25% (LM layer thickness accuracy)

Passive pad

Passive pad

The charge-sensitive preamplifier. The feedback capacitance.

1. Charge sensitivity: Uamplitude ≈ Qdet / Cfb

2. Charge collection (input impedance)

Cin *= A Cfb ≈ 140fF

Cin *>> Cpar ≈ 30fF

Cfb ≈ 1fF

Rfb ≈ 80MΩ

Cpar ≈ 30fFIdet(t)

Qdet

U(t)

A≈140

Coaxial-like layout of the input interconnection. Extraction with the parasitics.

Input pad

Substrate

Cfb = 1fF

C** = 0.5fF

Cp-sub = 23fF

40um40um

0.18um

0.2um

C**

≈ 0.5fF

!!! Accuracy of the fringe !!! Accuracy of the fringe

capacitor is capacitor is ±± 25% 25%(metal layers accuracy)(metal layers accuracy)

The charge-sensitive preamplifier. The feedback resistor. Cfb ≈ 1fF

Rfb ≈ 80MΩ

Cpar ≈ 30fFIdet(t)Δtdet ≈ 30ns

Qdet

U(t)

A≈140

1. To avoid ballistic deficit: Rfb Cfb > Δtdet=30nsRfb > 30MΩ

Cfb

2Ip

Output

Silicon sensor

CintIpIleak + Ip

Ileak

Classic F.Krummenacher charge sensitive preamplifier realizes large Rfb and compensates for the detector leakage current.

!!! Cint → ∞ in order to avoid differentiation of the input signal.

Cfb

OutputInput

There is no need to compensate for the detector leakage in GOSSIPO chip.

!!! Cint is not needed in this preamplifier and Ip=Ib. Rfb ≈ 1/gmM1+1/gmM2 ≈ 80MΩ ,where gm is

common-source transconductance of transistor.

M1 M2Ib=1nA Ib=1nA

Ip=Ib=1nA

The charge-sensitive preamplifier. Channel-to-channel variation of the DC offset at the output.

Cfb =1fF

K=127

Vbias1

Vbias2

Ibias2=2nA

Vdd=1.2V

OutputInput

Ibias4=1uA

Ibias3=0.2uA

M1 M2

M3

M5

M7 M6

M4

OPAMP

A (jw)

Vbias3

Ibias3=1nA

M8M9

M10UoutDC varies from channel to channel. Three source of mismatch are in the design:

1. Mismatch in the diffrential pair M1 vs M2 σ(δVg)=√2•[(σT

M1 )

2 +(σβ

M1•IdM1/gmM1)2] ≈ √2•σTM1

2. Mismatch in the current mirrors M10 vs M8,M9 σ[IdM8+ IdM9- IdM10]- /[IdM8+ IdM9]=[(σβ

M10 )

2 +(σ T

M10•gmM10/IdM10)2] ≈

σ TM10 • gmM10/IdM10

3. Mismatch in the current mirrors M5 vs M4 σ(δIdM5/IdM5)=√ 2•[(σβ

M5 )

2 +(σ T

M5•gmM5/IdM5)2] ≈ √ 2•gmM5/IdM5•σ TM5

Standard deviation of the statistical variations of UoutDC

σ(δUoutDC)=√ (√2•σTM1)2 + (2•√2• σ T

M5•gmM5/gmM1)2 + (σ TM10•gmM10/gmM1)2

Monte-Carlo simulations in Cadence give σ(δUoutDC) = 20mV (170e) .

Ib=1nA

The charge-sensitive preamplifier. The OPAMP.

Cfb ≈ 1fF

Rfb ≈ 80MΩ

Cpar ≈ 30fFIdet(t)

Qdet

U(t)

OPAMP

The OPAMP.A(jw)=gmT75/[gdsT75•(gdsT73/gmT73)+gdsT77+jwC*]

=140/(1+jw•14ns) gm is common-source transconductance of transistor.

gds is common-source output conductance of transistorC* is total parasitic capacitance at the output.

The charge-sensitive preamplifier. Real signal response and stability.

Magnitude-to-frequency response

Phase-to-frequency response

Unity gain line

Phase margin

62º

Phase margin of the preamplifier.

Cfb ≈ 1fF

Rfb ≈ 80MΩ

Cpar ≈ 30fFIdet(t)

Qdet

U(t)

OPAMP

Input signal 438e = 70aC

Output signal

Peaking time44ns

Amplitude 52mV

30ns

Decay of the signal is proportional to exp(-t/80ns)

Real signal response of the preamplifier.

The charge-sensitive preamplifier. Main specifications.

Table1.

R 0um 15um 20um 25um

Cpar 0fF 10fF 20fF 30fF

Gain 140mV/ke 130mV/ke 125 mV/ke 120 mV/ke

Nsim 34e RMS 43e RMS 57e RMS 71e RMS

Ncal 4.5e RMS 21e RMS 35e RMS 46e RMS

Tpint 20ns 27ns 32ns 36ns

Tpreal 41ns 46ns 50ns 52ns

δUDC σ ≈ 170e

P 1.2uW/channel for 1.2V supply

Cfb ≈ 1fF

Rfb ≈ 80MΩ

Cpar ≈ 30fFIdet(t)

Qdet

U(t)

OPAMP

Radius of the input pad

Parasitic capacitance at the input of the preamplifier

Charge sensitivity

Input referred noise (Affirma SPECTRE simulation)

Input referred noise (hand calculation of serial thermal noise )

Peaking time of the output signal when it is a δ-response.

Peaking time of the output signal when it is the responseto the real signal

Power dissipation

Channel-to-channel variation of the DC offset at the output.

Uout+

Uout-

-A

Ithr

Iin

Uout+ - Uout-

Iin - Ithr

T1

T2

VtT2=200mV

Ambiguity zone ± 30nA !!!± 30nA !!!

Low

VtT1=200mV

High

Low

High

Conversion to digital signal. Current comparator.(H.Traff 1992).

Design of the Current comparator as a current-to-voltage converter.

Uout+

Uout-

Iin

Vt=200mVgm=1.6u

Vt=200mVgm=1.6u

Vt=400mV

T1

T2

T3

T4 VbiasVt=200mV

33

130nA

Gainopen loop = gmT3 / gdsT3 = 53 (High state) = 18 (Low state)

Degradation of the output impedance of T3 in Low state causes drop of the open loop gain.

UDC=300mV

Zin

Freg,10MHz

High state. Iin = 60nA

500kΩ

40kΩ

14kΩ

Low state. Iin = - 60nA

Ambiguity state. Iin = 0nA.

Zin=1/ [Zin=1/ [gmgmT1,T2 T1,T2 • • GainGainopenopen looploop]]

Interface to the Current comparator. Design of the ac-coupled voltage-to-current converter.

Charge sensitive Preamplifier is a

Current-to-voltage converter

Voltage-to-currentconverter

Current Comparatoris

a current-to-voltage converter

voltage current

M1 M2

Vbias1

Vbias2

Vbias3

Iout

Uin

Ibias1=200nA

Cc=200fF

Ithr=42nA

1. Differentiation time constant of the AC-coupling: Cc • Ron = 200usec >> signal duration time.

2. Gain = Iout/Uin = 0.5• gmT1 = 90nA/52mV (438e).

3. Channel-to-channel Gain variation: σ(δGain/Gain) = 10% (44e).

4. Output impedance = 1/ gdsT3 = 100 MΩ.

5. Channel-to-channel variation of the output DC current: σ(δIoutDC) = 24nA (120e).

M3

LVDSDriver

Ron=1GΩM4

Design of the complete comparator with DC hysteresis.

Vbias1

Vbias2

Vbias3

Iout

Uin

Ithr=42nA

Uout+

Uout-

Vbias

33

130nA

UDC=300mV

Charge sensitive Preamplifier is a

Current-to-voltage converter

Voltage-to-currentconverter

Current Comparatoris

a current-to-voltage converter

voltage currentLVDS

Driver voltage

Ithr=15nA

Hysteresis or positive feedback allows to avoid too short pulses and double pulses at the output of the comparator.

U(THRup )-U(THRdown) = 15nA(73e) σnoise= 0.2 • U(THRup) = 75e

THRup

THRdown

≈ σnoise

Design of the LVDS output driver.

Charge sensitive Preamplifier is a

Current-to-voltage converter

Voltage-to-currentconverter

Current Comparatoris

a current-to-voltage converter

voltage currentLVDS

Driver voltage voltage

Ibias=21uA

Rl=7kΩ R2=7kΩ

Uin+

Uin-

Ibias=85uA

R3=1kΩR4=1kΩ

Uout-

Uout+

ΔU= 100mV

The Low Voltage Differential Driver (LVDS) delivers the digital signals to the external low

impedance load.

Cpar ≈ 8pF

ΔU= 55mV

Cpar ≈ 8pF

The signals in the design .

Time-walk at the output of the LVDS driver as a function of the signal amplitude (Amp).

Threshold = 350e.

Input current signalcoming from pixel pad

Output of the preamplifier

Output of the current comparator.

Output of the LVDS driver.

Threshold

ΔT=45ns

Amp=350e

Amp=438e

Amp=900e

Amp=1800e

Amp=9000e

Design of the bias circuit.

Controldetermines current

(voltage drop over R1).

Cncap = 10fF (11fF/um2 )

Ron=1GΩ W/L=0.16u/24uVgs=38mWVthr=250mV

A filter is needed to suppress common bus noise. A 1th order low-pass filter with cut-off frequencyfcut-off= 1/[2π • Ron • Cncap] = 16kHz

Vgs=38mWR1

Channel-to-channel spread of the output impedances T1…T4 is given as follows:

σ(δ(gds)/gds)= σ(δVt) /[n•Φt ] ≈ 15%

T1

T2

T3

T4

Conclusion and plans.. There will be no silicon sensor on the GOSSIPO chip due to a novel concept of the particle detection

that allows to circumvent major constrains related to that.

. Low input parasitic capacitance and no need for the detector leakage current compensation at the input are the reasons to expect an outstanding performance of the design.

. Design of the GOSSIPO chip is in progress on the basis of the potentialities of the 0.13um CMOS . The following specification have been found feasible so far:

a) parasitic input capacitance 10fF….30fF.

b) input referred electronic noise σnoise = 70e (corresponds to THR=350e).

c) δ-response peaking time ≈ 36ns , real signal response peaking time ≈ 52ns .

d) analog power dissipation ≈ 1.7uW/channel for 1.2V supply (without LVDS driver).

e) channel-to-channel threshold dispersion σTHR ≈140e.

. There will be 4 individual channels on the chip. Each channel will be equipped with a charge-sensitive preamplifier ac-coupled to a current comparator with DC hysteresis and a LVDS driver.

. Vertical Parallel Plate (VPP) or fringe capacitor seems to be suitable for injection of the test signal. The VPP-based capacitance is taken to implement the feedback capacitance in the preamplifier.

. A dedicated circuit on the chip will provide all the channels with bias voltages (currents).

. Low-pass filters have been added to each channel to avoid common bus noise.

. We look to submit this prototype within CERN organized MPW run in December 2005.