DESIGN GUIDE Carrier Board - VIA Technologies, Inc.cdn.viaembedded.com/products/docs/som-6x50/design_guide/DG_C… · DESIGN GUIDE Carrier Board for SOM-6X50 Module 1.01-08232018-160700

DESIGN GUIDE

Carrier Board for SOM-6X50 Module

1.01-08232018-160700

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Carrier Board Design Guide for SOM-6X50 Module

Revision History

Revision Date Description1.00 02/09/2018 Initial release1.01 08/23/2018 Modified caption description of figure 44

Updated signal names in tables 5, 39 and 40Fixed typo errors in tables 15-17, 19-20, 35 and 41Changed the fonts color of the table of contents, list of figures and list of tables

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Table of Contents

1. Introduction ....................................................................................................................... 11.1 Document Overview ............................................................................................................................. 11.2 Acronyms Used ..................................................................................................................................... 21.3 SchematicConventions ........................................................................................................................ 3

2. GeneralCarrierBoardRecommendations ........................................................................ 42.1 PCB Stackup .......................................................................................................................................... 4

2.1.1 4-Layer PCB Stackup Example ........................................................................................................ 52.1.2 4-Layer PCB Impedance Control .................................................................................................... 5

2.2 GeneralLayoutandRoutingGuidelines ............................................................................................... 62.2.1 RoutingStylesandTopology .......................................................................................................... 62.2.2 GeneralTraceAttributeRecommendation .................................................................................... 72.2.3 GeneralClockRoutingConsiderations ........................................................................................... 8

3. SOM-6X50ModuleandSOMDDR3SODIMMSlotSpecificationOverview ....................... 93.1 SOM-6X50 Module Placement ............................................................................................................ 93.2 SOM-6X50ModuleMechanicalCharacteristics ................................................................................... 93.3 SOM-6X50 Module and Carrier Board Dimensions ............................................................................ 103.4 SOM DDR3 SODIMM Slot ................................................................................................................... 11

3.4.1 SOM DDR3 SODIMM Slot Dimensions ........................................................................................ 113.4.2 SOM DDR3 SODIMM Slot Footprint ............................................................................................. 12

3.5 SOMDDR3SODIMMSlotPinAssignments ........................................................................................ 13

4. LayoutandRoutingRecommendation............................................................................. 164.1 HDMI Interface ................................................................................................................................... 16

4.1.1 HDMISignalDefinition ................................................................................................................. 164.1.2 HDMILayoutandRoutingRecommendations ............................................................................. 174.1.3 HDMIReferenceSchematics ........................................................................................................ 19

4.2 Ethernet Interface .............................................................................................................................. 204.2.1 EthernetSignalDefinition ............................................................................................................ 204.2.2 EthernetLayoutandRoutingRecommendations ........................................................................ 214.2.3 EthernetReferenceSchematics ................................................................................................... 22

4.3 USB Interface ...................................................................................................................................... 234.3.1 USBSignalDefinition ................................................................................................................... 234.3.2 USBLayoutandRoutingRecommendations ................................................................................ 244.3.3 USBReferenceSchematics ........................................................................................................... 26

4.4 COM and UART Interface .................................................................................................................... 274.4.1 COMandUARTSignalDefinition ................................................................................................. 274.4.2 COMandUARTLayoutandRoutingRecommendations ............................................................. 284.4.3 COMandUARTReferenceSchematics ........................................................................................ 29

4.5 LCD Interface ...................................................................................................................................... 304.5.1 LCDSignalDefinition .................................................................................................................... 304.5.2 LCDLayoutandRoutingRecommendations ................................................................................ 314.5.3 LCDReferenceSchematics ........................................................................................................... 32

4.6 Touch Panel Interface ......................................................................................................................... 334.6.1 TouchPanelSignalDefinition ....................................................................................................... 334.6.2 TouchPanelLayoutandRoutingRecommendations ................................................................... 344.6.3 TouchPanelReferenceSchematics .............................................................................................. 35

4.7 GPIO Interface .................................................................................................................................... 364.7.1 GPIOSignalDefinition .................................................................................................................. 364.7.2 GPIOLayoutandRoutingRecommendation ................................................................................ 36

4.8 I²C Interface ........................................................................................................................................ 374.8.1 I²CSignalDefinition ..................................................................................................................... 374.8.2 I²CLayoutandRoutingRecommendation ................................................................................... 37

4.9 SPI Interface ....................................................................................................................................... 38

iv


v

4.9.1 SPISignalDefinition ..................................................................................................................... 384.9.2 SPILayoutandRoutingRecommendation ................................................................................... 38

4.10 Audio Interface ................................................................................................................................... 394.10.1 AudioSignalDefinition ................................................................................................................ 394.10.2 AudioLayoutandRoutingRecommendations ............................................................................. 394.10.3 AudioInterfaceReferenceSchematics ........................................................................................ 40

4.11 SD Interface ........................................................................................................................................ 424.11.1 SDSignalDefinition ...................................................................................................................... 424.11.2 SDLayoutandRoutingRecommendations .................................................................................. 424.11.3 SDInterfaceReferenceSchematics .............................................................................................. 43

Appendix A.SOMDB1CarrierBoardReferenceSchematics ................................................... 44


ListofFiguresFigure1: Schematicconventions......................................................................................................................... 3Figure2: MicrostripPCBstackupexample .......................................................................................................... 4Figure3: StriplinePCBstackupexample ............................................................................................................. 4Figure4: 4-LayerPCBboardstackupdetail ......................................................................................................... 5Figure5: Point-to-pointandmulti-dropexamples ............................................................................................. 6Figure6: Daisy-chainexample ............................................................................................................................. 6Figure7: Alternatemulti-dropexample .............................................................................................................. 6Figure8: Signaltracewidthandspacingexample .............................................................................................. 7Figure9: Differentialsignaltracewidthandspacingexample ............................................................................ 7Figure10: Suggestedclocktracespacing .............................................................................................................. 8Figure11: Clocktracelayoutinrelationtothegroundplane ............................................................................... 8Figure12: Seriesterminationformultipleclockloads .......................................................................................... 8Figure13: SOM-6X50moduleplacementexampleonthecarrierboard ............................................................. 9Figure14: CarrierboardwithSOM-6X50module(sideview) .............................................................................. 9Figure15: CarrierboardandSOM-6X50moduleheightdistribution(sideview) ................................................. 9Figure16: DimensionsoftheSOM-6X50module ............................................................................................... 10Figure17: Dimensionsofthereferencecarrierboard ........................................................................................ 10Figure18: DimensionsoftheSOMDDR3SODIMMslot(topview) .................................................................... 11Figure19: DimensionsoftheSOMDDR3SODIMMslot(sideview) ................................................................... 11Figure20: PCBfootprintoftheSOMDDR3SODIMMslot .................................................................................. 12Figure21: PCBfootprintoftheSOMDDR3SODIMMslotwithSOM-6X50module ........................................... 12Figure22: SOMDDR3SODIMMslotschematics ................................................................................................. 15Figure23: HDMIroutingtopology ...................................................................................................................... 16Figure24: HDMIdifferentialtracewidthandspacingexample .......................................................................... 17Figure25: HDMIsingle-endedtracewidthandspacingexample ....................................................................... 17Figure26: HDMIreferencecircuitry .................................................................................................................... 19Figure27: Ethernetroutingtopology .................................................................................................................. 20Figure28: Ethernetsingle-endedtracewidthandspacingexample .................................................................. 21Figure29: Ethernetdifferentialtracewidthandspacingexample ..................................................................... 21Figure30: Ethernetreferencecircuitry ............................................................................................................... 22Figure31: USBroutingtopology ......................................................................................................................... 23Figure32: USBdifferentialsignalroutingexample ............................................................................................. 24Figure33: USBdifferentialtracewidthandspacingexample ............................................................................. 24Figure34: USBhostreferencecircuitry ............................................................................................................... 26Figure35: USBclientreferencecircuitry ............................................................................................................. 26Figure36: COMandUARTroutingtopology ....................................................................................................... 28Figure37: COMandUARTreferencecircuitry .................................................................................................... 29Figure38: LCDroutingtopology.......................................................................................................................... 31Figure39: LCDreferencecircuitry ....................................................................................................................... 32Figure40: Touchpanelroutingtopology ............................................................................................................ 34Figure41: Touchpanelreferencecircuitry .......................................................................................................... 35Figure42: Line-in1&2referencecircuitry ......................................................................................................... 40Figure43: Headphonereferencecircuitry .......................................................................................................... 40Figure44: Monospeakeroutreferencecircuitry ................................................................................................ 40Figure45: Rightchannelspeakerreferencecircuitry .......................................................................................... 41Figure46: Leftchannelspeakerreferencecircuitry ............................................................................................ 41Figure47: Onboardmicrophonereferencecircuitry........................................................................................... 41Figure48: SDroutingtopology ........................................................................................................................... 42Figure49: SDreferencecircuitry ......................................................................................................................... 43

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List of TablesTable1: Acronymsused ..................................................................................................................................... 2Table2: 4-LayerPCBimpedancecontrol ........................................................................................................... 5Table3: Recommendedtracewidthandspacing .............................................................................................. 7Table4: SOMDDR3SODIMMslotsample ....................................................................................................... 11Table5: SOMDDR3SODIMMslotpinouts ...................................................................................................... 14Table6: HDMIsignaldefinition ........................................................................................................................ 16Table7: HDMItraceproperties ....................................................................................................................... 17Table8: HDMIlayoutguidelines ...................................................................................................................... 18Table9: HDMIroutingtopologyandsignaltype ............................................................................................. 18Table10: Ethernetsignaldefinition ................................................................................................................... 20Table11: Ethernettraceproperties ................................................................................................................... 22Table12: Ethernetlayoutguidelines ................................................................................................................. 22Table13: Ethernetreferenceplane,signaltypeandroutingtopology ............................................................. 22Table14: USBsignaldefinition .......................................................................................................................... 23Table15: USBtraceproperties .......................................................................................................................... 25Table16: USBterminationoption,signaltypeandroutingtopology ................................................................ 25Table17: USBlayoutguidelines ......................................................................................................................... 25Table18: COMandUARTsignaldefinition ........................................................................................................ 27Table19: COMandUARTtraceproperties ........................................................................................................ 28Table20: COMandUARTtopology,signaltypeandlayoutguidelines .............................................................. 29Table21: LCDsignaldefinition ........................................................................................................................... 30Table22: LCDtraceproperties........................................................................................................................... 31Table23: LCDsignaltype,topologyandreferenceplane .................................................................................. 31Table24: LCDlayoutguidelines ......................................................................................................................... 32Table25: Touchpanelsignaldefinition ............................................................................................................. 33Table26: Touchpaneltraceproperties ............................................................................................................. 34Table27: Touchpanelsignaltype,routingtopologyandreferenceplane ........................................................ 34Table28: Touchpanellayoutguidelines ............................................................................................................ 34Table29: GPIOsignaldefinition ......................................................................................................................... 36Table30: GPIOtraceproperties ......................................................................................................................... 36Table31: GPIOsignaltype,topologyandlayoutguidelines .............................................................................. 36Table32: I²Csignaldefinition ............................................................................................................................ 37Table33: I²Ctraceproperties ............................................................................................................................ 37Table34: I²Csignaltype,topologyandlayoutguidelines .................................................................................. 37Table35: SPIsignaldefinition ............................................................................................................................ 38Table36: SPItraceproperties ............................................................................................................................ 38Table37: SPIsignaltype,topologyandlayoutguidelines ................................................................................. 38Table38: Audiosignaldefinition ....................................................................................................................... 39Table39: Audiotraceproperties ....................................................................................................................... 39Table40: Audiosignaltype,topologyandlayoutguidelines ............................................................................. 40Table41: SDsignaldefinition ............................................................................................................................. 42Table42: SDtraceproperties ............................................................................................................................ 43Table43: SDsignaltype,topologyandlayoutguidelines .................................................................................. 43

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1

1. IntroductionThisdocumentprovidesdesignguidelinesandrulerecommendationsforthedevelopersofacarrierboardthatsupportsthefeaturesoftheVIASOM-6X50module.Thisdocumentincludesthelayoutandroutingguidelinesforgeneralboarddesignsandmajorunderlyinginterfaces(e.g.HDMI,Ethernet,USB).Inaddition,thedocumentincludestheplacementandmechanicalinformationontheSOMDDR3SODIMMslotwhichisusedtoprovidehigh-speedinterfacesbetweenthecarrierboardandthemodule.

Pleasenotethatthisdocumentisconsideredtobeareferenceguideonly.Thisdocumentisnotintendedtobeaspecification.Allinformationandexampleslistedbelowareconsideredtobeaccurateasofthepublicationdate.However,developersmustbeawarethatthisdocumentisonlyareferenceguide.

1.1 Document OverviewAbriefdescriptionofeachchapterisgivenbelow.

Chapter 1: IntroductionThischapterbrieflyintroducesthestructureofthedesignguidedocument.

Chapter 2: General Carrier Board RecommendationsThegeneraldesignschemesandrecommendedlayoutrulesareshowninthischapter.

Chapter 3: SOM-6X50 Module and SOM DDR3 SODIMM Slot Specification OverviewDetailedinformationabouttheSOM-6X50moduleandSOMDDR3SODIMMslotplacementanddimensionsare described in this chapter.

Chapter 4: Layout and Routing RecommendationsDetailedlayoutandroutingguidelinesforeachmajorinterfacearedescribedinthischapter.

Appendix A: Carrier Board Reference SchematicsReferenceschematicsoftheSOMDB1evaluationcarrierboard.


2

1.2 Acronyms Used

Table1:Acronyms used

Term DescriptionASIC Application-specificIntegratedCircuitDDR Double Data RateEMI ElectromagneticInterferenceESD Electrostatic-discharge

GPIO General Purpose Input/OutputHDMI High-DefinitionMultimediaInterface

I²C Inter-ICIC IntegratedCircuit

LCD Liquid-Crystal DisplayLVDS Low-VoltageDifferentialSignalingP2P Point-to-PointPCB Printed Circuit BoardRGB Red,GreenandBlue

RJ-45 RegisteredJack45RS-232 Recommend Standard number 232

SD SecureDigitalSODIMM Small Outline Dual In-line Memory Module

SMT SurfaceMountTechnology

SOM System-On-ModuleSPI Serial Peripheral Interface

UART UniversalAsynchronousReceiver-TransmitterUSB Universal Serial Bus

USB OTG USB On-The-Go


3

1.3 SchematicConventionsThereferenceschematicsdepictedinthisdocumentshowthedirectionalflowofthesignals.Directionalflowisindicated by the pointed ends of the arrow shapes.

Figure1:Schematicconventions

Bidireconal signal flow

IC/Connector

Input signal flow

Output signal flow


4

2. General Carrier Board Recommendations ThissectioncontainsgeneralguidelinesforthePCBstackupandthelayoutoftraces.Thegeneralguidelinesforroutingstyle,topology,andtraceattributerecommendationsarealsodiscussed.

2.1 PCB StackupThePCBstackupconsistsofsignallayersandreferencelayers(powerandground).Thesignallayersarereferredtoasthecomponentlayer(top),innerlayerandsolderlayer(bottom).

ThecarrierboarddesignerscanchoosebetweentwobasiccategoriesofPCBstackupdesign:microstripandstripline.Themicrostripdesignshavetheoutersignallayersexposed.Thestriplinedesignshavetheoutermostsignallayersshieldedbyreferencelayers.

Thefollowingfiguresshowanexampleofmicrostripandstriplinedesigns.

.

Figure2:Microstrip PCB stackup example

Figure3:Stripline PCB stackup example

Thechoiceofmicrostriporstriplinedesigndependsontheapplicationforwhichthecarrierboardisbeingdesigned.IfthecarrierboardisbeingdesignedforlocationswheresensitivitytoEMIisanissue,astriplinedesignisrecommendedforreducingEMIandnoisecoupling.ForapplicationswherethetoleranceforEMIlevelsisgreater,amicrostripdesignisrecommendedtoreducecosts.DuetotheinherentnatureofstriplinePCBstacks,broad-sidecouplingispossible.

Microstrip stackup design

Signal layers

Reference layers

Component layer

Ground layer

Inner layer

Power layer

Ground layer

Solder layer

Stripline stackup design

Signal layers

Reference layers

Component layer

Ground layer

Inner layer

Power layer

Ground layer

Solder layer


5

2.1.1 4-Layer PCB Stackup ExampleThefollowingfigureshowstherecommended4-layerPCBstackupdesignforthecarrierboardoftheSOM-6X50 module.

Figure4:4-Layer PCB board stackup detail

2.1.2 4-Layer PCB Impedance Control

Table2: 4-Layer PCB impedance control

± 10%40Ω

Single-end50Ω

Single-end55Ω

Single-end85Ω

Differential90Ω

Differential90Ω

Differential

Layer 1 12mil 8mil 7mil7.8:9:7.8

mil7.6:8:7.6

mil7:7.5:7

mil

Layer 4 12mil 8mil 7mil7.8:9:7.8

mil7.6:8:7.6

mil7:7.5:7

mil

TOP = 1.0oz (1.46mil)

GROUND = 1.0oz (1.18mil)

POWER =1.0oz (1.18mil)

BOTTOM = 1.0 oz (1.46mil)

PP (Er) = 4.76mil

Core (Er) = 44.88mil

PP (Er) = 4.76mil

Soldermask = 0.79mil

Pla ng = 0.8mil

Soldermask = 0.79mil

Pla ng = 0.8mil

LAYER 1

LAYER 2

LAYER 3

LAYER 4

61.68mil

Copper foil + Plang

Copper foil

Copper foil

Copper foil + Plang


6

2.2 GeneralLayoutandRoutingGuidelinesThissectionprovidesgenerallayoutrulesandroutingguidelinesfordesigningcarrierboardsofSOM-6X50module.

2.2.1 RoutingStylesandTopologyTopologyisthephysicalconnectivityofanetoragroupofnets.Therearetwotypesoftopologiesforacarrierboardlayout:point-to-point(P2P)andmulti-drop.AnexampleofthesetopologiesisshowninFigure5.

Figure5:Point-to-pointandmulti-dropexamples

High-speedbussignalsaresensitivetotransmissionlinestubs,whichcanresultinringingontherisingedgecausedbythehighimpedanceoftheoutputbufferinthehighstate.Inordertomaintainbettersignalquality,transmissionstubsshouldbekeptasshortaspossible(lessthan1.5”).Therefore,daisychainstyleroutingisstronglyrecommendedforthesesignals.Figure6belowshowsanexampleofdaisychainrouting.

Figure6:Daisy-chain example

Ifdaisychainroutingisnotallowedinsomecircumstances,differentroutingsmaybeconsidered.AnalternativetopologyisshowninFigure7.Inthiscase,thebranchpointissomewherebetweenbothends.Itmaybenearthesourceorneartheloads,butbeingclosetotheloadsideisbest.Theseparatedtracesshouldbeequalinlength.

Figure7:Alternatemulti-dropexample


7

2.2.2 GeneralTraceAttributeRecommendationA5miltracewidthand10milspacingaregenerallyadvisedformostsignaltracesonacarrierboardlayout.Toreduce trace inductance the minimum power trace width is recommended to be 30mil.

Asaquickreference,theoverallrecommendedtracewidthandspacingfordifferenttracetypesarelistedinTable3,andtherecommendedtracewidthandspacingforeachsignalgroupisshowninChapter4.

Table3:Recommendedtracewidthandspacing

Generalrulesforminimizingcrosstalkinhigh-speedbusdesignsarelistedbelow:

• Maximize the distance between traces. Maintain 10mil minimum spaces between traces wherever possible.

•Maximizethedistance(30milminimum)betweentwoadjacentroutingareasofdifferentsignalgroups wherever possible.

•Avoidparallelismbetweentracesonadjacentlayers.

•Providestablereferenceplanesforallhigh-speedsignals.

•Neverroutehigh-speedsignalsoversplitsintheirperspectivereferenceplanes.

•Selectaboardstack-upthatminimizescouplingbetweenadjacenttraces.

Figure8:Signaltracewidthandspacingexample

Figure9:Differentialsignaltracewidthandspacingexample

Notes:1.W:Tracewidth2.S:Thespacingtoothertraces3.S1:Differentialpairspacing

Trace Type Trace Width (mil) Spacing (mil)RegularSignal 5 or wider 10 or widerInterfaceorBusReferenceVoltageSignal 20 or wider 20 or widerPower 30 or wider 20 or wider

S1S S

Reference Plane

W W

Signal Signal

S

Reference Plane

WS

Signal


8

2.2.3 GeneralClockRoutingConsiderationsTheclockroutingguidelinesarelistedbelow:

• The recommended clock trace width is 5mil.

•Theminimumspacebetweenoneclocktraceandadjacentclocktracesis20mil.Theminimumspace fromonesegmentofaclocktracetoothersegmentsofthesameclocktraceisatleasttwotimesof theclockwidth.Thatis,morespaceisneededfromoneclocktracetoothersoritsowntracetoavoid signalcoupling(seeFigure10).

•Theclocktracesshouldbeparalleltotheirreferencegroundplanes.Thatis,aclocktraceshouldberight beneathorontopofitsreferencegroundplane(seeFigure11).

•Theseriesterminations(dampingresistors)areneededforallclocksignals(typically0Ωto47Ω).When twoloadsaredrivenbyoneclocksignal,theseriesterminationlayoutisshowninFigure12.When multipleloads(morethantwo)areapplied,aclockbuffersolutionispreferred.

•Isolatingclocksynthesizerpowerandgroundplanesthroughferritebeadsornarrowchannels(typically 20milto50milwide)ispreferred.

• No clock traces on the internal layer if a six-layer board is used.

Figure10:Suggestedclocktracespacing

Figure11:Clocktracelayoutinrelationtothegroundplane

Figure12:Seriesterminationformultipleclockloads


9

3. SOM-6X50 Module and SOM DDR3 SODIMM Slot Specification Overview3.1 SOM-6X50 Module Placement ThefollowingfigureshowsthedepictionofthetopviewofthecarrierboardPCB(SOMDB1)withtheappropriate amount of space reserved for the SOM-6X50 module.

Figure13:SOM-6X50 module placement example on the carrier board

3.2 SOM-6X50ModuleMechanicalCharacteristics

Figure14:CarrierboardwithSOM-6X50module(sideview)

Figure15:CarrierboardandSOM-6X50moduleheightdistribution(sideview)

Carrier board

44.3mm

67.6mm

48mm

O 2mm

Carrier board PCB

SOM DDR3 SODIMM slotVIA SOM-6X50 module

Standoff spacer

Screw

6.5mm 1.8mm

53mm

1.3mm

2.5mm


10

3.3 SOM-6X50 Module and Carrier Board DimensionsThefollowingfiguresshowthemechanicaldimensionsoftheSOM-6X50moduleandthereferencecarrierboard(SOMDB1).

Figure16:Dimensions of the SOM-6X50 module

Figure17:Dimensions of the reference carrier board

SOMDB1VTS8666C

152.4mm

160mm

26mm

100mm

77mm 42mm41mm

3.8mm

O 4mm 3.8mm

92.4mm

44.3mm

67.6mm

48mm

O 2mm

21mm 39mm

20mm


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3.4 SOM DDR3 SODIMM SlotTheSOMDDR3SODIMMslotcanhandlehigh-speedsignalsandcomprises204pinstoconnecttheSOM-6X50module.Table4showsthespecificationsampleoftheSOMDDR3SODIMMslot.

Table4:SOM DDR3 SODIMM slot sample

3.4.1 SOM DDR3 SODIMM Slot Dimensions

Figure18:DimensionsoftheSOMDDR3SODIMMslot(topview)

Figure19:DimensionsoftheSOMDDR3SODIMMslot(sideview)

Part Number Description Height Vendor

40-40024-02 DDR3 SODIMM 5.2H 1.5V STD PLASTIC LATCH ASSEMBLY 5.2mm Deren

41.95mm±0.15

3.70mm3.70mm

71.1mm

64.7mm

21mm39mm3mm

1.35mm0.6mm0.6mm

0.15mm

21mm39mm3mm

1.35mm

41.35mm 23.35mm23.95mm±0.15

67.90mm±0.15

0.45mm

23.0

5mm

±0.2

0

25.8

5mm

±0.1

5

3mm

5.20mm

0.80mm

5mm

12mm

17.15mm9.80mm

0.60mm

5mm

1.06mm±0.04

0.25mm0.05mm +0.1

-0.05204 PIN CONTRACT

1.16mm REF.0.28mm +0.1

-0.05

SOM-6X50 module

Slot


12

3.4.2 SOM DDR3 SODIMM Slot Footprint

Figure20:PCB footprint of the SOM DDR3 SODIMM slot

Figure21:PCB footprint of the SOM DDR3 SODIMM slot with SOM-6X50 module

Pin # 204

39mm

3mm

21mm

Pin # 2

0.60mm (Pitch)

12mm

4.1mm

4.1mm

Ø1.10mm±0.05 (Hole)

Pin # 1

39mm

Pin # 203 3mm

21mm

0.35mm±0.03

Ø1.60mm±0.05 (Hole)

2mm±0.03

4.60mm±0.10 (2X)

3.50mm±0.10 (2X)

Carrier board PCB


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3.5 SOMDDR3SODIMMSlotPinAssignmentsThe SOM DDR3 SODIMM slot consists of 204 pins. The pinouts of the SOM DDR3 SODIMM slot are shown below.

Pin Signal Pin Signal1 USBATTA0 2 GND3 USBID0 4 nUSBH2+5 USBSW0 6 nUSBH2-7 GND 8 GND9 SPI0MISO 10 nUSBH1+

11 SPI0MOSI 12 nUSBH1-13 SPI0CLK 14 GND15 SPI0SS0- 16 nUSBHD0+17 GND 18 nUSBHD0-19 SD0CLK 20 GND21 SD0DATA1 22 UARTB_CTS23 SD0WP 24 UARTB_RTS25 SD0DATA0 26 UARTB_RX27 SD0CMD 28 UARTB_TX29 SD0DATA2 30 UARTA_CTS31 SD0DATA3 32 UARTA_RTS33 SD0PWRSW 34 UARTA_RX35 SD0CD 36 UARTA_TX37 M0_LINK 38 UARTC_RTS39 M0_SPEED 40 UARTC_RX41 PWMOUT0 42 UARTC_TX43 PWMOUT1 44 UARTC_CTS45 GND 46 UARTD_RTS47 NET_RX- 48 UARTD_CTS49 NET_RX+ 50 UARTD_TX51 GND 52 UARTD_RX53 NET_TX- 54 VDHSYNC55 NET_TX+ 56 VDVSYNC57 GND 58 VDDEN59 nHDMIHPD 60 VDCLK61 nHDMICEC 62 VDOUT063 nHDMIDDCSDA 64 VDOUT865 nHDMIDDCSCL 66 VDOUT167 GND 68 VDOUT1069 nLCD1DO3+ 70 VDOUT371 nLCD1DO3- 72 VDOUT273 GND 74 VDOUT575 nLCD1CLK+ 76 VDOUT477 nLCD1CLK- 78 VDOUT6

Pin Signal Pin Signal79 GND 80 VDOUT1381 nLCD1DO0+ 82 VDOUT983 nLCD1DO0- 84 VDOUT785 GND 86 VDOUT1587 nLCD1D01+ 88 VDOUT1189 nLCD1DO1- 90 VDOUT1291 GND 92 VDOUT1993 nLCD1DO2+ 94 VDOUT1495 nLCD1DO2- 96 VDOUT1897 GND 98 VDOUT1799 VDIN0 100 VDOUT20

101 VDIN1 102 VDOUT21103 VDIN2 104 VDOUT16105 VDIN4 106 VDOUT23107 VDIN3 108 VDOUT22109 VCLK 110 UART1RXD111 GND 112 UART1TXD113 VDIN6 114 UART1RTS115 C24MOUT 116 UART1CTS117 VDIN5 118 UART0RXD119 VDIN7 120 UART0TXD121 VVSYNC 122 SD3CMD123 VHSYNC 124 SD3CLK125 GPIO12 126 SD3DATA0127 GPIO13 128 SD3DATA3129 GND 130 SD3DATA2131 SPK_OUT_R- 132 SD3DATA1133 SPK_OUT_R+ 134 SD3PWRSW135 GND 136 SD3WP137 SPK_OUT_L- 138 I2CSDA139 SPK_OUT_L+ 140 I2C1SCL141 GND 142 I2C2SCL143 HPOUTR 144 I2C2SDA145 OUT3 146 I2C3SDA147 HPOUTL 148 I2C3SCL149 MICBIAS 150 SUS_GPIO0151 GND 152 PWRGD153 LINPUT3 154 WAKEUP0155 LINPUT2 156 SPI1MOSI


14

Table5:SOM DDR3 SODIMM slot pinouts

Pin Signal Pin Signal157 LINPUT1 158 GND159 GND 160 SPI1CLK161 RINPUT1 162 SPI1SS0-163 RINPUT2 164 SPI1MISO165 GND 166 GPIO1167 WAKEUP3 168 GPIO0169 PWRENVCC 170 GPIO6171 WAKEUP2 172 GPIO3173 CIRIN 174 GPIO4175 PWRENMEM 176 GPIO5177 PWRENVDD 178 GPIO9179 SUS_GPIO1 180 GPIO7181 PWRBTN- 182 GPIO8183 RSMRST- 184 VSUS33185 PWMOUT3 186 VSUS33187 PWMOUT2 188 VCC33189 PWREN_MAIN 190 VCC33191 VCC-BAT 192 VCC33193 NC 194 NC195 5VIN 196 GND197 5VIN 198 GND199 5VIN 200 GND201 5VIN 202 GND203 5VIN 204 GND


15

Figure22:SOMDDR3SODIMMslotschematics


16

4. Layout and Routing RecommendationTheinformationpresentedinthischapterincludesthesignaldefinition,topology,layoutandroutingguidelinesforeachbusinterface,andreferenceschematicsexample.Theinformationprovidedisintendedfordesigningcarrier boards that are compliant with the SOM-6X50 module.

4.1 HDMI InterfaceTheSOM-6X50modulefeaturesoneHDMIinterface.TheHDMIinterfaceusesfourcontrolsignals,onedifferentialclock,andthreedifferentialdatapairsignalsthatcarryvideoandaudiosignals.

4.1.1 HDMISignalDefinitionThefollowingtableprovidesthedefinitionoftheHDMIsignalsthatareimplementedintheSOMDDR3SODIMM slot.

Table6:HDMIsignaldefinition

Figure23:HDMIroutingtopology

Note:TheEMIfiltersandESDcomponentsmustbeplacedneartheHDMIport.

Signal Name Pin # I/O DescriptionnHDMID0+ 81

O HDMIdifferentialpairlineslane0nHDMID0- 83nHDMID1+ 87

O HDMIdifferentialpairlineslane1nHDMID1- 89

nHDMID2+ 93O HDMIdifferentialpairlineslane2

nHDMID2- 95nHDMICLK+ 75

O HDMIdifferentialpairclocklinesnHDMICLK- 77nHDMIDDCSCL 65 IO HDMI DDC SCLnHDMIDDCSDA 63 IO HDMI DDC SDAnHDMICEC 61 O HDMI consumer electronics connectornHDMIHPD 59 O HDMIhotplugdetect

L1L1

L1L1

L1

L1

L2

L2

SOM DDR3SODIMM Slot

HDMI port

EMI filter1 2

4 3

ESD

1 2

4 3

ESD

1 2

4 3

ESD

1 2

4 3

ESD

SOM-6X50

Edge

fing

er

L2

L2

L2

L2

L2

L2

L2

L2

nHDMID0+

nHDMID0-

nHDMID2+

nHDMIDDCSCL

nHDMIDDCSDA

nHDMICLK-

nHDMICLK+

nHDMID2-

nHDMID1-

nHDMID1+

ESD

ESD

L2

L2nHDMIHPD

nHDMICEC

N-ChannelDigital FET

L1

L1Route Differenally

L1


L1


L1



17

4.1.2 HDMILayoutandRoutingRecommendations•Tracelengthsshouldbekepttoaminimum.

•Eachtraceofdifferentialpairsshouldnothavemorethantwoviaholes.

•Eachdifferentialpairssignalshouldroutetoparalleltoeachotherwiththesametracelength.

•Differentialpairshouldbeallreferencedtoground.

•Routethedifferentialpairsonasinglelayeradjacenttoagroundplane.

•Thespacingbetweenthedifferentialpairsignalandothersignalsshouldbeatleastthreetimesthetrace width.

Figure24:HDMIdifferentialtracewidthandspacingexample

Figure25:HDMIsingle-endedtracewidthandspacingexample

Table7:HDMItraceproperties

HDMI SignalDifferenal Pair

S1S S

Reference Plane

W W

S

Reference Plane

WS

HDMI SignalSingle-ended

Signal Group Signal Name Trace Impedance

Trace & Spacing (mil)(S : W : S1 : W : S)

Pair to Pair Trace Mismatch

Spacing to Other Signal

Data

nHDMID0+

100Ω±15%(Differential)

15:5:7:5:15<5mil

(Differential)15mil

nHDMID0-nHDMID1+nHDMID1-nHDMID2+nHDMID2-

ClocknHDMICLK+ 100Ω±15%

(Differential)15:5:7:5:15 <5mil

(Differential) 15milnHDMICLK-

Control

nHDMIDDCSCL

50Ω±15%5:10(W:S)

6mil 10milnHDMIDDCSDAnHDMICECnHDMIHPD


18

Table8:HDMIlayoutguidelines

Table9:HDMIroutingtopologyandsignaltype

Signal Group Signal Name Routing LayerAccumulated Trace Length (L1+ L2 = LT)

Length Difference (mil)

To Clock In Group

Data

nHDMID0+

Top/Bottom LT < 3" <500 <1000


ClocknHDMICLK+

Top/Bottom LT < 3" <500 <1000nHDMICLK-

Control

nHDMIDDCSCL

Top/Bottom LT < 3" <500 <1000nHDMIDDCSDAnHDMICECnHDMIHPD

Signal Group Signal Name Reference Plane Routing Topology Signal Type

Data

nHDMID0+

Ground Point-to-Point DifferentialPairs


ClocknHDMICLK+

Ground Point-to-Point DifferentialPairsnHDMICLK-

Control

nHDMIDDCSCL

Ground Point-to-Point Single-endednHDMIDDCSDAnHDMICECnHDMIHPD


19

4.1.3 HDMIReferenceSchematics

Figure26:HDMI reference circuitry


20

4.2 Ethernet InterfaceTheSOM-6X50modulefeaturesoneEthernet(10/100Mbps)interface.TheEthernetinterfaceconsistsoftwodifferentialdatasignalsandtwocontrolsignalsforactivitylinkandspeedindicators.

4.2.1 EthernetSignalDefinitionThefollowingtableprovidesthedefinitionoftheEthernetsignalsthatareimplementedintheSOMDDR3SODIMM slot.

Table10: Ethernetsignaldefinition

Figure27:Ethernetroutingtopology

Note:ThemagneticmodulehastobeplacedascloseaspossibletotheRJ-45port.Thedistancemustbelessthan1".

Signal Name Pin # I/O DescriptionNET_TX+ 55

O EthernetdifferentialpairlinesTransmitNET_TX- 53NET_RX+ 49

O EthernetdifferentialpairlinesReceiveNET_RX- 47

M0_SPEED 39 O Ethernet controller 0 100Mbps speed indicatorM0_LINK 37 O Ethernet controller 0 100Mbps link indicator

SOM DDR3SODIMM Slot

RJ-45 port SOM-6X50

Edge

fing

er

L1

L1

L1

L1

LT

LT

L2

L2

L2

L2

NET_TX+

NET_TX-

M0_SPEED

M0_LINK

NET_RX-

NET_RX+

Magnec module (Transformer)

Route Differenally

Route Differenally


21

4.2.2 EthernetLayoutandRoutingRecommendations•Routedifferentialpairsclosetogetherandawayfromothersignals.

•Routeanyothertraceparalleltooneofthedifferentialtrace.

•Keeptracelengthwithineachdifferentialpairequal.

•Keepproperimpedancebetweentwotraceswithinadifferentialpair.


•Thespacingbetweenthedifferentialpairsignalandothersignalsshouldbeatleastthreetimesthetrace width.

•Eachdifferentialpairofsignalsisrequiredtobeparalleltoeachotherwiththesametracelength (Tolerance±50mil)onthecomponent(top)layerandtobeparalleltoarespectivegroundplane. Thelengthdifferencebetweentheshortestandlongestpairsshouldbelessthan200mil.

•TheaccumulatedtracelengthofthedifferentialsignalspairbetweentheSOMDDR3SODIMMslotand magneticmoduleshouldbelessthan1".

•TheaccumulatedtracelengthofthedifferentialsignalspairbetweenthemagneticmoduleandRJ-45 connectorshouldbelessthan1".Isolategroundplaneandconnecttochassis.

•Keepeachdifferentialpaironthesameplane.

•Topreventanynoisefrominjectingintothedifferentialpairs,besuretokeepdigitalsignalsorother signalsawayfromthedifferentialsignals.

•TheexternalmagneticmoduleshouldbeplacedclosetotheRJ-45connectortolimitEMIemissions.

Figure28:Ethernetsingle-endedtracewidthandspacingexample

Figure29:Ethernetdifferentialtracewidthandspacingexample

.

S

Reference Plane

WS

Ethernet Signal Single-ended

Ethernet SignalDifferenal Pair

S1S S

Reference Plane

W W


22

Table11: Ethernettraceproperties

Table12: Ethernetlayoutguidelines

Table13: Ethernetreferenceplane,signaltypeandroutingtopology

4.2.3 EthernetReferenceSchematics

Figure30:Ethernet reference circuitry





Data

NET_TX+

100Ω±15%(Differential)

10:10:5:10:10 50mil 10milNET_TX-NET_RX+NET_RX-

ControlM0_SPEED

55Ω±15% 5:10 - 10milM0_LINK

Signal Group Signal Name Routing LayerAccumulated Trace Length(L1+ L2 = LT)


To Clock

Data

NET_TX+

Top/Bottom LT < 3" <1500NET_TX-NET_RX+NET_RX-

ControlM0_SPEED

Top/Bottom LT < 3" <1500M0_LINK

Signal Group Signal Name Reference Plane Signal Type Routing Topology

Data

NET_TX+

Ground/Power DifferentialPairs Point-to-PointNET_TX-NET_RX+NET_RX-

ControlM0_SPEED

Ground/Power Single-ended Point-to-PointM0_LINK


23

4.3 USB InterfaceThe SOM-6X50 module features three USB 2.0 interfaces. Two of the three USB interfaces can only be used as ahost.Theotherinterfacecanbeconfiguredtobeusedaseitherthehostorclient.TheUSBinterfacesignalsusethreebi-directionaldifferentialdatapairs.

4.3.1 USBSignalDefinitionThefollowingtableprovidesthedefinitionoftheUSBsignalsthatareimplementedintheSOMDDR3SODIMMslot.

Table14: USBsignaldefinition

Figure31:USBroutingtopology

Signal Name Pin # I/O DescriptionnUSBHD0+ 16

IOOTGUniversalSerialBusport0,data+

nUSBHD0- 18 OTGUniversalSerialBusport0,data-nUSBHD1+ 10

IOUniversalSerialBusport1,data+

nUSBHD1- 12 UniversalSerialBusport1,data-

nUSBHD2+ 4IO

UniversalSerialBusport2,data+nUSBHD2- 6 UniversalSerialBusport2,data-USBATTA0 1 I UniversalSerialBusdeviceattachdetectUSBID0 3 I Port ID pinUSBSW0 5 I Universal Serial Bus power control pin

L2

L2

L2

L2

L2

L2

L1L1

L1L1

L1L1

L1L1

L1L1

L1L1

SOM DDR3SODIMM Slot

USB port 1

EMI filter1 2

4 3

ESD

1 2

4 3

ESD

1 2

4 3

ESD

SOM-6X50

Edge

fing

er

nUSBH1+

nUSBH1-

nUSBHD0+

USBID0

USBSW0

USBATTA0

nUSBHD0-

nUSBH2-

nUSBH2+USB port 2

USB port 3 (Micro USB)

USB Overcurrent Protector IC

R

R

VSUS

R

VCC

R

R


24

4.3.2 USBLayoutandRoutingRecommendations•Thedifferentialpairsignalsshouldbeallreferencedtoground.


•Differentialpairrouteinparallelandinequallength.

•TheamountofviasandcornersusedfortheUSBsignallayoutshouldbeminimized;thisistopreventtheoccurrenceofreflectionandimpedancechanges.

•EachpairofUSBdatalinesisrequiredtobeparalleltoeachotherwiththesametracelength,andnot parallelwithothersignalstominimizecrosstalk.

•Separatethesignaltracesintosimilargroupsandroutesimilarsignaltracestogether.Inaddition,itisrecommendedtohavedifferentialpairsroutedtogetheronthecarrierboard.

•Controltracesignalsimpedanceshouldmaintain55Ω±10%.

•FortheUSBtraces,donotroutethemunderoscillators,crystals,clocksynthesizers,magneticdevicesorIC’swhichcouldbeusingduplicateclocks.

TheroutingexamplefortwopairsofUSBdatabusesisshowninFigure32.

Figure32:USBdifferentialsignalroutingexample

Figure33:USBdifferentialtracewidthandspacingexample

SOM DDR3SODIMM Slot

nUSBH1+

nUSBH1-

nUSBH1-

nUSBH1+

Recommended

USB port

USB port

Not recommended

S1W W

USB Signal Differenal Pair

S S

Reference Plane

S1W W

S


25

Table15: USBtraceproperties

Table16: USBterminationoption,signaltypeandroutingtopology

Table17: USBlayoutguidelines





Data

nUSBH1+

90Ω±15% 20:7:7.5:7:20 100mil 20mil

nUSBH1-nUSBH2+nUSBH2-nUSBHD0+nUSBHD0-

ControlUSBATTA0

55Ω±10% 5:10 - 10milUSBID0USBSW0

Signal Group Signal Name Termination Option Signal Type Topology

Data

Port 1nUSBH1+

90Ω DifferentialDataPairs Point-to-Point

nUSBH1-

Port 2nUSBH2+nUSBH2-

Port 3nUSBHD0+nUSBHD0-

ControlUSBATTA0

60Ω - Point-to-PointUSBID0USBSW0

Signal Group Signal Name Routing LayerLength Difference

(In Pair)

Accumulated Trace Length(L1+ L2 = LT)

Data

Port 1nUSBH1+

Top/Bottom <100mil LT < 12"

nUSBH1-

Port 2nUSBH2+nUSBH2-

Port 3nUSBHD0+nUSBHD0-

ControlUSBATTA0

Top/Bottom - LT < 12"USBID0USBSW0


26

4.3.3 USBReferenceSchematics

Figure34:USB host reference circuitry

TheUSBportmodecanbecontrolledbythesignalUSBID0.Inthereferencecircuitryexamplebelow,theUSBID0signalisreferencedtogroundthatmakestheUSBportmodeasclientUSB(orUSBOTGport).

Figure35:USB client reference circuitry


27

4.4 COM and UART InterfaceTheSOM-6X50modulefeaturesCOMandUARTinterfacesthatenabletheinterfacingoffourCOMortwoUARTonthecarrierboard.ThefourCOMinterfacesareusedforRS-232serialcommunicationsandthetwoUARTcanbeusedforTX/RX,RTS,CTSanddebuggingTX/RX.

4.4.1 COMandUARTSignalDefinitionThefollowingtableprovidesthedefinitionoftheCOMandUARTsignalsthatareimplementedintheSOMDDR3 SODIMM slot.

Table18: COMandUARTsignaldefinition

Signal Name Pin # I/O DescriptionUARTA_TX 36 O UART Port-A transmit dataUARTA_RX 34 I UART Port-A receive dataUARTA_RTS 32 O UART Port-A request to sendUARTA_CTS 30 I UART Port-A clear to send

UARTB_TX 28 O UART Port-B transmit dataUARTB_RX 26 I UART Port-B receive dataUARTB_RTS 24 O UART Port-B request to sendUARTB_CTS 22 I UART Port-B clear to sendUARTC_TX 42 O UART Port-C transmit dataUARTC_RX 40 I UART Port-C receive dataUARTC_RTS 38 O UART Port-C request to sendUARTC_CTS 44 I UART Port-C clear to sendUARTD_TX 50 O UART Port-D transmit dataUARTD_RX 52 I UART Port-D receive dataUARTD_RTS 46 O UART Port-D request to sendUARTD_CTS 48 I UART Port-D clear to sendUART1TXD 112 O UART Port-1 transmit dataUART1RXD 110 I UART Port-1 receive dataUART1CTS 116 O UART Port-1 clear to sendUART1RTS 114 I UART Port-1 request to sendUART0TXD 120 O UART Port-0 transmit dataUART0RXD 118 I UART Port-0 receive data


28

Figure36:COMandUARTroutingtopology

4.4.2 COMandUARTLayoutandRoutingRecommendations•Thetransmitandreceivedatatracesignalsshouldberoutedinparallelandinequallength.

•TheamountofviasandcornersusedfortheCOMandUARTsignallayoutshouldbeminimized;thisisto preventtheoccurrenceofreflectionandimpedancechanges.

•Controltracesignalsimpedanceshouldmaintain55Ω±10%.

Table19: COMandUARTtraceproperties

L4L3L2L1

L4L3L2L1

L4L3L2L1

L4L3L2L1

ESD

L2

L2COM port 1

L4

L4

L3

L3

L1

L1

L4L3L2L1

L2

L2COM port 2

L4

L4

L3

L3

L1

L1

ESD UARTpin header 1

ESD

L2

L2COM port 3

L4

L4

L3

L3

L1

L1

L2

L2COM port 4

L4

L4

L3

L3

L1

L1

ESD UARTpin header 2

SOM DDR3SODIMM Slot

SOM-6X50

Edge

fing

er

UARTA_TX

UARTA_RTS

UARTA_RX

UARTA_CTS

UARTB_TX

UARTB_RTS

UARTB_RX

UARTB_CTS

UARTD_TX

UARTD_RTS

UARTD_RX

UARTD_CTS

UARTC_TX

UARTC_RTS

UARTC_RX

UARTC_CTS

L4L3L2L1

L4L3L2L1

L4L3L2L1

Tranceiver IC

Tranceiver IC

Tranceiver IC

Tranceiver IC

Signal Group Signal NameTrace (mil)

(Width:Spacing)Trace Impedance Spacing in Other Group

Data

UART[D:A]_TX

5:5 55Ω±10% 5milUART[D:A]_RXUART[1:0]TXDUART[1:0]RXD

Control

UART[D:A]_CTS

5:5 55Ω±10% 5milUART[D:A]_RTSUART1CTSUART1RTS


29

Table20: COMandUARTtopology,signaltypeandlayoutguidelines

4.4.3 COMandUARTReferenceSchematics

Figure37:COM and UART reference circuitry

Signal Group Signal Name Signal Type Topology Reference Plane

Accumulated Trace Length

(L1 + L2 + L3 + L4 = LT)

Data

UART[D:A]_TX

Single-ended Point-to-Point Ground/Power <10"UART[D:A]_RXUART[1:0]TXDUART[1:0]RXD

Control

UART[D:A]_CTS

Single-ended Point-to-Point Ground/Power <10"UART[D:A]_RTSUART1CTSUART1RTS


30

4.5 LCD InterfaceTheSOM-6X50modulefeaturesone(RGB)LCDinterface.TheLCDinterfaceisaparallelbussignalprovidedforinterfacingtheLCDconnectorforLVDSLCDdisplayasthemaindisplayinterface.TheLCDinterfaceisasingle-channel that supports 18-bit and 24-bit interfaces.

4.5.1 LCDSignalDefinitionThefollowingtableprovidesthedefinitionoftheLCDsignalsthatareimplementedintheSOMDDR3SODIMMslot.

.

Table21: LCDsignaldefinition

Signal Name Pin # I/O DescriptionVDOUT0 62 O

BlueLCDdatasignal

VDOUT1 66 O

VDOUT2 72 OVDOUT3 70 O

VDOUT4 76 OVDOUT5 74 OVDOUT6 78 OVDOUT7 84 OVDOUT8 64 O

GreenLCDdatasignal

VDOUT9 82 OVDOUT10 68 OVDOUT11 88 OVDOUT12 90 OVDOUT13 80 OVDOUT14 94 OVDOUT15 86 OVDOUT16 104 O

RedLCDdatasignal

VDOUT17 98 OVDOUT18 96 OVDOUT19 92 OVDOUT20 100 OVDOUT21 102 OVDOUT22 108 OVDOUT23 106 OVDHSYNC 54 O LCD Line Horizontal SyncVDVSYNC 56 O LCDFrameVerticalSyncVDDEN 58 O LCD Data EnableVDCLK 60 O LCD Clock


31

Figure38:LCDroutingtopology

4.5.2 LCDLayoutandRoutingRecommendations•RGBdatasignaltracesshouldbedesignedtobeasshortaspossible.

•InordertomaximizethenoiserejectioncharacteristicsoftheRGBvideooutputs,itisthen recommendedtoroutetheRGBvideooutputsonthetoplayeroverasolidgroundplane.

•TheroutingfortheRGBsignalsshouldbeassimilaraspossible(i.e.,sameroutinglayer,samenumber ofvias,sameroutinglengthandsamebends).

•RoutetheRGBdatatracesignalsandtwosyncsignals(VDHSYNCandVDVSYNC)asasingle-endedsignal withatraceimpedanceof55Ω.

Table22: LCDtraceproperties

Table23: LCDsignaltype,topologyandreferenceplane

LCD connector

RRS

R

SOM DDR3SODIMM Slot

SOM-6X50

Edge

fing

er

VDOUT23:0]

VDDEN

VDHSYNC

VDSYNC

VDCLK

C

LCD panel

LT

LT

LT

LT

LT


Trace (mil)(Width : Spacing)

Trace Mismatch Spacing to Other Signal

DataVDOUT[7:0]

55Ω±10% 5:10 1000mil 10milVDOUT[15:8]VDOUT[23:16]

ControlVDHSYNC

55Ω±10% 5:10 1000mil 10milVDVSYNC

Clock VDCLK 55Ω±10% 5:15 - -

Signal Group Signal Name Signal Type Topology Reference Plane

DataVDOUT[7:0]

Single-ended Point-to-Point Ground/PowerVDOUT[15:8]VDOUT[23:16]

ControlVDHSYNC

Single-ended Point-to-Point Ground/PowerVDVSYNC

Clock VDCLK Single-ended Point-to-Point Ground/Power


32

Table24: LCDlayoutguidelines

4.5.3 LCDReferenceSchematics

Figure39:LCD reference circuitry

Signal Group Signal Name Routing LayerLength Difference (mil) Accumulated

Trace Length (LT)To Clock In Group

DataVDOUT[7:0]

Top/Bottom <500 <1000Route to Minimum

(or<6")VDOUT[15:8]VDOUT[23:16]

ControlVDHSYNC

Top/Bottom <500 <1000Route to Minimum

(or<6")VDVSYNC

Clock VDCLK Top/Bottom -- --- --


33

4.6 Touch Panel InterfaceTheSOM-6X50modulefeaturesatouchpanelinterfaceforcapacitivetouchscreens.Itallowstheintegrationofthetouchscreensolutiononthecarrierboard.ThetouchpanelinterfaceisaninterfaceconnectionbetweentheSOMDDR3SODIMMslot,capacitivetouchsensorcontroller,andtouchpanelconnector.Thetouchpanelinterfacesupports4-wireand5-wirecapacitivetouchscreens.

4.6.1 TouchPanelSignalDefinitionThefollowingtableprovidesthedefinitionofthetouchpanelsignals.

Table25: Touchpanelsignaldefinition

From SOM DDR3 SODIMM Slot to Capacitive Touch Sensor ControllerSignal Name Pin # I/O Description

GPIO4 174 O TPresetsignalGPIO5 176 O TPinterruptsignal

I2C3SDA 146 O TP I²C DataI2C3SCL 148 O TP I²C Clock

From Capacitive Touch Sensor Controller to Touch Panel Connector

Signal Name Pin # I/O Description

DRIVE00 22 O CapacitivetouchICdriveline-0
















SENSE00 31 I CapacitivetouchICsenseline-0











34

Figure40:Touchpanelroutingtopology

4.6.2 TouchPanelLayoutandRoutingRecommendations•Keeptracelengthsasshortaspossible.

• It is recommended to route the traces on the top layer.

•Theamountofviasandcornersusedforthetouchpanelsignallayoutshouldbeminimized.

Table26: Touchpaneltraceproperties

Table27: Touchpanelsignaltype,routingtopologyandreferenceplane

Table28: Touchpanellayoutguidelines

L2

Touch Panel Connector

RRS

SOM DDR3SODIMM Slot

SOM-6X50Ed

ge fi

nger

GPIO4

GPIO5

I2C3SCL

I2C3SDA

CapaciveTouch screen Capacive

Touch Sensor Controller

TP_RESET

TP_INT

TP_SCL

TP_SDA

DRIVE[15:00]

SENSE[09:00]

L2

L1

L1

L1

L1

Interface Signal Name Trace Impedance

Trace (mil)(Width : Spacing)

Trace Mismatch


SOM DDR3 SODIMM slot to Touch Screen Controller

GPIO4

55Ω±10% 5:5 20mil 5milGPIO5I2C3SCLI2C3SDA

Touch screen controllerto Touch panel connector

DRIVE[23:00]55Ω±10% 5:5 20mil 5mil

SENSE[09:00]

Interface Signal Name Signal Type Topology Reference Plane

SOM DDR3 SODIMM slot to Touch screen controller

GPIO4

Single-ended Point-to-Point Ground/PowerGPIO5I2C3SCLI2C3SDA

Touch screen controller to Touch panel connector

DRIVE[23:00]Single-ended Point-to-Point Ground/Power

SENSE[09:00]

Interface Signal Name Routing Layer


Accumulated Trace Length (L1 + L2 = LT)

SOM DDR3 SODIMM slot to Touch Screen Controller

GPIO4

Top/Bottom - 2"GPIO5I2C3SCLI2C3SDA

Touch screen controllerto Touch panel connector

DRIVE[23:00]Top/Bottom 200mil 2"

SENSE[09:00]


35

4.6.3 TouchPanelReferenceSchematics

Figure41:Touch panel reference circuitry


36

4.7 GPIO InterfaceTheSOM-6X50modulefeaturesaGeneralPurposeInputandOutput(GPIO)interface.

4.7.1 GPIOSignalDefinitionThefollowingtableprovidesthedefinitionoftheGPIOsignalsthatareimplementedintheSOMDDR3SODIMM slot.

Table29: GPIOsignaldefinition

4.7.2 GPIOLayoutandRoutingRecommendation

Table30: GPIOtraceproperties

Table31: GPIOsignaltype,topologyandlayoutguidelines

Signal Name Pin # I/O DescriptionGPIO0 168 IO

General Purpose GPIO

GPIO1 166 IOGPIO3 172 IO

GPIO4 174 IOGPIO5 176 IOGPIO6 170 IOGPIO7 180 IOGPIO8 182 IOGPIO9 178 IOSUS_GPIO0 150 IO

General Purpose GPIO for Suspend Power DomainSUS_GPIO1 179 IO

Signal Group Signal Name Trace ImpedanceTrace (mil)

(Width : Spacing)Spacing to

Other Signal

Data

GPIO[1:0]55Ω 5:5 5mil

GPIO[9:3]SUS_GPIO0

55Ω 5:5 5milSUS_GPIO1

Signal Group Signal Name Signal Type Topology Reference Plane Accumulated Trace Length

Data

GPIO[1:0]Single-ended Point-to-Point Ground/Power 12"

GPIO[9:3]SUS_GPIO0

Single-ended Point-to-Point Ground/Power 12"SUS_GPIO1


37

4.8 I²C InterfaceThe SOM-6X50 module features an I²C interface that can support up to three I²C devices.

4.8.1 I²CSignalDefinitionThefollowingtableprovidesthedefinitionoftheI²CsignalsthatareimplementedintheSOMDDR3SODIMMslot.

Table32: I²Csignaldefinition

4.8.2 I²CLayoutandRoutingRecommendation

Table33: I²Ctraceproperties

Table34: I²Csignaltype,topologyandlayoutguidelines

Signal Name Pin # I/O DescriptionI2C1SDA 138 IO I²C1 serial dataI2C1SCL 140 IO I²C1 serial clockI2C2SDA 144 IO I²C2 serial data

I2C2SCL 142 IO I²C2 serial clockI2C3SDA 146 IO I²C3 serial dataI2C3SCL 148 IO I²C3 serial clock



Other SignalData I2C[3:1]SDA 55Ω 5:5 5milClock I2C[3:1]SCL 55Ω 5:5 5mil


Data I2C[3:1]SDA Single-ended Daisy chain Ground/Power <12"Clock I2C[3:1]SCL Single-ended Daisy chain Ground/Power <12"


38

4.9 SPI InterfaceThe SOM-6X50 module features two SPI interfaces. Each SPI interface can support one master and one slave.

4.9.1 SPISignalDefinitionThefollowingtableprovidesthedefinitionoftheSPIsignalsthatareimplementedintheSOMDDR3SODIMMslot.

Table35: SPIsignaldefinition

4.9.2 SPILayoutandRoutingRecommendation

Table36: SPItraceproperties

Table37: SPIsignaltype,topologyandlayoutguidelines

Signal Name Pin # I/O DescriptionSPI0MISO 9 I MasterInput0,SlaveOutput0SPI0MOSI 11 O MasterOutput0,SlaveInput0SPI0CLK 13 O Serial Clock 0

SPI0SS0- 15 O Slave Select 0SPI1MOSI 156 I MasterOutput1,SlaveInput1SPI1MISO 164 O MasterInput1,SlaveOutput1SPI1CLK 160 O Serial Clock 1SPI1SS0- 162 O Slave Select 1



Other Signal

DataSPI[1:0]MISO

55Ω 5:5 5milSPI[1:0]MOSISPI[1:0]SS0-

Clock SPI[1:0]CLK 55Ω 5:10 5mil


DataSPI[1:0]MISO

Single-ended Daisy chain Ground/Power <10"SPI[1:0]MOSISPI[1:0]SS0-

Clock SPI[1:0]CLK Single-ended Rs=22Ω Ground/Power <10"


39

4.10 Audio InterfaceTheSOM-6X50modulefeaturesanaudiointerfaceforaudioconnectorssuchastwoLine-in,headphone,monospeakerout,rightandleftchannelspeakers,andmicrophone.

4.10.1 AudioSignalDefinitionThefollowingtableprovidesthedefinitionoftheaudiosignalsthatareimplementedintheSOMDDR3SODIMM slot.

Table38: Audiosignaldefinition

4.10.2 AudioLayoutandRoutingRecommendations•Routetheanaloganddigitaltracesignalsasfaraspossiblefromeachothertopreventnoise.

•Routetheclocktraceawayfromanyanaloginputandvoltagereferencepins.

•Isolatethecodecorputawayfromanymajorcurrentpathorgroundbounce.

•Fillwithcoppertheregionsbetweentheanalogtracesandattachedittotheanalogground.

•Fillwithcoppertheregionsbetweenthedigitaltracesandattachedittothedigitalground.

•Keeptracelengthsasshortaspossible.

Table39: Audiotraceproperties

Signal Name Pin # I/O DescriptionHPOUTR 143 O HeadphonerightchanneloutputHPOUTL 147 O HeadphoneleftchanneloutputOUT3 145 O Audio mono output

LINPUT1 157 I Leftchannelsingle-endedMicinput/LeftchannelnegativedifferentialMicinput

LINPUT2 155 I Leftchannellineinput/LeftchannelpositivedifferentialMicinput

LINPUT3 153 I Leftchannellineinput/LeftchannelpositivedifferentialMicinput/Jack detect input pin

RINPUT1 161 I Rightchannelsingle-endedMicinput/RightchannelnegativedifferentialMicinput

RINPUT2 163 I Rightchannellineinput/RightchannelpositivedifferentialMic input

SPK_OUT_R+ 133 O RightspeakerpositiveoutputSPK_OUT_R- 131 O RightspeakernegativeoutputSPK_OUT_L+ 139 O LeftspeakerpositiveoutputSPK_OUT_L- 137 O Leftspeakernegativeoutput

Signal Name Trace ImpedanceTrace (mil)


Other SignalHPOUTR

55Ω±10% 8:5 5milHPOUTLOUT3 55Ω±10% 8:5 5milLINPUT[3:1]

55Ω±10% 8:5 5milRINPUT[2:1]SPK_OUT_R[+/-]

55Ω±10% 8:5 5milSPK_OUT_L[+/-]


40

Table40: Audiosignaltype,topologyandlayoutguidelines

4.10.3 AudioInterfaceReferenceSchematics

Figure42:Line-in1&2referencecircuitry

Figure43:Headphone reference circuitry

Figure44:Mono speaker out reference circuitry

Signal Name Signal Type Topology Reference Plane Accumulated Trace Length

LINPUT[3:1]Single-ended Point-to-Point Ground <10"

RINPUT[2:1]SPK_OUT_R[+/-]

Single-ended Point-to-Point Ground <10"SPK_OUT_L[+/-]


41

Figure45:Rightchannelspeakerreferencecircuitry

Figure46:Leftchannelspeakerreferencecircuitry

Figure47:Onboard microphone reference circuitry


42

4.11 SD InterfaceTheSOM-6X50modulefeaturesanSDinterfaceforSDstorage.

4.11.1 SDSignalDefinitionThefollowingtableprovidesthedefinitionoftheSDsignalsthatareimplementedintheSOMDDR3SODIMMslot.

Table41: SDsignaldefinition

Figure48:SDroutingtopology

4.11.2 SDLayoutandRoutingRecommendations•SignaltracesshouldbeaboveasolidandcontinuousgroundplanealongthepathfromSOMDDR3 SODIMM slot to SD slot.

•SD0CMDtracesignalmusthavepull-upresistorof4.7KΩ.

•SD0WPtracesignalmusthavepull-downresistorof1KΩtotheground.

•TheESDprotectionoftracesignalSD0PWRSWmustbeplacedneartheSDslot.

Signal Name Pin # I/O DescriptionSD0DATA0 25 IO Datasignal0,usedforSDinterfaceSD0DATA1 21 IO Datasignal1,usedforSDinterfaceSD0DATA2 29 IO Datasignal2,usedforSDinterfaceSD0DATA3 31 IO Datasignal3,usedforSDinterfaceSD0CMD 27 IO Commandsignal,addexternalpull-upresistorSD0CLK 19 O SD0 bus clockSD0CD 35 I SD0 CommandSD0PWRSW 33 O SD0 Power switchSD0WP 23 I SD0 write protect

L2L1

L2L1

L2L1

L1 L2

L1 L2

ESD

R

VCC33_SD0

R

SD slot

ESD SOM DDR3SODIMM Slot

SD0DATA[3:0]

SD0CMD

SD0CD

SD0PWRSW

SD0WP

SD0CLK SOM-6X50

Edge

fing

er


43

Table42: SDtraceproperties

Table43: SDsignaltype,topologyandlayoutguidelines

4.11.3 SDInterfaceReferenceSchematics

Figure49:SD reference circuitry

Signal Group Signal Name Signal Type Topology Reference PlaneAccumulated Trace Length(L1 + L2 = LT)

Data SD0DATA[3:0] Single-ended Point-to-Point Ground/Power <8"

Control

SD0CMD

Single-ended Point-to-Point Ground/Power <8"SD0CDSD0WPSD0PWRSW

Clock SD0CLK Single-ended Point-to-Point Ground/Power <8"



Other SignalData SD0DATA[3:0] 55Ω±15% 5:5 5mil

Control

SD0CMD

55Ω±15% 5:5 5milSD0CDSD0WPSD0PWRSW

Clock SD0CLK 55Ω±15% 5:15 15mil


44

Appendix A. SOMDB1 Carrier Board Reference SchematicsTheSOMDB1istheevaluationcarrierboardforSOM-6X50module.TheschematicsoftheSOMDB1carrierboardcanbeusedasanexampleofhowtodesignacarrierboardthatprovidesoptimalperformancewhenusedwiththeSOM-6X50module.Thereferencedesignsareonlyforreferencingandnottobecopied.

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

DDR3 SODIMM Golden finger

5V DC Input 1A

UART0 and 1 from WM8850

I2C Signal need external pull high

UART 3 has lower throughput rates than UARTS 0-2

5VIN

VCC33

VSUS33

MICBIAS

VCC-BAT

VCC33

VSUS33

5VIN

VCC-BAT

VVSYNC18,19

VDIN418,19

VCLK18,19

PWMOUT313PWMOUT213

PWRBTN-13,20RSMRST-13,20

PWRENVDD13SUS_GPIO113,20

RINPUT114

WAKEUP313

PWRENMEM13

LINPUT114

LINPUT314LINPUT214

WAKEUP213CIRIN11

PWRENVCC5,6,7,13,14,18

RINPUT214

VDIN018,19VDIN118,19VDIN218,19

HPOUTL14OUT314

SPK_OUT_L-14SPK_OUT_L+14

PWREN_MAIN13

UART0TXD 11

SD3DATA1 10

UART0RXD 11

SD3DATA0 10

SD3DATA2 10

SD3CMD 10SD3CLK 10

UART1RTS 10UART1TXD 10UART1RXD 10

UART1CTS 10

SD3DATA3 10

I2C2SCL 12,19

VDOUT23 16

GPIO9 13,19GPIO7 10,13GPIO8 13,14

GPIO5 13,17GPIO4 13,17

GPIO1 10,13GPIO0 10,13GPIO6 10,13GPIO3 13,15

SPI1SS0- 12SPI1MISO 12

SPI1CLK 12

SPI1MOSI 12

I2C2SDA 12,19I2C3SDA 12,17I2C3SCL 12,17

WAKEUP0 10,13

SUS_GPIO0 13,20PWRGD 13,20

VDIN518,19VDIN718,19

C24MOUT19

VHSYNC18,19GPIO1218,20GPIO1318

SPK_OUT_R+14SPK_OUT_R-14

HPOUTR14

VDOUT9 16

VDOUT11 16

VDOUT7 16

VDOUT6 16

VDOUT5 16VDOUT4 16

VDOUT22 16

VDOUT20 16VDOUT21 16

VDOUT19 16

VDOUT15 16

VDOUT17 16VDOUT18 16

VDOUT16 16

VDOUT12 16

VDOUT14 16

VDOUT13 16

VDIN318,19

VDIN618,19

I2C1SDA 12,18I2C1SCL 12,18

nHDMID1-7

nHDMID0+7

nHDMICLK-7nHDMICLK+7

nHDMID2+7nHDMID2-7

nHDMID1+7

nHDMID0-7

UARTD_RX 6

UARTD_RTS 6UARTD_CTS 6

UARTC_TX 6

UARTC_RTS 6

UARTB_TX 6UARTB_RX 6UARTB_RTS 6UARTB_CTS 6

UARTA_TX 6UARTA_RX 6UARTA_RTS 6UARTA_CTS 6

SPI0MISO12

SPI0CLK12

SD0WP9

SD0PWRSW9SD0DATA39SD0DATA29

SD0DATA19

SD0DATA09SD0CMD9

SD0CLK9

nUSBHD0+ 5nUSBHD0- 5

nUSBH2+ 5nUSBH2- 5

nUSBH1- 5nUSBH1+ 5

nHDMIHPD7

nHDMIDDCSDA7nHDMIDDCSCL7

nHDMICEC7

NET_TX-8NET_TX+8

NET_RX-8NET_RX+8

M0_LINK8M0_SPEED8

USBSW05USBID05USBATTA05

SD0CD9

PWMOUT110,13PWMOUT013,15

VDVSYNC 16VDHSYNC 16

VDDEN 16VDCLK 16VDOUT0 16

UARTD_TX 6

UARTC_RX 6

UARTC_CTS 6

SPI0MOSI12

SPI0SS0-12

VDOUT10 16VDOUT1 16VDOUT8 16

VDOUT3 16VDOUT2 16

Title

Size Document Number Rev

Date: Sheet of

VTS8666C 1.0

DDR3 SODIMM Golden Finger

Custom4 24Wednesday, November 29, 2017

Title


Date: Sheet of

VTS8666C 1.0



Title


Date: Sheet of

VTS8666C 1.0



C18010uF

C1810.1uF

TP1

TestPoint_1mm

1

C40.1uF

U67

071CAAAZ68B

1

V15

TestPoint_1mm

1

GND1

TestPoint_1mm

1

U68

071CAAAZ68B

1

C18310uF

TP2

TestPoint_1mm

1

C1840.1uF

V16

TestPoint_1mm

1

C18222uF

C322uF

TP76

TestPoint_1mm

1

PCB THICKNESS 1.0mm

J1

GF-DDR3_SODIMM_204P

A098

ODT1120

BA0109 BA1

108

CS0#114

CS1#121

CKE073

CKE174

CK0101

CK0#103 CK1

102

CK1#104

SDA200

SCL202

ODT0116

VREFDQ1

BA279 A15

78

A1480

A197 A2

96A3

95

A492

A591 A6

90

A786

A889

A985

A10/AP107

A1184

A12/BC#83

A13119

D05

D17

D215

D317

D44

D56

D616

D718

D821

D923

D1033

D1135

D1222

D1324

D1434

D1536

D1639

D1741

D1851

D1953

D2040

D2142

D2250

D2352

D2457

D2559

D2667

D2769

D2856

D2958

D3068

D3170

D32129

D33131

D34141

D35143

D36130

D37132

D38140

D39142

D40147

D41149

D42157

D43159

D44146

D45148

D46158

D47160

D48163

D49165

D50175

D51177

D52164

D53166

D54174

D55176

D56181

D57183

D58191

D59193

D60180

D61182

D62192

D63194

EVENT#198

NC2122

RESET#30

VREFCA126

TEST125

GND2

GND3

GND8

GND9

GND13

GND14

GND19

GND20

GND25

GND26

GND31

GND32

GND37

GND38

GND43

VDD175

VDD276

VDD381

VDD482

VDD587

VDD688

VDD793

VDD894

VDD999

VDD10100

VDD11105

VDD12106

VDD13111

VDD14112

VDD15117

VDD16118

VDD17123

VDD18124

SA0197

SA1201 VDDSPD199

NC177

DQM011

DQM128

DQM246

DQM363

DQM4136

DQM5153

DQM6170

DQM7187

GND44

GND48

GND49

GND54

GND55

GND60

GND61

GND65

GND66

GND71

GND72

DQS012DQS0#10

DQS129 DQS1#27

DQS247 DQS2#45

DQS364DQS3#62

DQS4137 DQS4#135

DQS5154DQS5#152

DQS6171 DQS6#169

DQS7188DQS7#186

GND127

GND128

GND133

GND134

GND138

GND139

GND144

GND145

GND150

GND151

GND155

GND156

GND161

GND162

GND167

GND168

GND172

GND173

GND178

GND179

GND184

GND185

GND189

GND190

GND195

GND196

WE#113

CAS#115

RAS#110

VTT203

VTT204

C1851uF

C222uF

V17

TestPoint_1mm

1

C110uF

TP77

TestPoint_1mm

1

VVSYNC

VCLK

PWMOUT2

RSMRST-PWMOUT3

SUS_GPIO1

PWRBTN-

PWRENMEMPWRENVDD

WAKEUP3

LINPUT2LINPUT1

RINPUT1

LINPUT3

CIRIN

PWRENVCCWAKEUP2

HPOUTLOUT3

RINPUT2

SPK_OUT_L-SPK_OUT_L+

PWREN_MAIN

SD3DATA1

SD3DATA0

SD3DATA2

SD3CMDSD3CLK

SD3DATA3

SD3WPSD3PWRSW

I2C2SCL

SPI1SS0-SPI1MISO

SPI1CLK

SPI1MOSI

I2C3SDAI2C3SCL

I2C2SDA

PWRGDWAKEUP0

SUS_GPIO0

GPIO0GPIO1

GPIO9GPIO5GPIO4GPIO3GPIO6

GPIO8GPIO7

VDIN7

C24MOUTVDIN5

VHSYNC

SPK_OUT_R-SPK_OUT_R+

HPOUTR

VDOUT22

I2C1SDAI2C1SCL

nLCD1DO3+

nLCD1DO3-

SD3PWRSW

SD3WP

UARTD_TXUARTD_RX

UARTD_RTSUARTD_CTS

UARTC_TX

UARTC_RTS

UARTB_TXUARTB_RXUARTB_RTSUARTB_CTS

UARTA_TXUARTA_RXUARTA_RTSUARTA_CTS

SD0WP

SD0PWRSWSD0DATA3SD0DATA2

SD0DATA1

SD0DATA0SD0CMD

SD0CLKnUSBHD0-nUSBHD0+

nUSBH2-nUSBH2+

nUSBH1-nUSBH1+

nHDMIHPD

nHDMIDDCSDAnHDMIDDCSCL

nHDMICEC

NET_TX-NET_TX+

NET_RX-NET_RX+

M0_LINKM0_SPEED

USBATTA0

USBSW0USBID0

SD0CD

PWMOUT1PWMOUT0

nLCD1DO3-nLCD1DO3+

UARTC_CTS

UARTC_RX

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

USB

Rset

Ilim(A)=6800/Rset(ohm)6800/6800=1A

Co-lay

Current Limit: 1.0A

Ilim(A)=6800/Rset(ohm)6800/10000=0.68A

Rset

1

0

Device

USB PORT 0 Configuration Table

HOST

USBID0

VCC33

VSUS33

5VIN

5VIN

nUSBH1+4

nUSBH1-4

nUSBH2+4

nUSBH2-4

nUSBHD0+4

nUSBHD0-4

USBATTA0 4 USBID04

USBSW04

PWRENVCC4,6,7,13,14,18

Title


Date: Sheet of

VTS8666C 1.0

USB I/F


Title


Date: Sheet of

VTS8666C 1.0

USB I/F


Title


Date: Sheet of

VTS8666C 1.0

USB I/F


L3DLW21SN900HQ2

3

21

4

C1110uF

C1310uF

ESD2CS0801S

12

C810uF

+ CE1100uF

12

ESD3CS0801S

12

ESD6

CS0801M

12

C141000pF

ESD8CS0801S

12

V18

TestPoint_1mm

1

R8 1K

ESD7CS0801S

12

R710K_1%

ESD5CS0801S

12

R310K

C101000pF

ESD4CS0801S

12

R5 10K

ESD9

CS0801M

12

+ CE2100uF

12

R920K

U2

SY6280AAC

OUT1

GND2

SET3

EN4

IN5

J270555-0003

123

M1

M2

4

R1

6.8K_1%

L2DLW21SN900HQ2

3

21

4

J470555-0003

123

M1

M2

4

C510uF

R40/X

J7LK-SP-Micro_USB

11

22

33

44

55

G3

G3

G4

G4

G1

G1

G2

G2

C610uF

C1210uF

R2 1K

U1SY6280AAC

OUT1

GND2

SET3

EN4

IN5

C710uF

V19

TestPoint_1mm1

R60

L1DLW21SN900HQ2

3

21

4

C910uF

ESD1

CS0801M

12

USBH1+nUSBH1+

nUSBH1- USBH1-

nUSBH2-

nUSBH2+

USBH2-

VBUS01

USBH2+

USB_VBUS

USBH0- USBHD0-USBH0+ USBHD0+

nUSBHD0+

nUSBHD0-

USBID0

USB_VBUS

USBID0

USB_VBUS

VBUS01

USBH1+

VBUS01USBH2-USBH2+

USBH1-

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

UART

1A or Higher

Vout=0.6*(1+R1/R2)0.6*(1+453K/100K)=3.3V

R1

R2

3.3VVCC33_UART

5VIN

VCC33_UART

VCC33_UART

VCC33_UART

VCC33_UART

VCC33_UARTVCC33_UART

VCC33_UARTVCC33_UART

UARTA_TX4UARTA_RTS4

UARTA_RX4UARTA_CTS4

UARTB_RTS4UARTB_TX4

UARTB_CTS4UARTB_RX4

UARTC_TX4

UARTC_CTS4UARTC_RX4

UARTC_RTS4

UARTD_CTS4

UARTD_TX4

UARTD_RX4

UARTD_RTS4

PWRENVCC4,5,7,13,14,18

Title


Date: Sheet of

VTS8666C1.0

RS-232 Output Conn


Title


Date: Sheet of

VTS8666C1.0

RS-232 Output Conn


Title


Date: Sheet of

VTS8666C1.0

RS-232 Output Conn


R335 1K

C33 0.1uF

C28 0.1uF

ES

D1

0C

S0

80

1M

12

C1891000pF

ES

D2

1C

S0

80

1M

12

J8HEADER 2X6

13 45 67 89 10

11 12

2

ES

D2

0C

S0

80

1M

12

C23 0.1uF

J59

85205-0500N

12

G1

G2

345

R23 33

C18610uF

R19 33

C19020pF

C18710uF

U6SP3232EBEY-L_TSSOP16

V-6

VC

C1

6

C1+1

V+2

C1-3

C2+4

C2-5

GN

D1

5

DOUT114

DOUT27

RIN113

RIN28

DIN111

DIN210

ROUT112

ROUT29


V-6

VC

C1

6

C1+1

V+2

C1-3

C2+4

C2-5

GN

D1

5

DOUT114

DOUT27

RIN113

RIN28

DIN111

DIN210

ROUT112

ROUT29

ES

D1

1C

S0

80

1M

12

C18 0.1uF

R15 33

R24 33

U27

SY8086AAC

EN1GND2LX3

VIN4

FB5

R20 33

C310.1uF

ES

D2

2C

S0

80

1M

12

C250.1uF


V-6

VC

C1

6C1+

1

V+2

C1-3

C2+4

C2-5

GN

D1

5

DOUT114

DOUT27

RIN113

RIN28

DIN111

DIN210

ROUT112

ROUT29

R25 33

ES

D1

2C

S0

80

1M

12

ES

D1

4C

S0

80

1M

12

C18810uF

R21 33


V-6

VC

C1

6

C1+1

V+2

C1-3

C2+4

C2-5

GN

D1

5

DOUT114

DOUT27

RIN113

RIN28

DIN111

DIN210

ROUT112

ROUT29

R17 33

ES

D1

3C

S0

80

1M

12

C200.1uF

R22 33

ES

D2

3C

S0

80

1M

12

R18 33

J55

85205-0500N

12

G1

G2

345

C150.1uF

J9HEADER 2X6

13 45 67 89 10

11 12

2

R16 33

R332100K

V20

TestPoint_1mm

1

C300.1uF

ES

D1

5C

S0

80

1M

12

C260.1uF

R14 33

ES

D2

5C

S0

80

1M

12

R11 33

C340.1uF

R334453K_1%

C290.1uF

C220.1uF

J58

85205-0500N

12

G1

G2

345

R12 33

ES

D1

7C

S0

80

1M

12

ES

D1

8C

S0

80

1M

12

C32 0.1uF

C27 0.1uF

ES

D2

4C

S0

80

1M

12

C21 0.1uF

R13 33

ES

D1

6C

S0

80

1M

12

C160.1uF

R10 33

C240.1uF

J57

85205-0500N

12

G1

G2

345

C17 0.1uF

ES

D1

9C

S0

80

1M

12

C190.1uF

R333100K_1%

L12 ZAD-3015MES-3R3M

COMA_RX

COMA_RTS

COMA_CTS

COMA_TXUARTA_TX

COM_A_TXCOM_A_RX

COM_A_RTSCOM_A_CTS

UARTA_RTS

UARTA_RXUARTA_CTS

COMA_RXCOMA_TXCOMA_CTSCOMA_RTS

COMB_TX

COMB_CTS

COMB_RTS

COMB_RX

COM_B_RXCOM_B_TXCOM_B_CTSCOM_B_RTS

UARTB_TXUARTB_RTS

UARTB_CTSUARTB_RX

COMB_RXCOMB_TXCOMB_CTSCOMB_RTS

COMC_CTS

COMC_TX

COMC_RX

COMC_RTS

COM_C_TXCOM_C_RX

COM_C_RTSCOM_C_CTS

COMD_CTS

COMD_TX

COMD_RX

COMD_RTS

COM_D_TXCOM_D_RX

COM_D_RTSCOM_D_CTS

COMD_RX

COMD_CTSCOMD_TX

COMD_RTS

UARTC_CTSUARTC_RX

UARTC_TXUARTC_RTS

COMC_TX

COMC_RTSCOMC_CTS

COMC_RX

UARTD_TX

UARTD_RXUARTD_CTS

UARTD_RTS

UARTA_TXUARTA_RTS

UARTA_CTSUARTA_RX

UARTB_RTSUARTB_TX

UARTB_RXUARTB_CTS

UARTC_CTS

UARTC_TX

UARTC_RXUARTC_RTS

UARTD_RX

UARTD_TXUARTD_RTS

UARTD_CTS

COM_A_CTSCOM_A_RTS

COM_A_RXCOM_A_TX

COM_B_RXCOM_B_TX

COM_A_RTSCOM_A_CTS

COM_A_TXCOM_A_RX

COM_B_RX

COM_B_RTSCOM_B_CTS

COM_B_TX

COM_C_RXCOM_C_TXCOM_C_CTSCOM_C_RTS

COM_D_RTS

COM_D_RXCOM_D_TXCOM_D_CTS

COM_C_TXCOM_C_RX

COM_D_RXCOM_D_TX

COM_B_CTSCOM_B_RTS

COM_C_RTSCOM_C_CTS

COM_D_RTSCOM_D_CTS

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

HDMI

In Pair Pair to Pair

nHDMID[2:0]+/-

Do not change.

ESD Component can not be costdown!

nHDMICLK+/-

Notice: ESD components place near HDMI connector.

HDMI Port

HDMICLK+/-

For HDMI Logo:

HDMID[2:0]+/-< 5 < 100

LT < 3"

(5:7:5)

Do not change.

For HDMI Logo: SPN7002 change to FDV301N

Signal Name

For HDMI Logo:

Closed to HDMI connector

Length Mismatch (mils)Total Length

(Width : Spacing)

VCC33VCC33

VCC33VCC33

5V_HDMI

VCC33

5V_HDMI

VCC33

5V_HDMI

5VIN

VCC33

nHDMICLK- 4

nHDMID0+ 4nHDMID1- 4nHDMID1+ 4nHDMID2- 4nHDMID2+ 4

nHDMICLK+ 4

nHDMICEC 4,7

nHDMID0- 4

nHDMIHPD 4,7

nHDMIDDCSCL 4,7nHDMIDDCSDA 4,7

nHDMIDDCSDA4,7

nHDMIDDCSCL4,7

nHDMIHPD4,7

nHDMICEC4,7

PWRENVCC4,5,6,13,14,18

Title


Date: Sheet of

VTS8666C 1.0

HDMI


Title


Date: Sheet of

VTS8666C 1.0

HDMI


Title


Date: Sheet of

VTS8666C 1.0

HDMI


R31 100

R3520K

ESD28CS0801M

12

L4

DLW21SN900HQ2

3

21

4

V21

TestPoint_1mm

1

R3847K

Q4L2N7002LT1G

G

DS R34 100

D2

RB520S-30

AK

L5

DLW21SN900HQ2

3

21

4

Q2

LMBT3904LT1G

1

23

R332K

ESD29CS0801M

12

L7

DLW21SN900HQ2

3

21

4

D5

RB520S-30

AK

R371M

R36 100

C380.1uF

D1

RB551V-30/X

A K

L6

DLW21SN900HQ2

3

21

4

R292K

ESD27CS0801M

12

R28 1K

Q3L2N7002LT1G

G

DS

D3 CS0806S

2

G1

45

1

67

910

C371uF

R27

1K

R322K

C351uF

ESD30CS0801M

12

D4 CS0806S

2

G1

45

1

67

910

R302K J10

HT003

123456789

10111213141516171819

G1

G2

G4

G3

R26100K

Q1GN2305-G

G

D SC361uF

C390.1uF

ESD26CS0801M

12

Q5L2N7002LT1G

G

DS

HDMID1-HDMID1+

HDMID2-HDMID2+

HDMICLK-HDMICLK+

HDMID0-HDMID0+

HDMI_CECIN

HDMI_CECIN

nHDMIDDCSDAnHDMIDDCSCL

nHDMI_CECIN

nHDMIHPD

nHDMID1+nHDMID2-

HDMID1-

nHDMID2+

nHDMICLK+

nHDMID0+nHDMID0-

nHDMICLK-

nHDMID1-

HDMICLK+

nHDMID2+

HDMID0+

nHDMIDDCSCL

HDMID1+

HDMI_CECIN

HDMIDDCSCL

nHDMIDDCSDA

nHDMID0-

nHDMID0+

HDMIDDCSDAHDMIDDCSCL

HDMID2+

HDMIDDCSDA

HDMIHPD

HDMIDDCSDAHDMIDDCSCL

HDMID0-

HDMID2-

HDMID1-

HDMICLK-

HDMIHPDnHDMIHPD

HDMID2-

HDMICLK-

nHDMID1+

nHDMID1-

nHDMID2-

nHDMICLK+

nHDMICLK-

HDMID0-

HDMID1+

HDMID2+

HDMICLK+

HDMID0+

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Ethernet

Active

Speed

VCC33

NET_TX-4

M0_LINK 4M0_SPEED 4

NET_RX-4

NET_RX+4

NET_TX+4

Title


Date: Sheet of

VTS8666C 1.0

Ethernet


Title


Date: Sheet of

VTS8666C 1.0

Ethernet


Title


Date: Sheet of

VTS8666C 1.0

Ethernet


R39 75_1%

R43 560C410.1uF

R44 560

Y G

J1162500115

M1G1

M2

G2

12345678

91

0

11

12

C401000pF

D7BTUC05VD323B/X

12

R4075

D6BTUC05VD323B/X

12 R41

75

R42 75_1%

T1 TS8121ALF

TX+16

TX-14

CT315

RX+11

RX-9

CT410

TD+1

CT12

TD-3

RD+6

CT27

RD-8

M0_LINK

NET_TX+

NET_TX-

RX+NET_RX+

NET_RX-

TX-

TX+

RX-

RX-

CMT5

RX+

TX-

TX+

M0_SPEED

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Micro SD

low RDS

Please near SD Card

VCC33_SD0

VCC33

VCC33_SD0

SD0WP4

SD0PWRSW4

SD0CMD4SD0DATA34SD0DATA24

SD0CLK4

SD0DATA14SD0DATA04

SD0CD4

Title


Date: Sheet of

VTS8666C 1.0

Micro SD


Title


Date: Sheet of

VTS8666C 1.0

Micro SD


Title


Date: Sheet of

VTS8666C 1.0

Micro SD


R45 33

ESD47CS0801S

12

ESD48CS0801S

12

Q6

GN2305-G

G

DS

ESD49CS0801S

12

MR01A-01211J12

CARD DETECT9

DAT21

CD/DAT32

CMD3

VDD4

CLK5

VSS6

DAT07

DAT18

G1G1

G2G2

G3G3

G4G4

ESD50CS0801S

12

ESD51CS0801S

12

ESD46CS0801S

12

ESD52CS0801S

12

R47 1K

V22

TestPoint_1mm

1

R46 4.7K

ESD31CS0801M

12

C431uF

C420.1uF

C440.1uF

SD0DATA2

SD0DATA1SD0DATA0

SD0DATA3SD0CMD

SD0CD

SD0CLK

SD0CMD

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Wi-Fi

External 32K input

2.2uF : DCR 0.06 OHM IDC 1.60A

AP6181/AP6330 : 0ohmESP8089: 200ohm

Place close, route short.

- default

C153AP6181/AP6330 : 10pFESP8089: 5.6pF

26MHZ : +/-10 PPM 10PF ESR <40 OHM

Co-lay Design

ESP8089(COB): 2.4GHz WiFiAP6181 : 2.4GHz WiFiAP6330 : 3-in-1 combo 2.4GHz/5GHz WiFi+BT+FM

Ampak 12*12 Module

AP6181/AP6330 : OSC2 26MHzC35/C36 3.9pFR232 100ESP8089:OSC2 40MHzC35/C36 15pFR232 0

Vout=0.894*(1+R1/R2)0.894*(1+270K/100K)=3.3V

VCC_WIFI

VCC_WIFI

VCC_WIFI

VCC_WIFI

VCC_WIFI

5VIN VCC_WIFI

VCC33

WAKEUP04,13

UART1CTS4

PWMOUT1 4,13

UART1RTS4

UART1RXD4UART1TXD4

SD3CLK4

SD3DATA34SD3DATA24

SD3DATA14SD3DATA04

SD3CMD4

GPIO64,13

GPIO7 4,13

GPIO14,13

GPIO04,13

PWRENVCC 4,5,7,13,14,18

Title


Date: Sheet of

VTS8666C 1.0

SDIO WiFi


Title


Date: Sheet of

VTS8666C 1.0

SDIO WiFi


Title


Date: Sheet of

VTS8666C 1.0

SDIO WiFi


R53 0/X

R52100K/X

R573 0/X

R51 100

C5410pF/X

R68 0

R62 0

R50100K

R65 0

C521uF

R71 0

C494.7uF

R69 0

TP78

TestPoint_1mm

1

R55 4.7K

C511uF

R63 0

C461uF

R60 0R59 0/X

R66 0

C451uF

C5710pF

OSC1

26MHz

GND4

11

33

GND2

R70 0

N_VDDSWPIO____45N_VDDSWP_OUT__46N_VDDSWP_IN___47

AP6181/AP6330U8

XT

AL

_O

UT

11

BT

_V

IO/N

_H

OS

T_

WA

KE

8

BT

_H

OS

T_

WA

KE

7

VB

AT

9P

CM

_O

UT

25

SDIO_DATA_CLK17

SDIO_DATA_214

SDIO_DATA_018

SDIO_DATA_CMD16

SDIO_DATA_315

WL_HOST_WAKE13

SDIO_DATA_119

UART_RTS_N41

GP

S_

RF

32

VDDIO22

LP

O2

4

VIN

_L

DO

23

VIN_LDO_OUT21

GND36

BT_RST_N34

N_I2C_SDA35

N_I2C_SCL37

N_REG_PU38

TX239

TX140

XT

AL

_IN

10

WL

_B

T_

AN

T2

TC

XO

_IN

30

GN

D3

GN

D1

PC

M_

SY

NC

28

PC

M_

CL

K2

6

PC

M_

IN2

7

N_

WA

KE

5

BT

_W

AK

E6

WL_REG_ON12

VD

D_

TC

XO

29

GN

D3

1

GN

D3

3

UART_TXD42

GND20

UART_RXD43

UART_CTS_N44

FX

_R

X4

C5510pF/X

R5720K

R48 270K_1%

V23

TestPoint_1mm

1

L8

ZAD-3015MES-4R7N

D10 RB520S-30AK

OSC2

32.768KHz

E/D1

GND2

OUT3

VDD4

C584.7uF

R64 0

C620.1uF

R572 0

J13SMA8400M-0000

1

2345

R49100K_1%

D8 RB520S-30AK

C48 12pF

R54 0

D9 RB520S-30A K

C47 12pF

R67 0

R61 0

U7

EMP8736-00VF05NRR

VIN1

GND2

EN3

ADJ4

VOUT5

C604.7uF

C6110pF

SD_CLK

SD_D0SD_D1

32K768HZ

XTAL26M_I

XTAL26M_O

BT_WAKE_HOST

WAKE_HOST

SD_D2

SD_D3

SD_CMD

WL_REG_ON

SD_CLK

SD_D0

SD_D1

XTAL26M_O

XTAL26M_I

WL_WAKE_HOST

BT_WAKE_HOSTHOST_WAKE_BT

32K768HZ

WIFI_BT_ANT

WL_REG_ON

TXD

RXD

RTS

CTS

CTS

RTS

WL_WAKE_HOST

RXD

SD_D3SD_D2

SD_CMD

TXD

HOST_WAKE_BTWAKE_HOST

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Debug Port and IR

Use the same direction connect wire

Co-lay With IR1.

VCC33

VCC33

VSUS33VSUS33

VSUS33

CIRIN 4

UART0TXD 4UART0RXD 4

Title


Date: Sheet of

VTS8666C 1.0

Debug Port and IR

A11 24Wednesday, November 29, 2017

Title


Date: Sheet of

VTS8666C 1.0

Debug Port and IR


Title


Date: Sheet of

VTS8666C 1.0

Debug Port and IR


R7210K/X

J151251R-04-SM1-TR-F5

12

M1

M2

34

IR1FM-9038LM-5CN

VOUT1 GND2 VCC3

J14HEADER_1X4

1

34

2

C630.1uF

J16HEADER_1X3

21

3

C641uF

CIRIN

UART0TXDUART0RXD

CIRIN CIRIN

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

VCC33 VCC33

VCC33

VCC33

VCC33

VCC33 VCC33

I2C1SCL4,18 I2C1SDA 4,18I2C2SCL4,19 I2C2SDA 4,19I2C3SCL4,17 I2C3SDA 4,17

SPI0CLK4SPI0MOSI4SPI0MISO4SPI0SS0-4

SPI1CLK 4SPI1MOSI 4

SPI1MISO 4SPI1SS0- 4

Title


Date: Sheet of

VTS8666C 1.0

SPI & I2C


Title


Date: Sheet of

VTS8666C 1.0

SPI & I2C


Title


Date: Sheet of

VTS8666C 1.0

SPI & I2C


R732.2K

R742.2K

J17HEADER 2X6

13 45 67 89 10

11 12

2

R772.2K

R752.2K

R762.2K

R782.2K

J18HEADER_2X5

13 4

2

5 67 8

109

SPI0MOSISPI0MISOSPI0SS0-

SPI0CLK SPI1CLKSPI1MOSISPI1MISOSPI1SS0-

I2C1SDAI2C1SCL

I2C2SDAI2C2SCL

I2C3SCLI2C3SDA

I2C1SCL I2C1SDAI2C2SCL I2C2SDAI2C3SCL I2C3SDA

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

VCC33VCC33 VCC33

VCC33 VCC33

VCC33 VCC33 VCC33

VCC33

WAKEUP0 4,10

WAKEUP3 4WAKEUP2 4

PWMOUT14,10PWMOUT04,15

PWMOUT24PWMOUT34

GPIO5 4,17GPIO6 4,10GPIO7 4,10GPIO8 4,14GPIO9 4,19

SUS_GPIO04,20SUS_GPIO14,20

GPIO04,10

GPIO34,15GPIO44,17

GPIO14,10

PWREN_MAIN4PWRENVDD4PWRENMEM4PWRENVCC4,5,6,7,14,18

PWRGD 4,20RSMRST- 4,20PWRBTN- 4,20

Title


Date: Sheet of

VTS8666C 1.0

GPIO & PWM


Title


Date: Sheet of

VTS8666C 1.0

GPIO & PWM


Title


Date: Sheet of

VTS8666C 1.0

GPIO & PWM


LED2LED LAMP RED

12

J21HEADER 2X6

13 45 67 89 10

11 12

2

R812.2K

LED4LED LAMP RED

12

LED3LED LAMP RED

12

R892.2K

LED5LED LAMP RED

12

J19HEADER_2X5

13 4

2

5 67 8

109

R822.2K

R902.2K

LED6LED LAMP RED

12

J20HEADER 2X6

13 45 67 89 10

11 12

2

R912.2K

WAKEUP2WAKEUP0

WAKEUP3

PWMOUT0PWMOUT1PWMOUT2PWMOUT3

GPIO5GPIO6

GPIO9

GPIO7GPIO8

SUS_GPIO1SUS_GPIO0

GPIO1GPIO0

GPIO4GPIO3

PWMOUT2 PWMOUT3

WAKEUP0 WAKEUP2 WAKEUP3

PWREN_MAIN

PWRENMEMPWRENVCC

PWRENVDD RSMRST-PWRGD

PWRBTN-

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

NCN Mode

Close to Amplifier

Mute Speaker

Shortconnection, andshielding withGND

Onboard MIC

VCC33

VCC5_SPK

VCC5_SPK

MICBIAS

5VIN VCC5_SPK

HPOUTR4

HPOUTL4LINPUT34

OUT34

SPK_OUT_L+4SPK_OUT_L-4

LINPUT1 4

RINPUT1 4

LINPUT2 4

RINPUT2 4

PWRENVCC4,5,6,7,13,18

GPIO84,13

SPK_OUT_R+4SPK_OUT_R-4

Title


Date: Sheet of

VTS8666C 1.0

SPK & MIC


Title


Date: Sheet of

VTS8666C 1.0

SPK & MIC


Title


Date: Sheet of

VTS8666C 1.0

SPK & MIC


J28HEADER_1X2

21

FB2BLM15AX102SN1D

C691000pF

C821uF

C671000pF

C781000pF/X R104

100K

C92100pF

J31HEADER_1X3

21

3

C8010uF C84

0.1uF

R115 2.2K

C661000pF/X

FB3BLM15AX102SN1D

J4285204-0200L

12

G1

G2

FB9BLM15AX102SN1D

ESD33

CS0801M

12

J2685204-0200L

12

G1

G2

FB5BLM15AX102SN1D

C88100pF

R105 1K

R1140

FB7BLM15AX102SN1D

R1121K

ESD32

CS0801M

12

Q7LMBT3904LT1G

1

23

J2285204-0200L

12

G1

G2

J29

TSH-3865D

3

4

1

102

J23HEADER_1X2

21

J25HEADER_1X2

21

J32HEADER_1X3

21

3

R108100K

R11620K/X

U10

NS4158

CTRL1

Bypass2

NC3

INN4

VDD6

VO-5

VO+8

GND7

C701000pF/X

C651000pF/X

C89 4.7uF

+CE3 100uF1 2

C87100pF

ESD43CS0801M

12

ESD41CS0801M

12 C91

4.7uF

FB10BLM15AX102SN1D

J24HEADER_1X2

21

R11010K

ESD44CS0801M

12

ESD42CS0801M

12

Q8GN2305-G

G

DS

R113 1K

C760.1uF

FB8BLM15AX102SN1D

R1170

FB6BLM15AX102SN1D

R99 36K

R101 0 C751000pF

R106 0/X

FB4BLM15AX102SN1D

Q9

LMBT3904LT1G

1

23

C68 0.022uF

R102 0 C771uF

C90100pF

C791000pF

C93100pF

R98 0

R11110K

C721000pF/X

R10082K

MIC1O422-40C1-PCD-00-L

1

2

R109 0/X

C741000pF

C85220pF

+CE4 100uF1 2

C731000pF/X

J2785204-0200L1

2

G1

G2

ESD34

CS0801M

12

C86220pF

R10343K

C711000pF

J30HEADER_1X3

21

3

FB1BLM15AX102SN1D

R97 0

C8110uFR107 0

HPOUTR

HPOUTLLINPUT3

SPK3_P

SPK3_N

SPK3_PSPK3_N

SPKL_N

RIN1

LIN1 LINPUT1

RINPUT1

LIN2

RIN2

LINPUT2

RINPUT2

MIC1

LINPUT1

SPK3_PSPK3_N

SPKR_P

SPKR_N

SPKL_P

HPOUTLLINPUT3HPOUTR

OUT3

MIC1

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

TOP Contact Place TOP Layer

Top Contact

VCOM

VCOM

AVDD VGL

VGH

VCC33

VCC33

VCC33

LCM_LEDA15

LCM_LEDK15

VDHSYNC4VDVSYNC4

VDOUT14VDOUT04

VDDEN4

VDOUT74VDOUT64VDOUT54

VDOUT234

VDOUT44

VDOUT214

VDOUT194VDOUT184

VDOUT224

VDOUT204

VDCLK4

VDOUT24VDOUT34

VDOUT104

VDOUT154

VDOUT114

VDOUT144

VDOUT124VDOUT134

VDOUT94VDOUT84

VDOUT174VDOUT164

Title


Date: Sheet of

VTS8666C 1.0

LCD I/F


Title


Date: Sheet of

VTS8666C 1.0

LCD I/F


Title


Date: Sheet of

VTS8666C 1.0

LCD I/F


TP29 TestPoint_1mm1

TP21 TestPoint_1mm1

TP4 TestPoint_1mm1

TP16 TestPoint_1mm1

TP31 TestPoint_1mm1

R14810K

TP28 TestPoint_1mm1

TP10 TestPoint_1mm1

R139 0

TP22 TestPoint_1mm1

C114100pF

R141 100

RN4 1001 23 45 67 8

RN2 1001 23 45 67 8

TP23 TestPoint_1mm1

R14610K

C1170.1uF/25V

TP17 TestPoint_1mm1

TP5 TestPoint_1mm1

TP24 TestPoint_1mm1

C121 1uF

TP11 TestPoint_1mm1

R15010K/X

R142 100

J349631S-50Y913

11

22

33

44

55

66

77

88

99

1010

1111

1212

1313

1414

1515

1616

1717

1818

1919

2020

2121

2222

2323

2424

2525

2626

2727

2828

2929

3030

3131

3232

3333

3434

3535

3636

3737

3838

3939

4040

4141

4242

4343

4444

4545

4646

4747

4848

4949

5050

GNDG1

GNDG2

RN5 1001 23 45 67 8

R15110K/X

TP25 TestPoint_1mm1

TP18 TestPoint_1mm1

R152 10K

TP26 TestPoint_1mm1

TP6 TestPoint_1mm1

TP12 TestPoint_1mm1

C1180.1uF/25V

TP19 TestPoint_1mm1

R140 100

TP7 TestPoint_1mm1

TP13 TestPoint_1mm1

C1151uFCAP0402

TP30 TestPoint_1mm1

C1160.1uF/25V

TP20 TestPoint_1mm1

TP8 TestPoint_1mm1

TP14 TestPoint_1mm1

R14510K

RN1 1001 23 45 67 8

R14910K/X

TP15 TestPoint_1mm1

C1201uFCAP0402

R143 0

TP9 TestPoint_1mm1

TP3 TestPoint_1mm1

RN6 1001 23 45 67 8

RN3 1001 23 45 67 8

TP27 TestPoint_1mm1

R14410K/X

R14710K

C11920pF/X

MODEDITH

RESET

UPDNSHLR

LCD_B7LCD_B6

LCD_B4LCD_B5

LCD_B2LCD_B3

LCD_G7LCD_G6LCD_G5LCD_G4LCD_G3LCD_G2

LCD_R7LCD_R6LCD_R5LCD_R4LCD_R3LCD_R2

LCM_LEDA

LCD_PCLK

LCM_LEDK

SHLRUPDN

RESET

DITHVCOM

MODE

VCOM

LCD_HSYNCLCD_VSYNCLCD_EN

LCD_R4

LCD_R7LCD_R6LCD_R5

LCD_R2LCD_R3

LCD_B7

LCD_B5LCD_B4

LCD_B6

LCD_EN

LCD_HSYNCLCD_VSYNC

LCD_PCLK

LCD_B1LCD_B0

LCD_G1LCD_G0

LCD_R1LCD_R0

LCD_B2LCD_B3

LCD_B1LCD_B0

LCD_G3LCD_G2

LCD_G7LCD_G6

LCD_G4LCD_G5

LCD_G1LCD_G0

LCD_R1LCD_R0

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

CAP closed to Connector Pins.

Touch Panel

P1 GNDP2-P11 Y9-Y0P12,P13 GNDP14-P29 X0-X15P30 GND

TOP

1.8V IO

301

Max 9mA

Top Contact

FOR CAP TOUCH PANEL

TP_30V

TP_18V

TP_30V

TP_30VVCC33

TP_30V

I2C3SCL 4,12I2C3SDA 4,12

GPIO5 4,13GPIO4 4,13

Title


Date: Sheet of

VTS8666C 1.0

CAP Touch - GSL1680


Title


Date: Sheet of

VTS8666C 1.0

CAP Touch - GSL1680


Title


Date: Sheet of

VTS8666C 1.0

CAP Touch - GSL1680


TP55 TestPoint_1mm1

C1291uFCAP0402

TP58 TestPoint_1mm1

R158 0/X

TP43 TestPoint_1mm1

TP42 TestPoint_1mm1

C1234.7uF

C1224.7uF

TP49 TestPoint_1mm1

J351226-30-02

34567

2

9101112131415161718192021222324252627282930

8

1G1

G2

TP50 TestPoint_1mm1

TP36 TestPoint_1mm1

U18GSL1680

AVDD1

AVDD21

GND30

VDDIO16

GND10

GND18

SDA12

SCL13

GPIO014

GPIO115

IRQ17

VTNC20

SHUTDOWN19

1V8_OUT11

Y940Y839Y738Y637Y536

X123

Y031

X152X143X134X125X116X107X98X89

Y233

Y435

X022

X224

X325

X426

X527

X628

X729

Y132

GN

DG

1

Y334

J60

FH34S-6S-0.5SH(10)

11

22

33

44

G1

G1

G2

G2

55

66

TP52 TestPoint_1mm1

TP48 TestPoint_1mm1

R153 0

TP37 TestPoint_1mm1

R574100K/X

TP32 TestPoint_1mm1

C1251uFCAP0402

FB11BLM15AX102SN1D

TP51 TestPoint_1mm1

TP39 TestPoint_1mm1

R154 0

C127

0.1uF

R155 22

R84 33

V7

TestPoint_1mm

1

TP38 TestPoint_1mm1

C124

0.1uF

R86 33

C561

0.1uF

TP44 TestPoint_1mm1

V8

TestPoint_1mm

1

R156 22

TP45 TestPoint_1mm1

TP47 TestPoint_1mm1

TP33 TestPoint_1mm1

R15910K

TP46 TestPoint_1mm1

C1261uFCAP0402

TP53 TestPoint_1mm1

TP57 TestPoint_1mm1

TP34 TestPoint_1mm1

TP54 TestPoint_1mm1

R157 0

TP40 TestPoint_1mm1

C1284.7uF

TP56 TestPoint_1mm1

TP35 TestPoint_1mm1

TP41 TestPoint_1mm1

TP_RESET

TP_SDATP_SCL

SENSE01SENSE00TP_INT

SENSE06SENSE05SENSE04SENSE03SENSE02

SENSE09SENSE08SENSE07

TP_INTTP_RESET

TP_SCLTP_SDA

DRIVE13DRIVE14DRIVE15


DRIVE06DRIVE05

DRIVE07

DRIVE04DRIVE03

DRIVE08DRIVE09

DRIVE02DRIVE01

SENSE00



SENSE07

SENSE09SENSE08

DRIVE02DRIVE03

DRIVE14

DRIVE00DRIVE01

DRIVE10DRIVE11DRIVE12DRIVE13

DRIVE09


DRIVE04DRIVE05

DRIVE15DRIVE00

I2C3SCLI2C3SDA

TP_RESET

TP_SDA

TP_SCL

TP_INT

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

R2R1

Vout=0.894*(1+R1/R2)0.894*(1+100K/100K)=1.788V

DVDD_GM7150 AVDD_GM7150VCAMD_PMU

IODVDD_GM7150

AVDD_GM7150

AVDD_GM7150 DVDD_GM7150

IODVDD_GM7150

IODVDD_GM7150

VCAMD_PMU

5VIN

VCC33 IODVDD_GM7150

VDIN0 4,19VDIN1 4,19

VDIN3 4,19VDIN2 4,19

VDIN4 4,19VDIN5 4,19VDIN6 4,19VDIN7 4,19

VVSYNC 4,19

VHSYNC 4,19

I2C1SCL 4,12

I2C1SDA 4,12

VCLK 4,19

GPIO124,20

GPIO13 4

PWRENVCC4,5,6,7,13,14

GPIO134,13

Title


Date: Sheet of

VTS8666C 1.0

GM7150BC_Video_Decoder


Title


Date: Sheet of

VTS8666C 1.0



Title


Date: Sheet of

VTS8666C 1.0



C14820pF

C5631uF

R169 0

C1410.1uF

Q14

LMBT3904LT1G

1

23

C1351uF

C134 1uF

R567 33

U21

GM7150BC

AIP1A1

AIP1B2

PLL_AGND3

PLL_AVDD4

XTAL15

XTAL26

AGND7

RESETB8

PC

LK

/SC

LK

9

IO_

DV

DD

10

YO

UT

71

1

YO

UT

61

2

YO

UT

51

3

YO

UT

41

4

YO

UT

31

5

YO

UT

21

6

YOUT117

YOUT018

DGND19

SCL21

DVDD20

SDA22

INT

RE

Q2

7

RE

FM

30

CH

_A

GN

D3

1

CH

_A

VD

D3

2

FID/GLCO23

VSYNC/PALI24

HS

YN

C2

5

AV

ID2

6

PD

N2

8

RE

FP

29

PA

DG

1

R168 10K

Q15GN2305-G

G

DS

R184 33

R170 33/X

R183 0/X

C5641uF

R162 0/X

C1321uF

R1801M

C5620.1uF

C1371uF

R175 33

R568 33

C14920pF

C15130pF/X

J45HEADER_1X2

21

C1381uF

FB12BLM15AX102SN1D

V25

TestPoint_1mm

1

C5650.1uF

C1501uF

R164 10K

C146 0.1uF

V28

TestPoint_1mm

1

R160 100K_1%

U19

EMP8736-00VF05NRR

VIN1

GND2

EN3

ADJ4

VOUT5

C136 1uF

R569 33

R564 33

R171 33/X

C1420.1uF

R179 33R173 0/X

R178 33

R174 37.4_1%

x2

14.31818MHZ

GND4

11

33

GND2

R17637.4_1%

R570 33

R57910K

C147 0.1uF

R1810

R565 33

C1401uF

R165100K_1%

R18210K

R5801K

C1390.1uF

Color:YELLOW

U22

WT-04048Y

2

1

34

R177 33/X

R172 33

R571 33

R581 1K

C1301uF

R566 33

CVBS_IN

GM7150_RSTB

GM7150_XTAL2

GM7150_XTAL1

CMDAT7CMDAT6

CMDAT8CMDAT9

CMDAT3

CMDAT2

CMDAT4CMDAT5

VCLK

VHSYNC

VVSYNC

GM7150_RSTB

CVBS_IN

CMVREF

CMHREF

CMCLK

GM7150_SDA

GM7150_SCL

GM7150_XTAL2

GM7150_XTAL1

VDIN0VDIN1VDIN2VDIN3

VDIN4VDIN5VDIN6VDIN7

I2C1SCL

I2C1SDA

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Place near connector.

CCIR656 CameraI2C Address:

0x42

Vout=0.894*(1+R1/R2)0.894*(1+210K/100K)=2.7714V

VCCVID

VCCVID

VCCVIDVCC33 VCCVID

AVCCVIDVCCVID

AVCCVID

VCAMD_PMUDVDD_CAM

GPIO94,13

C24MOUT4

VCLK4,18

I2C2SCL4,12

I2C2SDA4,12

VVSYNC4,18

VHSYNC4,18

VDIN74,18VDIN54,18VDIN34,18VDIN14,18

VDIN6 4,18VDIN4 4,18VDIN2 4,18VDIN0 4,18

Title


Date: Sheet of

VTS8666C 1.0

CCIR656 Camera


Title


Date: Sheet of

VTS8666C 1.0

CCIR656 Camera


Title


Date: Sheet of

VTS8666C 1.0

CCIR656 Camera


C3660.1uF

R19310K

R575 0

C1540.1uF

TP62 TestPoint_1mm1

TP66 TestPoint_1mm1

R185 33

D17RB520S-30/X

A K

TP67 TestPoint_1mm1

C1560.1uF

TP68 TestPoint_1mm1

R186 33C1521uF

TP69 TestPoint_1mm1

C367

4.7uF

V27

TestPoint_1mm

1

R190100K_1%

TP70 TestPoint_1mm1

TP65 TestPoint_1mm1

TP71 TestPoint_1mm1

C3651uF

TP60 TestPoint_1mm1

TP63 TestPoint_1mm1

C1531uF

R234 0

J36FH12-24S-0.5SH

123456789

101112131415161718192021222324

TP72 TestPoint_1mm1

TP73 TestPoint_1mm1

C1910.1uF

U23

EMP8736-00VF05NRR

VIN1

GND2

EN3

ADJ4

VOUT5

TP64 TestPoint_1mm1

TP74 TestPoint_1mm1

TP75 TestPoint_1mm1

TP61 TestPoint_1mm1

C364

4.7uF

R19410K

R188 210K_1%

R192 22

CAMERA1_RESET

CAMERA1_PWDN

VDIN7

VDIN6

VDIN5

VDIN3VDIN0VDIN4

VDIN2VDIN1

CAMERA1_RESET

CAMERA1_PWDN

CAMERA1_RESET

I2C2SDAI2C2SCLVVSYNCVHSYNC

C24MOUTVCLK

VDIN7VDIN6VDIN5VDIN4VDIN3VDIN2VDIN1VDIN0

DVDD_CAM

DVDD_CAM

VDIN7 VDIN6VDIN5 VDIN4

VDIN1VDIN3

VDIN0VDIN2

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Active High

Watchdog

8ms Reserved for WOLwatchdog default enable when DC12V on

watchdog programming header

WDG_RESET_IN PA6

CPU_ACTIVE PA5

RECOVERY_MODE PA4

SUS_GPIO1PA2

Reset Key

SUS_GPIO0

Power Key

I

I

I

WDO PA1 O Cut Power

ILow Power alert

WatchDog External Connect

Vout=0.894*(1+R1/R2)0.894*(1+270K/100K)=3.3V

28V 3A 360kHz 0.8VFB

VIN Range:4.5V-23V

ESD near button.

>=5s

Low for disablewatchdog.

ESD near button.

Power

ESD near button.

Recovery/Reset

ICP_VDDVCC_WDG

ICP_VDD

ICP_VDD

VCC_WDG

5VIN_RTC

SYS_12VIN

5VIN_RTCVCC-BAT

5VIN VCC33 ICP_VDD

5VIN_RTC

5VIN

VCC33

GPIO12 4,18

SUS_GPIO1 4,13

SUS_GPIO04,13

WD_PA4 15

PWRBTN- 15

GPIO0 4,13

RSMRST- 4,20

Title


Date: Sheet of

VTS8666C1.0

DC-IN & WDT


Title


Date: Sheet of

VTS8666C1.0

DC-IN & WDT


Title


Date: Sheet of

VTS8666C1.0

DC-IN & WDT


ESD36CS0801M

12

5VIN

1

ESD38

CS0801M

12

R552 100K

C161

22uF

C5601000pF

C1670.1uF

FID4

FIDUCIAL

1

C160

22uF

ICP_DAT11

MH6

MTH6_3.5N

1234 5

678

9

R557 100K

R211 270K_1%

D44 RB520S-30/XAK

C5580.1uF

FID5

FIDUCIAL

1

R556 100K

J41HEADER_1X4/X

1

34

2

SW2 STS-B51

2

3

4

MH1

MTH6_3.5N

1234 5

678

9

C17610nF

ICP_GND11

FID1

FIDUCIAL

1

R578 10K

R2080

U26HT68F002

VDD1

VSS10

PA7/RES/ICPCK/INT74

PA5/INT53

PA62

PA2/INT27

PA18

PA0/ICPDA9

PA45

PA3/INT36

C5591uF

R206

10k

R577 0/X

ICP_VDD11

FID6

FIDUCIAL

1

V13

TestPoint_1mm

1

LED8LED LAMP RED

12

R210 1K_1%

R198 0

L11SPM7070100MESL

D46 RB520S-30AK

ICP_CLK11

FID2

FIDUCIAL

1

MH3

MTH6_3.5N

1234 5

678

9

ESD45CS0801M

12

R2022.2K

R529 100

C1703.3nf

FID3

FIDUCIAL

1

C179

0.1uF

D19BAT54C

1

23

R576 33

R530 100/X

C16547uFX5R

V11

TestPoint_1mm

1

D18B340A-13/X

A K

LED7LED LAMP RED

12

R216 0

C16647uFX5R

R201 100K/X

U66

SGM2588IYN5I

VOUT1

GND2/FAULT3

EN4

VIN5

V9

TestPoint_1mm1

V14

TestPoint_1mm

1

MH5

MTH6_3.5N

1234 5

678

9

R545 100

J531251S-02-SM1-TR-F5

12

M1

M2

C1750.1uF

R2032.2K

C55610uF

R200100K

U25

EMP8736-00VF05NRR

VIN1

GND2

EN3

ADJ4

VOUT5

MH2

MTH6_3.5N

1234 5

678

9

R474 100/X

C1690.1uF/25V

J46

2317SJ-02

12

C164 56pF

R213100K_1%

C1721uF

R559 33

C1681000pF

U24

MP2303ADN

BO

OS

T1

VIN

2

LX3

FB5

NC6

SHDN7

SS8

GND4

GNDG1

C1620.1uF/25V

R21510K

R550 100K

R214100K

C16310nF/25V

SW1PTS-018S

123

456

C5481000pF

V10

TestPoint_1mm

1

R20710K_1%

C55710uF

ESD40

CS0801M

12

R551 100K

C177

0.1uF

R204 53.6K_1%

R218 33

C1711uF

R205 51K_1%

ESD39

CS0801M

12

MH4

MTH6_3.5N

1234 5

678

9

a b c

SW3 MSS3N-Q-TR

1 32

G1 G2G3 G4

R553 100K

R199100K

WD_PA4

ICP_DAT

WDI

ICP_CLK

WDO

WD_PA2WDG_RESET

ICP_CLK

ICP_VDDICP_DAT

WDG_EN

CPU_ACTIVE

WD_PA3

ICP_CLKICP_DATICP_VDD

PWRBTN-

GPIO12

WD_PA3

WD_PA2

WDO

WD_PA4ICP_DAT

WDI

WDO

WDG_EN

PWRBTN-

RSMRST-

1F, 531 Zhong-zheng Road,Xindian Dist., New Taipei City 231Taiwan

Tel: 886-2-2218-5452Fax: 886-2-2218-9860Email: [email protected]

940 Mission CourtFremont, CA 94539,USA


Email: [email protected]

Taiwan Headquarters USA

Europe

Tsinghua Science Park Bldg. 7No. 1 Zongguancun East Road,Haidian Dist., Beijing, 100084China

Tel: 86-10-59852288Fax: 86-10-59852299Email: [email protected]

3-15-7 Ebisu MT Bldg. 6F,Higashi, Shibuya-kuTokyo 150-0011Japan


ChinaJapan

Documents

DESIGN GUIDE Carrier Board - VIA Technologies, Inc.cdn.viaembedded.com/products/docs/som-6x50/design_guide/DG_C… · DESIGN GUIDE Carrier Board for SOM-6X50 Module 1.01-08232018-160700