Embed Size (px)
Citation preview
Rochester Institute of TechnologyRIT Scholar Works
Theses Thesis/Dissertation Collections
9-1-1991
Design and simulation of a primitive RISCarchitecture using VHDLEvangelos Moustakas
Follow this and additional works at: http://scholarworks.rit.edu/theses
This Thesis is brought to you for free and open access by the Thesis/Dissertation Collections at RIT Scholar Works. It has been accepted for inclusionin Theses by an authorized administrator of RIT Scholar Works. For more information, please contact [email protected].
Recommended CitationMoustakas, Evangelos, "Design and simulation of a primitive RISC architecture using VHDL" (1991). Thesis. Rochester Institute ofTechnology. Accessed from
DESIGN AND SIMULATION OF A PRIMITIVERISC ARCHITECTURE USING VHDL
Evangelos Moustakas
A Thesis Submitted in Partial Fullfilmentof the Requirements for the Degree of
Master of Sciencein
Computer Enginneering
Approved by ProfessorGeorge A. Brown ('Thesis Advisor)
ProfessorTony H. Chang, Ph.D.
ProfessorRoy S. Czernikowski, Ph.D.
Department of Computer EngineeringCollege of Engineering
Rochester Institute of TechnologyRochester, New York
September 1991
September 6, 1991
I, Evangelos Moustakas, hereby deny permission to theWallace Memorial Library of RIT to reproduce my thesis inwhole or in part.
The Author
Abstract
Hardware Description Languages are used as the connecting
links between the design of a digital system and the way this
design is being represented in computers, with the ultimate
goal being the simulation and verification of that design
before the construction of any prototype.
In this thesis, we follow all the steps of a RISC
architecture design and finally use VHDL as the tool to
describe, simulate and verify the design. By the unique
abilities of VHDL we give both a structural and a behavioral
description where the latter contains multiple description
levels, from gate to Processor-Memory-Switch (PMS) . The final
step is the simulation to verify the proper operation of the
design or to assist in pinpointing design errors for
correction .
Table of Contents
Table of contents i
List of figures iii
List of tables iv
List of abbreviations iv
Preface v
1 . The RISC Concept
1.1 How the RISC architecture evolved 1
1.2 Definition of the RISC 1
1.3 Advantages and Disadvantages of the RISC 2
2 . Architecture and Organization
2.1 Why"primitive"
5
2.2 General System Description 7
2.3 System Bus Timing 12
2.4 The Memory Organization and the Stack 14
2.5 Exception Handling 15
3 . The Instruction Set
3.1 The instructions and the fetch cycle 18
3.2 The instruction formats 18
3.3 The addressing modes 22
3.4 The Processor Status Word 25
3.5 Assembly syntax and instruction encoding 2 6
4 . The Central Processing Unit
4.1 The CPU structure 28
4.2 The Control Unit 30
4.3 The Interrupt Unit 31
4 . 4 The control points 32
4.4.1 The immediate registers 35
4.4.2 The register file 35
4.4.3 The Arithmetic Logic Unit 36
4.4.4 The Power Shifter 36
4.5 Instruction Decomposition 37
5 . VHDL Description of the Architecture
5.1 Hardware Description Languages 43
5.1.1 VHDL
~ ~
4 3
5.2 Getting Started 45
5.2.1 Packages 45
5.3 Component Description 4 6
5.4 The data bus 4 8
5.5 The secondary units 50
5.6 The memory 52
5.7 The CPU 53
5.7.1 The registers 53
5.7.2 The control unit 54
5.7.2.1 The internal clock 54
-l-
5.7.2.2 The fetch PROCESS 55
5.7.2.3 The execute BLOCK 55
5.7.2.4 The state coordination 56
5.7.2.5 The interrupts 57
5.7.2.6 The memory access PROCESS 58
5.7.3 The interrupt unit 5 9
5.8 Hints for future VHDL users 59
Simulation of the System
6.1 The program code 63
6.2 Powering up the system 65
6.3 Issuing the RESET interrupt 66
6.4 Program execution and external interrupt 68
Conclusion - Recommendations 7 0
References 71
Appendix A - Package Listing Al
Appendix B - VHDL Program Listing Bl
Appendix C - Simnlatioi* ;._ Program Execution (1) CI
Appendix D - Simulation of Program Execution (2) Dl
-n-
List of Figures
Figure 2 . 1
Figure 2.2
Figure 2 . 3
Figure 2.4a
Figure 2 . 4b
Figure 2.5
Figure 2 . 6
Figure 2.7
Figure 2.8
Figure 2 . 9
Figure 2.10
Figure 3 . 1
Figure 3.2
Figure 3 . 3
Figure 3 . 4
Figure 3.5
Figure 4 . 1
Figure 4.2
Figure 4 . 3
Figure 4.4
Figure 5 . 1
Figure 5.2
Figure 5 . 3
Figure 5 . 4
Figure 5.5
Figure 5 . 6
Figure 5.7
Figure 5 . 8
Figure 5 . 9
Figure 5.10
Figure 5.11
Figure 5 . 12
Figure 5.13
Figure 5.14
Figure 5.15
Figure 5 . 16
Figure 5.17
Figure 5.18
Figure 5.19
Figure 5.20
Figure 5.21
Figure 5.22
Figure 5.23
Figure 5.24
Figure 5.25
Figure 5.2 6
Figure 6 . 1
Figure 6.2
Figure 6 . 3
Figure 6 . 4
System Under Simulation 8
Memory Bank Select Logic 9
Memory Banks and Signals 9
Word and Byte Organization 10
Word and Byte Organization 10
Memory Read/Write Protocol 11
Sequence of Bus Cycles 12
Memory Timing Characteristics 13
System Bus Timing 13
Memory Organization 14
Stack Operation 15
The register-source instruction format 20
The short-immediate instruction format 20
The long-immediate instruction format 21
Instructions & Flags 24
The Processor Status Word 25
The CPU structure 2 9
State Sequence 30
Example of an instruction decoder 32
Control node fox c7 and c8 control signal 33
Description Levels of Digital Systems 44
Directory Organization 4 6
BLOCKS and PROCESSes 47
Control Unit BLOCK 47
Interrupt Unit Block 47
Wired OR logic 48
Resolution Function 4 9
Data bus decomposition 4 9
Data bus PROCESS 50
Example of the data bus formation 50
System Clock Generator 51
Memory Bank Select Unit 51
CPU-Memory handshaking unit 51
Memory Bank #2 52
VHDL description for MAR 54
Internal Clock 55
The fetch PROCESS 55
The execute BLOCK 5 6
The state coordination PROCESS 56
Micro-operations for external interrupt 57
VHDL implementation for external interrupts 8
The memory access PROCESS 5 9
RESET recognition by the IU 5 9
This PROCESS will issue an error 60
This PROCESS will pass 60
A serious error 62
Memory loading 63
Beginning of the simulation 65
RESET interrupt recognition 66
Memory read cycle 6 6
-in-
Figure 6.5 Operation of the buses 67
Figure 6.6 External interrupt assertion 68
List of Tables
Table 2.1 Memory write instructions 11
Table 2.2 Timing Characteristics and their Meaning 13
Table 3.1 The Instruction Set 19
Table 3.2 Opcode Assignment 22
Table 3.3 Instruction syntax & encoding 26
Table 4 . 1 Transfers and Operations 33
Table 5.1 Resolution Table for the input of G3 48
List of Abbreviations
ADL Architecture Description Language
ALU Arithmetic Logic Unit
CISC Complex Instruction Set Computer
CMHU CPU-Memory Handshaking Unit
CPU Central Processing Unit
CU Control Unit
HDL Hardware Description Language
HLL High Level Language
INTA Interrupt Acknowledge
IU Interrupt Unit
MAR Memory Address Register
MBSU Memory Bank Select Unit
MDR Memory Data Register
PC Program Counter
PIA Peripheral Interface Adapter
PMS Processor Memory Switch
PS Power Shifter
PSW Processor Status Word
RISC Reduced Instruction Set Computer
SP Stack Pointer
UART Universal Asynchronous Receiver
Transmitter
VHDL VHSIC Hardware Description Language
VHSIC Very High Speed Integrated Circuit
VMA Valid Memory Address
-iv-
Preface
As one can understand from the title of this thesis, it
is focused on two important topics : The RISC architecture and
the VHSIC Hardware Description Language (VHDL) . They are both
quite recent issues -
although the word"recent"
in computer
related products is usually used to date something no more
than one year old-
since they both began to evolve in the
early1980'
s. They are, however, the main points of attraction
in the computer architecture and hardware description and
simulation fields today and they seem to promise a lot for the
future .
These two apparently disparate topics are connected in
this thesis in the following way. The VHDL is used to describe
and simulate a RISC architecture which will be a primitive but
representative design according to the definition of the RISC
theory. The RISC architecture was chosen because it is much
simpler than the CISC ones and a relatively short time could
be spent to design, develop and describe the system with words
and figures. VHDL can then replace the words and the figures
with universally recognized code for hardware description. The
capabilities of VHDL are exhibited, as we attempt to describe
a complete architecture and not just a single piece of
hardware like a gate or an ALU. The system's parts, their
interconnections, the instruction set, the interrupt handlingand so many other issues of an architecture will become pages
of well organized and self-explained code when described in
VHDL.
The present thesis report contains two parts. In the
first one (chapters 1-4), the architecture of the system that
will be used for the simulation is presented, starting with a
general description of the RISC architecture and continuing
with the organization and the architecture of the machine we
built. Enough details for the behavior of the system and its
parts are given from the chip level down to the register
transfer level. In the second part of the thesis report
(chapters 5-6) we first introduce the VHSIC Hardware
Description Language (VHDL) and then we use it to describe and
simulate the architecture of the system we built in the first
part, explaining simultaneously the features of the language
and the way we use them to complete the project.
Finally, at the completion of this thesis project, I
would like to thank the following faculty members ofRIT'
s
Department of Computer Engineering, professors George A.
Brown, Tony H. Chang and Roy S. Czernikowski, for their
observations, suggestionsand corrections during the project,
but mainly for the valuable time they dedicated in the many
thesis meetings.
v-
1 The RISC Concept
There are many controversial comments today about the
numerous and powerful RISC architectures that have invaded the
microprocessor market, promising a new era the computer
performance. This chapter tries to discover the strong points
of these new CPUs, the reason they became so popular, and
their weaknesses, compared to the more conventional micro
processors .
1 . 1 How the RISC architecture evolved
With the progress of computer technology and the abilityof microprocessor manufacturers to use many more transistors
in a single chip, the instruction sets grew, including more
complex and robust instructions. A typical instruction set
came to have almost two hundred (200) instructions and in
combination with the various and often numerous addressing
modes, a confusing situation emerged where the control unit of
the microprocessor took up almost 60% of the available space.
The programmers and the compilers had a hard time determiningwhich instruction was the best for a particular situation.
Also, a total increase in the average execution time of a
single instruction became inevitable. The instructions could
consist of several bytes or they could use the data and the
address buses several times in order to access their operands,
mainly due to the complicated addressing modes.
Some computer engineers and computer scientists thought
that it would be better if a microprocessor had a simple and
relatively small instruction set with a uniform instruction
size, fewer addressing modes or instruction formats, which
would use only a single fetch cycle for all the instructions .
Also, if possible, a single execution cycle would be used so
that the throughput of the system could be maximum.
After years of research that started within the
laboratories of IBM in the late seventies and continued in a
number of companies in the eighties, a new type of
microprocessor emerged that had all the required
characteristics. It was called RISC (Reduced Instruction Set
Computer) because of its limited instruction set, but it also
had some new features .
1.2 Definition of the RISC
In the early RISC era it was quite easy to define a RISC
machine and say exactly what distinguished it from other CPUs .
Today, after years of development, thenew RISCs are almost as
complicated as CISCs. Experts now have started arguing about
precisely what constitutes a RISC and what does not . Below, we
will try to define a RISC machine depending on the most common
of their characteristics as they are described today .
-1-
Small Instruction Set : It was observed during the years of
research for the RISC machines that most of the compilers used
only 30% of the instruction sets of some robust CISCs. RISC
CPUs attempt to implement only that 30%, giving the ability to
have a smaller, cheaper and faster chip.
Fewer Instruction Formats : The instruction formats are
usually no more than four (4) and they contain instructions of
the same length. It is important that the length matches the
size of the data bus (data word) so that an instruction fetch
will always be one cycle. The only problem with this
restriction is that the loading of an immediate operand may
require more than one instruction, increasing in this way the
overall program size.
Many On-Chip Registers : Most RISCs include a register file
with about one hundred (100) registers. There are of course
some variations like the MIPS R2000 with only 32 registers or
the GMU MIRIS with 2048.
Dummy Registers : Almost all of the RISCs have a dummyregister (usually R0) that yields the value zero when read and
discards any value written to it (i.e. it is always tied to
GROUND) .
Limited Addressing Modes : Because of the existence of many
registers inside the CPU, the operands for each instruction
are usually loaded first into the registers and every ALU
operation is applied to the contents of the registers or a
partial immediate data. The addressing modes, thus, have been
limited and only two are usually met : the register indirect
and the immediate.
Deferred Jumps and Calls : All the RISC CPUs implement a
pipelined execution system. In the case of a branch or a call,
the system cannot immediately execute the instruction before
it flushes or executes the one that had been prefetched (see
2.1) .
Single-Cycle execution : Because most of the operations are
simple and occur between registers, a single execution cycle
has been obtained for most of the instructions. Some others,
however, require multiple execution cycles (load, store,
multiply, divide, etc) .
Load/Store Architecture : The only available way to manipulate
external memory is by the use of the Load and Store
instructions. Some modern RISC architectures have also
complicated Load/Store instructions that may includetest-and-
set or swap operations .
1 . 3 Advantages and Disadvantages of the RISC
In the years of research that brought up the RISC
architecture, the computer experts were demanding four (4)
basic features for their new microprocessors : speed,
simplicity, High Level Language (HLL) support and low cost of
manufacturing. Their demands were accomplished in a high
degree, even though there are always some trade-offs such as
the size of the programs for example.
-2-
The main idea in RISCs is to use a big register file in
the CPU to save most of the operands in order to eliminate the
frequent memory accesses, to build a simple instruction set
with a standard length equal to thesystem'
s data word, and to
reduce the instruction formats and the addressing modes .
By reducing the size of the instruction set and the
number of instruction formats and addressing modes, we reduce
the huge and complicated Decoding System. The instruction
decoding can now be done with simpler circuits in less time.
The Control Unit (CU) now occupies at most 10% of the total
chip area instead of around 60% as with the CISCs. The
simplicity of the CU in turn means greater speed. A smaller CU
means fewer gates and shorter propagation paths with fast VLSI
realization. The space that was saved by the implementation of
smaller CUs was dedicated to large register files (more than
100 registers) . The speed of the RISC CPUs is also due to
their ability to handle interrupts and context switching
internally, eliminating the CPU-memory traffic in this way -
The instruction set of the RISCs was created after an
examination of the way that many HLLs and their compilers
behave. The designer tries to reduce the time that a CPU
spends in loops and subroutine calls. All the operations are
performed on the contents of the registers in the register
file where the data items are kept, thus minimizing the memory
accesses .
The size of the register file is always a subject that
will split the computer designers into two categories : those
who support a big register file and those who insist that a
relatively small register file is enough. They are both right
and wrong because each structure has its advantages and
disadvantages [TAB90] . Some of the disadvantages happen also
to be general disadvantages of the RISC architecture.
In the case of a small register file, many intermediate
results will have to be stored in memory, resulting in
increasing the number of memory accesses (exactly the opposite
of what RISC promises) . There will not be an adequate support
for subroutine calls and interrupt handling (the use of a
stack will be needed) and the ability to use the CPU in
multitasking environment will get minimized.
On the other hand, a large register file will need longer
access time, more space and, if window policies are used,
complicated CPU logic to address the window pointers on a
context switch or a subroutine call state.
An inseparable disadvantage of the RISC is the small
instruction set. With the availability of only a small number
of instructions, the programmers or the compilers have to use
two or more instructions to describe a procedure which could
be described with a single instruction using the CISCs
instruction set, thus making the average code size 50% larger
than the one written in CISC. The larger the code the more
memory space it wiil need. The instruction traffic between the
CPU and the memory will alsobe increased.
The size of the instruction set is a rather subtle
subject and even today there continues to be a lot of research
-3-
in this area. Some companies that manufacture RISCs, provide
rather complex instruction sets with 150-200 instructions,
reaching the state to be considered CISCs rather than RISCs.
It is true that both CISCs and RISCs have crossed the
limits of their area and they have borrowed some features from
each other. Maybe in the future we will see microprocessors
that will combine all the positive characteristics from both
architectures and they will have diminished the drawbacks that
are now associated with each of them.
-4-
2 Architecture and Organization
The architecture that we developed for this thesis
complies with most of the aspects of a RISC architecture, as
they were mentioned in the previous chapter, in the followingaspects : the number of instructions, the instruction formats,
the addressing modes, the load/store architecture, the uniform
fetch cycle, and the standard length of all instructions which
is equal to the basic system word length and the data bus
width. In this chapter, after a short explanation of the
reasons that led us to name our RISC "primitive", an extended
description of the architecture is given. Because there are
examples written in assembly language, the reader should also
refer to the third chapter where the instructions are
explained more thoroughly.
2 . 1 Why"primitive"
According to the previous chapter, a RISC architecture
must exhibit some characteristics that distinguishes it from
the CISC ones. Even if our architecture implements most of
these characteristics, it also lacks some important ones that
every RISC machine happens to have.
Pipelining is one of them and the most important one. Our
system doesn't support any pipelining for the sake of
simplicity. One of the great advantages of the pipelined
systems is the high speed due to the simultaneous fetch and
execute cycles (of consecutive instructions) . It incorporates,
however, some drawbacks which our architecture was supposed to
take care in the case that the pipelining was implemented.
These drawbacks are shown in the form of program code below
and explained later :
a) SBB A,B ; A = A - B - CF
; Jump to address if Carry Set
; Move X to Y
SBB A,B
JC address
MOV X,Y
CLCF
LDX (address)
b) CLCF ; Clear Carry Flag
; Load X with the
; contents of address
ADC X,Y ; X = X + Y + CF
In the first example, the last instruction is fetched
while the one before it, it is being executed. Because the
latter is a branch instruction and the flow of the program may
change, there may be no need to execute the last instruction,
which has been already fetched and consequently it must be
flushed. Some assemblers change the sequence of the
instructions and place after the branch instruction an
instruction that was before it, without affecting though, the
-5-
intended program operation. This instruction will be executed
even in the case of a successful branch, since it will have
been prefetched, but now some mechanism will have to delay thebranch execution until the already fetched instruction gets
executed first. This delayed branch technique is quite
complicated and along with the reason that follows, became the
motive not to use any pipelining in our system.
The second case is more obvious than the first one since
the LDX instruction takes two (2) execution cycles to load the
X register while the next one (ADC) takes only one and it
needs the new contents of X to produce the right result . To
visualize the problem, here are the steps of the execution of
each instruction:
LDX FEE
ADC F E
where F means Fetch cycle and E means Execution cycle. Most of
the RISC machines today overcome the above problem with a
method called scoreboarding. Without any further explanation
on that, the result is shown below, where as we can clearlysee the execution of the ADC instruction is held until the
load instruction completes its execution :
LDX FEE
ADC F H E
Besides a pipeline which can be used in CISC systems, but
is a must in the RISC ones, another powerful feature which is
also not implemented in our case is register windowing. With
this technique, the microprocessor divides its total number of
registers into register windows (blocks) and dedicates each
one of the windows to a procedure. The register window has the
space to keep the local variables as well as some space which
is accessible by two consecutive register windows and keeps
the variables that are common to two procedures (one nested to
the other), passed parameters or global variables. In this
way, the only thing that has to be done by the microprocessor
every time a new subroutine is called, is to advance the
pointer that points to the base of a new register window. Our
machine cannot support this feature because it has only eight
(8) registers -this is another disadvantage since all the RISC
systems have at least 32 (MIPS R2000)-and each time that a
subroutine is called we have to push the registers we want to
save into the stack.
Finally, we have to mention that our CPU lacks any
instructions or external pins that can make it capable of
working in a multiprocessing environment or even to host a
supervising program, such as an operating system, that can
permit multitasking.
-6-
2 . 2 General System Description
The microprocessor and the main memory compose the system
under simulation. A data and an address bus run between them,
both 16-bit long, with some additional lines that carry the
control signals. There are also four other lines (RESET, /INT,
INTA, CLOCK) used for interrupt handling and processor timing.
The whole system is a 16-bit machine with each byte in
memory individually addressed. The CPU's external pins are the
following:
16-bit, tri-state, bidirectional bus for
the data transfer to/from the memory or
other I/O devices. (I/O)
16-bit, tri-state, unidirectional bus,used to carry the memory address. (O)
If HIGH, a load/store operation of a
word (16 bits) will take place. If LOW
then only a single byte will be read or
written from/to the memory. (0)
Stands for Valid Memory Address . Becomes
HIGH when the address bus contains a
valid memory address. (0)
A HIGH pulse on this line for at least
three clock cycles will reset the
CPU. (I)
A LOW pulse on this pin detected at the
end of an instruction execution cycle
will grab the CPU's attention for an
ongoing interrupt request. (I)
With this signal the CPU acknowledges
to the I/O device that its interrupt
request has been accepted and it will be
processed. (0)
LOW level active read pulse for reading
data from the memory. (O)
LOW level active write pulse for writing
data to the memory. (0)
Input signal that will permit us to map
the desired clock period for the CPU
operation. (I)
Input signal that becomes LOW during a
memory read or write cycle until the
memory gets ready to accept the data
from the bus or put the data on the
bus. (I)
where (I) means Input and (0) means Output line.
a) Data bus
b) Address bus
c) WORD
d) VMA
e) RESET
f) /INT
g) INTA
h)/RD1
i) /WR
j ) CLOCK
h) MEMRDY
aIn the remainder of this document the /RD and /WR signals
will be mentioned as RD_bar and WR_bar respectively.
-7-
> IN
Cdpo 13
2:
ISLU
//\\ /
A
\_t
0in
>- t-,_
LO-4 t^ut:V O Z LU
~
Vcn LU CD LU
-3
to => z cn
=3
CD
CD
CO
A
O
CX cnec
LU
az 0
O
/
0
a
CX
cc
D
CE
O 1" lKkN\/
> 3C Ice |3E
=3 S
iC c
(_JUJ z
O1
LU crr2
z cn 1 i-S
Z3 LU z zUj CC
CC cr t-^ ?= =
cr cdt-
er.-i
3E
0
r
Figure 2 . 1 System Under Simulation
-8-
The control signals that are used for the properCPU-
Memory connection are not routed directly to the memory
modules but they first pass through some additional logic (see
Fig. 2.1) which is essential for generating the signals to
access a single byte or a word from the memory.
This additional logic is called the memory bank select
unit and the exact gate level design of this module is given
in figure 2.2. It generates different write control signals
for the two memory banks, one for the even addresses-
represented by memory bank #1 -
and one for the odd ones-
memory bank #2 - (Fig. 2.3).
VMPO 1> OVMR
RDO--ORD
R0DR<0>O-
>r^H
HRO- >>WORDO
=L>
-OWRl
O
-OWR2
Figure 2 . 2 Memory Bank Select Logic
There is another circuit between the CPU and the memory,
namely the CPU-Memory Handshaking Unit, that generates the
MEMRDY signal during the memory access cycles and it is
responsible for the proper timing of the buses during memory
reads or writes. This circuit depends on the type of the
memory that the system has . In order to provide the right
timing, it has some other inputs-
usually some jumpers - that
specify the number of wait cycles.
CPU
A/ DfiTR BUS <15i0>
.11!
.X
ADDRESS BUS <15i 1>
"X "7>
IEM0RY
BANK
1
\.BDDB1>
IB
HEMORT
BANK
SELECT
UNIT
-r
P
MEMORY
BANK
*2
TT wm
Figure 2 . 3 Memory Banks and Signals
-9-
If during the memory access the MEMRDY signal remains LOW
after the end of the second clock cycle, then T wait states
are inserted until it becomes HIGH. For more information refer
to paragraph 2.3.
The memory can look like figure 2.4a where all the data
items are aligned in such a way that they do not cross word
boundaries. In the case that a word is stored, it is divided
into two consecutive bytes and it is shared by both memory
banks with the MSByte stored in bank #1 and the LSByte stored
in bank #2 (Fig. 2.4a) . The above scheme, however, is not
clear to the user, who thinks that the memory is a continuous
space, where the MSByte of a word is stored in the low order
address and the LSByte in the immediately higher (Fig. 2.4b) .
Nevertheless, it should be clear that words can be saved only
at even memory addresses (e.g. 00H, 02H, 04H...).
From the address bus only fifteen out of the sixteen
l-BRNK 1
15
BANK *2-\
0
OQ H
02
04H
Q6H
08H
QRH
0C
0E
Byte 1 Byte 2
Wore 1
Worei 2
Byte 3 Byte 4
Byte 5 Byte 6
Woni 3
Wor<i 4
Q2
mH
Q6H
08
Byte 1
Byte 2
Hord 1.
Word 1
Word 2
Word 2
Byte 3
Byte 4
Word 3
Word 3
MSByte
LSByte
MSByte
LSByte
MSByte
LSByte
Figure 2.4a Word and Byte organization Figure 2.4b
lines reach the memory banks, giving a total addressable space
of2x215
bytes or215
words. The line that carries the least
significant bit (LSb) of the address, goes to the memory bank
select unit and is used along with the signal WORD to choose
either a word or a single byte to access which may be at an
odd or even address. The instructions that use a write cycle
to the memory are given in Table 2.1 with the WORD and
address' LSb combination at each case and the byte that gets
overwritten. Every time that a byte is to be written to the
memory, a 16-bit data value is placed on the data bus with its
LSByte or MSByte containing the byte that is to be stored. The
memorybank select unit with the help of the
address'
least
-10-
significant bit and the signal WORD allows in this case onlyone memory bank to change its contents -at the address that
the address bus indicates-, finally resulting in storing onlythe desired byte of the data bus.
Byte (B) to be
overwritten
Instr WORD Addr<0> <15:8> <7:0>
STW 1 X B B
STB,L 0 1 B
STB,H 0 0 B
Table 2.1 Memory write instructions
The memory read cycle always asserts the signal WORD to
HIGH, thus a whole word is read each time, even in the cases
that a single byte is to be read (Fig. 2.2) . This time the CPU
decides internally which byte to keep, after the contents of
the data bus have been loaded into the Memory Data Register
(see chapter 4 for more explanation on internal CPU
structure) . The memory access read/write protocol is shown in
figure 2.5 (see next page for farther description) .
Reed Cycle (Word)
DflTR
VMfl
RD
RR
WORD
yooooooocv xyyy
yxvxxy xxxx
y X
X y
y X
Write Cycle (Word)
noiH vrxwyy vyyyyyy
H[ii)H|-'<*;ywxxv xxxx
vmh y x
HU
HH \ /
WORD / "V
DflTR
VMR
RU
HR
WORD
Write Cycle
(Odd Byte)
Yxwra XXXXXXX
wrara xxxx
xxxxxx/ xxxxx
y x
\_ y
DflTR xxxxxx
Write Cycle
(Even Byte)xxxxxxx"
R0DRE5SXSXXXX
RDDR<D>XXXXXX\
VMR /
RD
WR
WORD
X.
xxxx
/XXXX
>^
y
Figure 2 . 5 Memory Read/Write Protocol
-11-
2 . 3 System Bus Timing
The bus cycle consists of three (3) clock cycles, namely
T1 to T3, and an undetermined number of wait cycles T. The
wait cycles are inserted when the CPU has to deal with a slow
I/O or memory module. There are also some idle states, Tbetween the bus cycles (Fig. 2.6) when the bus is not used.
IWalt etatee while weltingfor memory or I/O interface
to reepond .
Tl|T2|Tw|T3|Tl|T2|T3 T1|T1 Tl |T2|Tw|Tw|T3 Ti Tl|
dock n_rijnjij"Ljnj"ijnjijnjx^
r Idle etotee between
bus cycles
Figure 2 . 6 Sequence of Bus Cycles
There are different events that occur during these bus
cycles for a memory read and a memory write :
a) read cycle : At the LOW-to-HIGH transition of the
clock in Ti cycle, the address is transferred to the address
bus . After time tSETUP that the address needs to get stable ,
the VMA signal goes HIGH and tD after that the RD_bar signal
is asserted. During the T2 cycle, the data are expected on the
data bus, along with the MEMRDY signal from the CPU-Memory
Handshaking Unit, which is asserted t0 nanoseconds after the
assertion of the RD_bar signal and denotes that the data are
ready and stable on the data bus. If the MEMRDY signal has not
been received till the end of the second cycle (T2) , T cycles
are inserted. Upon reception of the signal, always at the
beginning of T3, the data are stored in the Memory Data
Register and the RD_bar and VMA signals get deasserted and the
address bus returns in the high impedance state after time
t0TD .
b) write cycle : In the write cycle, at the LOW-to-HIGH
transition of the clock in Tir the address is transferred to
the address bus and the data to the data bus. The VMA is first
asserted after time tSETUP and then the WR_bar signal after time
tD from the time that the VMA was asserted. During the T2
cycle, the MEMRDY signal is expected and, again, Tw cycles are
inserted if it remains LOW longer than the period of T2 cycle.
The MEMRDY signal is asserted HIGH at the beginning of the T3
bus cycle and after zero or more T cycles have been inserted
according to the jumper configuration. After it is received
from the CPU, the address and the data are removed from the
address and data buses respectively, and the VMA and WR_bar
signals are deasserted. All of the above are described in
figure 2.8. tA, t0, t0TD and t are memory dependent timing
-12-
characteristics as they appear in figure 2.7 and explained in
table 2.2. tSETOP and tD are bus standards and depend on the
physical implementation of the bus.
RDDRE5S-
C5.
DRTR.
-tfi-
tD
^
tSETUP to
<
- tOTD
READ CTCLE
HDDRES
WR
DAT~!
tH-
tD
,5FTUP
WRITE CTCLE
>
Figure 2 . 7 Memory Timing Characteristics
Read Meaning
tA Access Time
t0 Output Enabled to Output Valid
t0TD Output 3-state from Deselection
Write Meaning
tw Write Time
Table 2 . 2 Timing Characteristics and their Meaning
CLOCK
ADDRESS
VMR
TO
Tl I T2 I T3
DflTR
MEMRDT XXX)
o
RERO CTCLE
CLOCK
RDDRESS
! Tl ! T2 I T3 I
VMR
_ _
ORTR ^
memrdt xyyi
>
WRITE CTCLE
Figure 2 . 8 System Bus Timing
-13-
2 . 4 The Memory Organization and the Stack
We took a glance on the memory in paragraph 2 . 1 where it
was also first told that the memory is byte and word
addressable and occupies2x215
bytes. The exact organization
of the memory space is given in figure 2.9. The first four (4)
words of the memory contain the addresses of the interrupt
service routines. The next six (6) words are used for mapping
I/O addresses, like a PIA and a UART in our case. The next six
(6) word locations are reserved for possible system expansion,
and immediately after these, exists the space for a Monitor
Program as well as the space for the
interrupt service routines while the
remaining space of the memory is
available to the user. In our case
there is no Monitor Program but
there are some simple routines for
interrupt service . The user should
place his code starting from address
0300H which is the address that the
CPU loads into the Program Counter
after a RESET. This address can be
changed by the user by changing the
contents of the memory locations
$207h and $209h which contain the
MSByte and LSByte of the address
respectively (see next paragraph) .
The Program Counter is always
incremented by two (all the
instructions are 16-bits) and it
stops only when it meets the HLT
command. After the execution of this
command, the CPU remains idle until
it is again externally reset.
The stack is organized in words
and not in bytes. The Stack Pointer
(an internal CPU register) always
points to even addresses, starting
with the address that will be first
loaded into it and represents the
top of the stack. Once the Stack
Pointer is loaded with the first
address (Top of Stack) there is no
limitation of the space that the
stack is supposed to include.
Therefore the programmer should be very careful in the use of
the stack because it may collidewith other segments (data or
code) after extensive use. For loading or storing the Stack
Pointer, there have been incorporated two commands, LDSP (Load
the Stack Pointer) and STSP (Store the Stack Pointer) where
the former loads the Stack Pointer with the contents of a
register and the latter stores the contents of the Stack
15 8,7 0
eo. R...t
02. Interrupt Request
GU. Opcoda Error
06. Rddreea Hleellgnnenl
08, PIR Control/Stotul Reg
BR PIR Deto Reg.
0C> URRT Receive Doto Rag.
BE. URRT I.ll Deto Rag.
10. URRT Control Rao.
12. URRT Statue Rag.
m. Heaarwad
16. Raaarwad
IB. Raaarwad
1R, Raaarwad
1C, Reaarvad
1E Raaarwad
20.MONITOR
PR0GRRM
lrE(239 Word.)
260.Interrupt
Sarwlce
Routlnaa
2FE
306.
Uaar'a Speca
161.768 Butaa)
FFFE,
Figure 2 . 9
Memory Organization
-14-
Pointer to a register. We need to store the Stack Pointer in
the cases that we use multiple stacks and we shift from one to
another during a program execution. The LDSP command can also
be used to create multiple stacks in the memory area. The
stack is useful for saving the CPU registers (R1-R7 and PSW)
in the case of a subroutine call or when we need to
temporarily save one of the registers and use it for another
task.
Every time that something is stored in the stack, the
stack pointer gets decreased by two, pointing to the next
available location. Once something is popped off the stack,
then the stack pointer gets first increased by two and then
the data that it is pointing to are popped off (Fig. 2.10)
1FEH
1FCh
2Oh
(topi
PUSH Rl
=>
(bo t ton)
SP =01FEh
R1=07h
R2=FFEFh
1FEh 07h
IFCh
*
2 0H
IFEh
IFCh
POP R2
\
SP=01FCh
R107h
R2=FFEFh
y>
20ri
SP=Q1FEh
R1-07h
R2=07h
Figure 2.10 Stack Operation
2 . 5 Exception Handling
One of the most important features of a microprocessor
today is its ability to handle interrupts. Interrupts are
special actions taken by the CPU whenever certain conditions
exist within a program or the computer system. There are two
general classes of interrupts. The external interrupts that
are usually caused by the user or I/O devices and the internal
interrupts which are caused by a CPU malfunction due to an
unrecognizable opcode, an overflow or a stack violation.
Each interrupt can be either maskable or non-maskable
depending on how important this interrupt is for the CPU. The
maskable interrupts can be suspended by the use of a special
Flag in the PSW, the Interrupt (Disable) Flag. If the system
has more than one maskable interrupt, then a special mechanism
has to be provided for interrupt priority handling. In our
case there is only one maskable interrupt going to the CPU,
-15-
which is not an extraordinary case, especially when there is
only one interrupt source in our system (i.e. us)
The non-maskable interrupts have always the highest
priority and in our system the following exist :
(a) RESET : It is an external interrupt which initializes the
CPU and starts up the program execution upon the activation
(HIGH) of the RESET pin. The RESET signal is required to stay
HIGH for at least three (3) clock cycles. Once the RESET
interrupt is detected, the CPU clears all the Flags except the
Interrupt Flag which is set to HIGH, zeroes the registers of
the register file and loads the Program Counter with the
address contained in the memory location 00H. This address has
saved the number 0200H which is the address of the interrupt
service routine for the RESET. Inside the routine the
Interrupt Flag is cleared and the program is transferred to
the location where the user's program begins. The contents of
this routine could look like this :
ADDRESS INSTRUCTION
$200 STPSW Rl Rl <- PSW
$202 AND Rl, 01111b , IF <- 0
$204 LDPSW Rl PSW <- Rl
$206 LDHI Rl,03h Rl <- 0300H$208 LDLO Rl,00h
$20A JMP ALW,R1 Jump to (Rl)
(program code)
(b) opcode error : raised when an invalid opcode is read into
the instruction decoder or when an invalid combination between
the opcode and the IMM and SIGN fields is present. The Program
Counter is loaded with the contents of the memory address 04H.
(c) address misalignment : raised when we try to access an odd
memory locationwith the LDW or STW instructions that operate
only on even addresses. (PC <-(06H) )
The interrupt request line of the CPU (/INT) represents
the only maskable interrupt that our system has . It is a low
level active signal and it is examined by the CPU at the end
of the execution of each instruction. If it is found stable at
the LOW level then the following events occur :
(1) If the Interrupt Disable Flag is at logic one (IF=1)
the interrupt request is ignored.
(2) If the Interrupt Flag equals zero, it is set equal
to 1 to prevent further interrupts from occurring
until the interrupt service routine starts
processing the present.
(3) The current contents of the Program Counter are
stored onto the stack.
-16-
(4) The PSW is stored onto the stack.
(5) The CPU reads the contents of the memory location
02H which become the new Program Counter (PC) .
(6) The program execution continues with the code
pointed by the new PC (start of the interrupt
service routine) .
One of the first instructions inside the interrupt service
routine should be the modification of the Interrupt Flag so
that a new interrupt request can be processed, thus supporting
nested interrupts. The last instruction before the return of
an interrupt service routine should always be :
POP PSW
Because there is not a return from interrupt (RETI)
instruction which would pop off the stack both the PSW and the
stored PC, the programmer must use the above instruction and
restore the flags to the state they were before the interrupt
request .
In the case that a new interrupt request is being issued
before or after the above "POPPSW"
instruction, that pops
the flags, gets executed, the CPU will follow the normal
operation of servicing the interrupt. This will include the
saving of the flags and the program counter, which will now
show the address of the above instruction or the one after it,
into the stack and the calling of the interrupt service
routine (this one will be nested to the previous) . Upon
completion of the execution of the new interrupt request, the
service routine will pop off the flags and the program
counter, and will continue by returning the execution to the
old interrupt service routine which, by its turn, will again
pop off the flags and the program counter continuing with the
initially interrupted program.
-17-
3 The Instruction Set
Trying to follow the RISC designing rules, an instruction
set was created with only twenty five (25) instructions from
which only the load/store and push/pop instructions can
directly access the memory during the execution cycle. The
remainder of the instructions have to operate between
registers or registers and immediate data.
3 . 1 The instructions and the fetch cycle
The instruction set includes instructions for data
manipulation -arithmetic and logical-, memory handling,program flow control and stack support (Table 3.1) . The data
have to be integer numbers (always considered as 2's
complement) in the range (-215,215-1) . Our system has no
floating point manipulation or string handling facility.
All the instructions are 16-bit long, equal to the
system'
s word, thus providing a uniform fetch cycle of three
stages as follows :
1) Load the Memory Address Register with the
contents of the Program Counter.
2) Load the Memory Data Register with the contents
of the memory location pointed by the Memory
Address Register . (Memory Access Cycle)
3) Pass the instruction contained in the Memory Data
Register to the instruction decoder and the
operands to temporary registers . Increase the
Program Counter by two (2) .
The execution cycle is much more complicated and it is
also instruction dependent. In the next chapter, the different
micro-operations of each instruction are given.
In table 3.1, the instructions and their actions are
shown. Rd, Rsl and Rs2 represent the CPU registers RO to R7 .
Rd is the destination register and the Rsl and Rs2 are the
source registers. In some instructions, the Rd register is
used to encode the register to be pushed or popped to/from the
stack (push, pop) and the Rsl register to encode the branching
conditions (jmp) .
3 . 2 The instruction formats
There are three kinds of instruction formats. The
register-source, theshort-immediate and the long-immediate.
The function of the each one is shown below in figures 3.1,
3.2 and 3.3 respectively- The only common elements between the
three instruction formats are the opcode and the destination
register bit fields. The opcode field has five (5) bits and
can encode up to 25(=32) different instructions while the
-18-
INSTRUCTION ACTION TAKEN IMM SIGN CODE
1 . Add with Carry
2. Subtract with
3. Logical AND
4 . Logical OR
5. Logical XOR
Rd <-
Rd <-
Borrow Rd <-
Rd <-
Rd <-
Rd <-
Rd <-
Rd <-
Rd <-
Rd <-
Rd <-
Rd <-
Rd <-
Rsl + Rs2 + CF 0 0 ADC
Rd + (IMm1) + CF 1 0
Rsl - Rs2 - CF 0 0 SBB
Rd - (IMm) - CF 1 0
Rsl AND Rs2 0 0 AND
Rd AND (IMm) 1 0
Rd AND (Imm2) 1 1
Rsl OR Rs2 0 0 OR
Rd OR (IMm) 1 0
Rd OR (Imm) 1 1
Rsl XOR Rs2 0 0 XOR
Rd XOR (IMm) 1 0
Rd XOR (Imm) 1 1
6. Shift Left Log. Imm. Rd <-
(imm3) *SHL 1 0 SHLL
7. Shift Right Log. Imm. Rd <-
(imm) *SHR 1 0 SHRL
8. Shift Right Ar.Imm. Rd <- (imm)*SHR 1 0 SHRA
9. Load Word Rd <- M[Rsl +Rs2]4 xb
V LDW
10. Load Byte Rd <- M[Rsl + Rs2] X 0 LDB
(sign extended) X 1
11. Load Imm. High Rd <-(IMM, SIGN, Rsl,,Rs2)
(,D1
D LDHI
12. Load Imm. Low Rd <- (IMM, SIGN, Rsl,,Rs2) D D LDLO
13. Load PSW PSW <- Rd X X LDPSW
14 Store Word M[Rsl + Rs2]<- Rd X X STW
15. Store Byte (LSB)
(MSB)
M[Rsl + Rs2]<- Rd 0
1
X STB
16. Store PSW Rd <- PSW X X STPSW
17. Branch PC <- Rd
Rsl Condition
000 Always
001 On Carry010 On Overflow
011 On Negative
100 On Zero
101 On No Overflow
110 On No Carry111 On Positive
18. Call Subroutine
19. Return
(SP)
SP
PC
SP
PC
<- PC
<-
<-
SP
Rd
- 2
<- SP + 2
<- (SP)
JMP
CALL
RET
Table 3.1 The Instruction Set
integer in range (0,63)
2Integer in range (-32,31)
3Integer in range (1,8)
4M[Rsl+Rs2] means "the contents of the memory location pointed
by the number which is the sum of Rsl andRs2"
sBinary number is not considered (it can be any)
6IMM, SIGN, Rsl and Rs2 fields (see instruction formats) contain
the 8-bit immediate data
7D means that the IMM and SIGN 1-bit fields are considered as
Data
-19-
15 11 10 B 7
opcode Rd I nned 1 e te-8
opcode
Immediate-8
IMM
SIGN
5-bit field with the binary representation of the mnemonic
of the instruction.
8-bit field with immediate data. Now the IMM and SIGN 1-bit
fields contain the two MSbits of the data.
In the above instruction format it is not used, but instead,data are contained.
As the IMM 1-bit field, it is not used but it contains part of
the 8-bit immediate data.
Figure 3.3 The long-immediate instruction format
destination register field contains three (3) bits and it can
address up to eight (8) registers.
Once we have seen now the instruction formats, we can
explain why a single mnemonic is used in cases where two or
more actions may be taken (e.g. ADC, SBB, LDB) , in Table 3.2.
The opcode, independent of the action, is always the same.
What may change is the IMM and SIGN 1-bit fields in some
instructions, or the Rsl 3-bit field in some others. This
depends on the syntax of the instruction when it is written in
assembly language. For the case of the branch instruction for
example, the opcode is always constant (01111B) and the
condition is given by the 3-bit field Rsl. Here are some
commands in assembly and machine language respectively.
Observe the way the assembly instructions are translated
according to their syntax :
Assembly
JMP C,R7
JMP ALW,R7
ADC R7,R5,R2
ADC R7, 011011b
XOR R7,R5,R2
Machine Language
opcode Rd IS Rsl Rs2
01111 111 xx 001 xxx ; Jump on Carry Set
JMP R7
01111 111 xx 000 xxx
JMP R7 ALW
00000 111 008101 010
ADC R7 R5 R2
00000 111 10 011 011
ADC R7 Immed-6
11100 111 00 101 010
XOR R7 R5 R2
to the address
contained by R7
Jump Always to
the address
contained by R7
R7 = R5+R2+CF
R7 = R7+01BH+CF
R7 = R5 XOR R2
8SIGN bit has to be always zero in ADC and SBB instructions
-21-
20. Push to Stack (SP) <- Rd
SP <- SP -
Rd
000
Register
PSW
001 Rl
010 R2
Oil R3
100 R4
101 R5
110 R6
111 R7
21. Pop from Stack SP <- SP + 2
Rd
000
Register
PSW
Rd <-(SP)
001 Rl
010 R2
Oil R3
100 R4
101 R5
110 R6
111 R7
22. Load Stack Pointer SP <- Rd
23. Store St ack Pointer Rd <- SP
24. No Operation
25. Halt
PUSH
POP
X V LDSP
X X STSP
VX NOP
X X HLT
Table 3 . 1 The Instruction Set (continued)
15 11 10 6 7 6 5 32
opcode Rd IMM SIGN Rsl Rs2
opcode
Rd,Rsl,Rs2
IMM
SIGN
5-bit field with the binary representation of the mnemonic
of the instruction.
3-bit fields with the addresses of the destination (Rd) and
source registers (Rsl,Rs2).
1-bit field used for immediate addressing. In the above
instruction format it is always zero (0) .
1-bit field that distinguishes if the immediate data is signed
or not. It is always zero (0) in the above instruction format.
Figure 3 . 1 The register-source instruction format
15 11 10 6 7 6 5 0
opcode Rd IMH SIGN Innadlota-6
opcode : 5-bit field with the binary representation of the mnemonic
of the instruction.
Immediate-6 : 6-bit field that contain immediate data.
jMM : 1-bit field used for immediate addressing. In the above
instruction format it is always one (1) .
SIGN : 1-bit field that distinguishes if the immediate data is signed
or not. The immediate data are considered signed if it is one
(1), unsigned otherwise.
Figure 3.2 The short-immediate instruction format
-20-
XOR R7, 111111b, s 11100 111 11 111 111 ; R7 = R7 XOR FFFFBXOR R7 I Immed-6
sign extended
immediate
XOR R7, 111111b 11100 111 10 111 111
XOR R7 Immed-6
R7 = R7 XOR 03FH
The opcode assignment of the instructions is given in
table 3.2.
xxxOO xxxOl xxxlO xxxll
OOOxx ADC NOP SHLL LDW
OOlxx SBB HLT SHRL STW
OlOxx LDB LDPSW SHRA
Ollxx STB STPSW JMP
lOOxx CALL LDHI
lOlxx AND RET LDLO LDSP
llOxx OR PUSH STSP
lllxx XOR POP
Table 3.2 Opcode Assignment
Other instructions can also be implemented, indirectly,
with the specified instruction set. Here are some of them that
one usually finds in the instruction sets of other CPUs:
Instruction
move Rs to Rd
increment Rd
decrement Rd
complement of Rd
negate Rd
clear Rd
exchange Rd and Rs
Implementation
(by our Instruction Set)
Rd <- Rs + R0 (CF=0)
Rd <- Rd + (1D) (CF=0)
Rd <- Rd -
(1D) (CF=1)
Rd <- R0 - Rd (CF=1)
Rd<- Rd XOR (-1D)
Rd<- R0 + RO (CF=0)
Rd <- Rd XOR Rs
Rs<- Rd XOR Rs
Rd<- Rs XOR Rd
3 . 3 The addressing modes
The supported addressing modes are only two
a) Indexed
-22-
i ) Register Indirect
ii) For a Linear byte/word arrayand b) Immediate
This a)-ii case is an interesting way to easily access arrayelements . Suppose for example that R1=0FFH and it contains the
base address of an array with 256 elements. When R2 takes anyvalue between 00H and 0FEH then the instruction :
LDW R5, [R1+R2]
can easily load the contents of any array element into
register R5 . In the case that the array is an array of bytes,we have to use the load byte command (LDB) and specify which
byte we want to keep (MSByte or LSByte) .
The immediate addressing mode is a little tricky, so a
programmer should pay special attention on that part. First,
the destination and the source registers must always be the
same. No immediate data can be longer than 8-bits and in some
other cases they have to be only 6-bit s long. To load a 16-bit
immediate operand into any of the CPU registers, we must use
two in-structions that were incorporated for this purpose
only: LDHI and LDLO. The instruction :
LDHI R4, 1010111b
loads the MSByte of register R4 with the binary number 1010011
leaving the rest of the register unchanged. LDLO performs
exactly the same operation for the LSByte of the registers . In
both cases the operand that is loaded is unsigned i.e. no sign
extension takes place. The instruction format for those
instructions is the long-immediate, where the LSByte of the
instruction contains the immediate data. In the cases, now,
that that the immediate operand is only 6-bit long, the SIGN
field has to be used to show whether the operand has to be
sign extended or not (not applicable in ADC and SBB
instructions) and the IMM field has to be always' 1' (short-
immediate instruction format) .
For example, even though the following two commands have the
same binary number as immediate operands, the actual numbers
that are represented in the logical operation are completely
different :
XOR R3 ,111111b ; R3 = R3 XOR 0FFH(= 63D)
XOR R3, 111111b, s ; R3 = R3 XOR FFFFH(=-1D)
Sign extension can also happen in the case we load a byte
from the memory into any of the registers (with the LDB
command only), but now the data are 8-bit long. The sign
extension doesn't take place in the Add, Subtract and Shift
instructions. For the latter the reason is obvious. What could
a shift left for (-8) times mean? Or should that be translated
as a shift right? But how is then possible to use a shift left
command to execute a shift right operation? Because we wanted
-23-
our instruction set to be non-ambiguous for the compilers, we
prohibited the use of sign extented operands for the abovecommands. So the subtraction can never mean the addition of a
negative number, if and only if the immediate addressing modeis used, and the shift left operation can never be a shiftright for a negative number of times.
Figure 3 . 4 shows how
each instruction affects the
Flags. The Interrupt Flag isnot affected by the
execution of anyinstruction. The only way to
set or clear it, is bystoring the PSW to a
register, modify the
Interrupt Flag bit and then
load back the PSW with the
contents of that register.
Concluding about the
instruction set, we have to
mention that it was greatlyinfluenced by the Berkley's
RISC I & RISC II instruction
sets as they appear in
[KAT83] .
V N
ADC 1 1
SBB 1 1
XOR 0 0
OR 0 0
AND 0 0
LDW 0
LDB 0 0
LDB(S) 0 1
STPSW
LDPSW ? 7 ?
STW
STB
JMP
PUSH
POP
CALL
RET
HLT
NOP
SHLL I I 1 1
SHRA 1 I 1 1
SHRL 1 1 1 I
Figure 3.4 Instruct ions
& Flags
Symbol Meaning
1 Test & Set if True, Clear
Otherwise
Not affected
? New contents depend on
previous ones
In the shifting instructions there is also another
restriction. The immediate data not only have to be positive
integers but they also have to be in the range (1-8) . The
reason for that is because a hardware element called Power
Shifter cannot make more than eight (8) shifts per clock
cycle. Of course, we exclude zero number of shifts because it
makes no sense to use the shift command to make no shifts.
Another group of instructions is the one that includes
the instructions needed for accessing the memory. These are
the STW, STB, LDW and LDB commands as shown in Table 3.1.
These instructions use the register indirect addressing mode
where the address of the memory to read or write is determined
by the result of the addition of the contents of the two
source registers, Rsl and Rs2 . For the instructions that
access a single byte (LDB and STB) we have also to know which
byte this is (MSByte or LSByte), and whether it's going to be
sign extended after its loading from the memory. This
-24-
information is encoded into the IMM 1-bit field where the
binary digit'1'
means the MSByte while the digit'0'
means
the LSByte of the Rd register. Especially for the STB command,
attention has to be paid in its implementation because if the
result of the addition of Rsl and Rs2 happens to be even
number, only the memory bank #1 has to be enabled because it
represents the even addresses, while in the case that the
result is odd only the memory bank #2 has to be enabled. We
have, finally, to say that before the byte has been put on the
data bus it should have the right position in the Memory Data
Register (MDR) to reach the desired memory bank. (For the
exact implementation of the above command, see in chapter 4
the micro-operations of the STB command) .
3 . 4 The Processor Status Word
Another user visible and accessible CPU register is the
Processor Status Word (Fig. 3.5) . Only the five (5) LSbits of
its sixteen (16) bits are used, giving the ability to the user
to modify its Flags with the use of no more than one register.
We have to use a register because there are no instructions
that can access and modify directly the PSW. Therefore, every
time we store the PSW in one of the seven available registers
(remember that R0 is always zero) a modification on any of the
Flags can be made. The PSW can then be loaded with the new
contents of that register. The contents of the PSW can also be
pushed onto the stack as with any of the registers Rl to R7 .
!>MxM>MM>W>ro&<lXiInterrupt Flsg 1
(Int. Disable If 1. Enebla IF Bl
Nsgotlua Flag
(It Is SET on Nsgotius rasultl
Zsro Flag(It Is SET an Zsro raault)
OwsrfloH Flag(It is SET If raault < -2'* op
raault >215
-11
Carry Flog
Figure 3 . 5 The Processor Status Word
There are of course some other ways to modify thePSW'
s
Flags and one of them is by executing some instructions that
we know they affect the Flags, producing dummy results. The
instruction for example :
ADC R0 , R0 , R0
clears the carry flag and sets the zero flag, by executing
only one instructions and without changing the contents of any
register. The following instruction, however, affects (clears)
only the carry flag :
-25-
ADC RO, 000001b
Even if RO is zero after the execution of the instruction, the
intermediate result that the ALU produces is 01H and,
actually, this is the one that affects the PSW's Flags. This
way seems to be faster and smarter but it doesn't work with
all the flags.
3.5 Assembly syntax and instruction encoding
The instruction encoding that we first mentioned in
paragraph 3.2 will now be presented. The complete table of the
syntax of the instructions and their encoding to the machine
language which is in binary representation will be described.
The mnemonics of the instructions that are used for their
representation in the assembly language have already been
given in table 3.1. As everyone knows it is a lot easier to
write a program in assembly than in machine language because
the only things we need to know are the mnemonics and the
syntax of the instructions which will later interpret to the
proper instruction formats and addressing modes . The syntax of
the instructions, thus, is given in table 3.3 with their
encoding to the machine language and some comments about the
meaning of the parameters and the symbols that are used.
INSTRUCTION SYNTAX
1. ADC
SBB
AND
4. OR
XOR
a) ADC Rd,Rsl,Rs2
b) ADC Rd,imm
a) SBB
b) SBB
a) AND
b) AND
a) OR
b) OR
Rd,Rsl,Rs2
Rd, imm
Rd,Rsl,Rs2
Rd, imm
c) AND Rd,imm,s
Rd,Rsl,Rs2
Rd, imm
;) OR Rd,imm,s
a) XOR Rd,Rsl,Rs2
b) XOR Rd,imm
M.S. Byte
76543 210
00000
00000
Rd
Rd
00001 Rd
00001 Rd
10100 Rd
10100 Rd
10100 Rd
11000 Rd
11000 Rd
11000 Rd
11100 Rd
11100 Rd
L.S. Byte
7 6 543 210
0 0 Rsl Rs2
1 0 Immed-6-unsigned
from 000 000 (0D)
to 111 111 (63D)
0 0 Rsl Rs2
1 0 Immed-6-unsigned
from 000 000 (0D)
to 111 111 (63J0 0 Rsl Rs2
1 0 Immed-6-unsigned
from 000 000 (0D)
to 111 111 (63r)
1 1 Immed-6-signed
from 100 000 (-32r)
to 011 111 (31L,)
0 0 Rsl Rs2
1 0 Immed-6-unsigned
from 000 000 <0D)
to 111 111 (63D)
1 1 Immed-6-signed
from 100 000 (-32D)
to 011 111 (31D)
0 0 Rsl Rs2
1 0 Immed-6-unsigned
from 000 000 (0P)
to 111 111 (63D)
Table 3.3 Instruction syntax & encoding
-26-
C) XOR Rd, imm, s 11100 Rd 1 1 Immed6signed
from 100 000 (-32Jto 011 111 (31n)
6. SHLL a) SHLL Rd, imm 00010 Rd 1 0 Immed6unsigned
from 000 001 dD)to 001 000 (8n)
7. SHRL a) SHRX Rd, imm 00110 Rd 1 0 Immed6unsigned
from 000 001 UD)to 001 000 (8ri)
8. SHRA a) SHRA Rd, imm 01010 Rd 1 0 Immed6unsigned
from 000 001 do)to 001 000 <8D)
9. LDW a) LDW Rd, [Rsl+Rs2] 00011 Rd X X Rsl Rs2
10. LDB a) LDB Rd, [Rsl+Rs2] ,h 01000 Rd 1 0 Rsl Rs2
Load High Byte (MSB) unsigned
b) LDB Rd, [Rsl+Rs2] , hs 01000 Rd 1 1 Rsl Rs2
Load High Byte (MSB) signed
c) LDB Rd, [Rsl+Rs2] ,1 01000 Rd 1 1 Rsl Rs2
Load Low Byte (LSB) unsigned
d) LDB Rd, [Rsl+Rs2] ,1s 01000 Rd 1 1 Rsl Rs2
Load Low Byte (LSB) signed
11. LDHI a) LDHI Rd, imm 10010 Rd Immed -8-unsigned
from 0 0 000 000 (0D)to 1 1 111 111 (255D)
12. LDLO a) LDLO Rd, imm 10010 Rd Immed-8-unsigned
from 0 0 000 000 (0D)to 1 1 111 111 (255D)
13. LDPSW a) LDPSW Rd 01001 Rd X X xxx xxx
14. STPSW a) STPSW Rd 01101 Rd X X xxx xxx
15. LDSP a) LDSP Rd 10111 Rd X X xxx xxx
16. STSP a) STSP Rd 11011 Rd X X xxx xxx
17. STW a) STW Rd, [Rsl+Rs2] 00111 Rd X X Rsl Rs2
18. STB a) STB
Load
Rd, [Rsl+Rs2] ,h
High Byte (MSB)
i 01100 Rd 1 0 Rsl Rs2
b) LDB
Load
Rd, [Rsl+Rs2] ,1
Low Byte (LSB)
. 01100 Rd 1 1 Rsl Rs2
19. CALL a) CALL Rd 10001 Rd X X xxx xxx
20. PUSH a) PUSH Rd 11001 Rd X X xxx xxx
21. POP a) POP Rd 11101 Rd X X xxx xxx
22. JMP a) JMP Condition, Rd 01111 Rd X X Rsl xxx
Rsl encodes the condit.ion
23. RET a) RET 10101 Rd X X xxx xxx
24. NOP a) NOP 00001 Rd X X xxx xxx
25. HLT a) HLT 00101 Rd X X xxx xxx
Table 3 . 3 Instruction syntax & encoding (continued)
-27-
4 The Central Processing Unit
The heart of every computer is the Central ProcessingUnit (CPU) . This is the reason that we chose to give a
description of the CPU with more detail than the rest of the
parts of our system. The description has been carried down to
the Register Transfer Level (RTL) where the key component is
a (parallel) register, that is, a storage device for words.
There are also other combinational and sequential components
such as decoders, multiplexers, ALUs, counters and shift
registers and they are usually described as boxes with a
specified operation. Between these boxes runs a group of lines
that carry the data and referred to as buses.
In this level, there is a degree of abstraction, in the
sense that we don't usually see what's inside in each of these
boxes, and quite soon we will see that a box may sometimes
represent more than one component.
4 . 1 The CPU structure
The CPU as an entity is given in figure 4.1. In the first
steps of its design, only the necessary registers were placed
and some units like the Arithmetic Logic Unit (ALU) , the
Control Unit (CU) and the Interrupt Unit (IU) . The registers
that we decided to incorporate are all 16-bit s and are the
following :
i) Memory Data Register (MDR) : holds the data after a
memory read and before a memory write .
ii) Memory Address Register (MAR) : holds the address of the
memory location that we want to write to or read from.
iii) Program Counter (PC) : keeps the address of the next
program instruction to be executed.
iv) Stack Pointer (SP) : it always contains the memory
address that is the next available stack position.
v) ALU Input Registers (Ra,Rb) : they keep the data
that will be used as operands in the ALU operations.
vi) Front End Immediate Register (Ri) : this register loads
the contents of the MDR and serves as a delay stage
before the data reach the Far End Immediate Register.
This delay is absolutely essential because at the same
time that Ri is loaded the instruction decoding is
taking place and we don't know yet which part of the
data is useful or not, or even more if it needs some
further processing.
viii) Far End Immediate Register (Rixnm) contains raw
immediate data after they have been processed during
their transfer from the Front End Immediate Register.
ix) Node Register (Re) : keeps the result of an ALU or PS
(Power Shifter) operation or the contents of other
registers such as the PC and SP .
x) Processor Status Word (PSW) : this register keeps the
-28-
2en
to
?-?J* ??Iv
V
a.
-? tcz
t:
t
LU
CO
LU
DC
cr
zccLU1-
X
LU
LU
o
o
u
a.o
cn
cn
LUcc
oa
a
o
cc
a
CD
(6) U0M
h5t=h5
0-'
Figure 4 . 1 The CPU structure
-29-
flags (Carry, Overflow, Negative, Zero and Interrupt) .
The Power Shifter was mentioned before but it really was
considered as another CPU component in the next steps of the
design where the data paths were assigned and we wanted to
speed up the flow and the processing of the data. The data
paths connect the various CPU components together and they
usually have the so called control points.
A control point is a data path switch which, when
activated by a control signal, allows data to be transferred
over the data path. When inactive, the data path is
effectively blocked. In the case that two or more input data
paths reach a control node (point) ,then we need two or more
control signals to distinguish which data path will be
transferred to the output. So, sometimes a control node may be
not just a single switch but something more complex.
4.2 The Control Unit
ldlo
'RESET
Interrupt
fstch
sxscu ts
Figure 4.2
State Sequence
The control unit implements a
function fe or a group of functions
flf f2, . . . , fn. Every time a function
is executed by the control unit,
there is a sequence of events that
is transferred to the control points
and consequently affects the data
path. The overall function imple
mented by the control unit is that
of the CPU operation as shown in
figure 4.2. It consists of other
sub-functions such as the instruc
tion fetch, the execution of each of
the instructions, the interrupt
services, the memory access and
generally the CPU states. In our CPU
there are four possible states :
idle, interrupt, fetch and execute.
After the power up of the system
(i.e. the RUN signal goes HIGH) the
CPU is always initialized to the
idle state until it is externally
reset. It then enters the interrupt
state until the interrupt service
routine is called and then it
continues by changing alternately
between the fetch and the execute
states, starting always from the
fetch. If during the execution of a
program the HLT command is reached,
then the processor enters the idle
state until it is again externally
reset. If an interrupt occurs it
enters first the interrupt state and
-30-
then it continues by fetching and executing the commands of
the interrupt service routine .
The control unit generates an internal clock which is
distributed to all the other CPU components. When the CPU
executes a memory read or a memory write, this internal clock
freezes until it receives the MEMRDY signal from the CPU-
Memory handshaking unit giving to all the components the
illusion that only one cycle has elapsed while at least three
cycles have occurred in the external CPU environment (Fig.
2.1) .
Inside the control unit there is also an instruction
decoder which is enabled at the third fetch cycle. It
interprets the instruction, the addressing mode and the
operands or conditions that are enclosed in the 16-bit word.
The Control Unit generates some other signals, internal
to it, except the control signals that are shown in figure
4.1. These signals are used for the state coordination or for
the issuing of interrupts, like the four signals that the CU
pases to the IU in figure 4.1. The first of these signals is
the ex_end signal which becomes HIGH after the last cycle of
the execution of every instruction. The second is the
opcode_error signal that informs the interrupt unit that the
opcode field contained an invalid binary representation and
the third and fourth signals are the write_mem and word which
are both used to assert an interrupt condition whenever a word
is attempted to be written to the memory at an odd address.
4 . 3 The interrupt unit
This unit is the portion of the CPU which is responsible
for issuing the interrupts. It has two external inputs, RESET
and INT bar, and four inputs from the control unit. It also
has as Inputs the Interrupt Disable Flag (IDF) bit of the PSW
and the LSbit of the MAR.
Every time that an interrupt is activated, this unit
generates two signals for the control unit. The first one
changes the processor state from idle, fetch or execute to
interrupt and the second signal contains information about the
type of the interrupt (reset, external interrupt, opcode error
or address misalignment) . These two signals may not be
necessarilysingle lines but two or more according to the
number of states that need to be encoded.
For the case of the RESET interrupt, a counter has been
used which is enabled by the LOW to HIGH transition of the
RESET line and once enabled it counts up to three clock pulses
and it finally issues the internal RESET interrupt.
For the external interrupt, the interrupt unit (IU)
always waits for the HIGH state of the ex_end signal. After
this state is reached, the IU checks the INTJbar line. In the
case that it is stable HIGH, no interrupt is issued. In the
case that it is LOW then the IDF is checked to see if the
interrupt is enabled. Eventually, the external interrupt is
issued if there is a request and the IDF is zero.
-31-
The assertion of the opcode interrupt is quite easy since
the signal error is given directly by the instruction decoder
which can be designed as in figure 4.3.
error
Figure 4 . 3 Example of an instruction decoder
Finally for the address misalignment, the interrupt unit
needs three signals. The two first are the write_mem and word
signals from the control unit and the third is the LSbit of
the Memory Address Register (MAR) . Every time that a memory
write cycle is to be performed and the word signal is HIGH
(i.e. a word is going to be written) the LSbit of the MAR is
examined to see if it is one or zero. If it is zero there is
no danger since it points to an even address and all the words
should be stored at even addresses only. In the case, though,
that the LSbit is one, then an address misalignment interrupt
is issued.
4 . 4 The control points
The data path switches as they are depicted in figure
4.1, are responsible for the proper traffic of the data among
the components that assemble the CPU. But some of them are not
only switches but they represent more complex structures such
as decoders, multiplexers or comparators. The control node,
for example, in figure 4.1 that has as inputs the control
signals c7 and c8 is a much more complex structure than it is
shown to be. The operation of those control signals is
described in table 4.1 -
as with every other control signal of
our system-
and the actual design can look like figure 4.4.
Generally, the control nodes with more than one control
signal as inputs, perform a function which is more complex
than that of a switch.
Every control node (point) controls either the transfer
of data or an operation. Table 4.1 shows all the control
points, their control signals and the function that they
encode, and finally the registers or the other units that they
affect. Later, in chapter 5, this same table will make the
sensitivity list for the VHDL processes that will implement
the operation of those registers.
-32-
-iLOAD
C1B
FKIt:
Figure 4 . 4 Control node for c7 and c8 control signals
Memory Data Register
MDR<- Re cl9
MDR<- Data Bus
Memory Address Reqister
c36
MAR<- PC c25
MAR<- SP c26
MAR<- Re c21
MAR<- int vector
Proqram Counter
c23
PC<- PC+2 c22
PC<- Re
Stack Pointer
c24
SP<- SP+2 (c27, c28) = (0,1)
SP<- SP-2 (c27, c28) = (1,0)
SP<- Re c43
Ri (immediate Reqister - front end)
Ri<- MDR cl8
Rimm (immediate Reqister - far end)
(cl2 Cl3,cl4)= (0,0,Rimm
<- Ri 1)
Rimm<- Ri<5:0>,u (cl2 cl3,cl4)
= (0,1, 0)
Rimm<- Ri<5:0>,s (cl2 cl3,cl4)
= (0,1 1)
Rimm<- Ri<7:0>,u (cl2 cl3,cl4)
= (1,0 0)
Rimm<- Ri<7:0>,s (cl2 cl3,cl4)
= (1,0 1)
Rimm<- Ri<15:8>,u (cl2 cl3,cl4)
= (1,1 0)
Rimm<- Ri<15:8>,s (Cl2 Cl3,cl4)
= (1,1 1)
Table 4 . 1 Tranfers and Operations
-33-
Rd
Rsl
Rs2
Rd,Rsl,Rs2
<- MDR<10:8>
<- MDR<5:3>
<- MDR<2 : 0>
External Signals
WR_bar
""
<- LOW
RD_bar <- LOW
WORD <- HIGH
VMA <- HIGH
INTA <- HIGH
Data_Bus <- MDR
Address_Bus <- MAR
Reqister File
Rf (Rd)"
<- Re
Rf(Rd)<15:8> <- Rimm<7 : 0>
Rf(Rd)<7:0> <- Rimm<7:0>
Rf (Rd)<- Rimm
R( (Rd)<-
zeros
c20
c2 0
c20
c30
c31
c32
c33
c34
c37
c35
(Cl5,cl6,cl7)
(Cl5,cl6,cl7)
(cl5,cl6,cl7)
(cl5,cl6,cl7)
(Cl5,cl6,cl7)
(0,0,1)
(0,1,0)
(0,1,1)
(1,0,0)
(1,0,1)
Ra
Ra
Rb
Re
Re
Re
Re
Ra,Rb,Rc (ALU registers-
sources, destination)<-
Rf (Rsl)<-
Rf (Rd)<-
Rf (Rs2)<- ALU bus
<- PS bus
<- PC
<- SP
Arithmetic LogicUnit1
ALU_bus
ALU_bus
ALU_bus
PSW
PSW
ALU_bus<7: 0>
ALU_bus<15: 8>
ALU_bus
ALU_bus
ALU_bus
ALU_bus
ALU_bus
ALU bus<-
<- Ra'
<- Rb vRimm3'4
<- PSW:
<- Ra-
<-Rimm"
<- Ra<15:8>2
Ra
0>2
Rimm)3'4
Rimm)3"1
<- Ra<7
+ (Rb v
<- Ra - (Rb v
<- Ra AND (Rb vRimm)-'4
<- Ra OR (Rb vRimm)3'"
Ra XOR (Rb vRimm)3'"
Ra + (Rb v Rimm)3'4
CF
CF
C7
c8
e9
c40 ; switched i:rom ALU
c41 ; from P . !SHIFTER
c2 9
c42
(el, c2, c3, c4) = (0,0, 0, 1)
(el, c2, c3, c4)= (0,0, 1, 0)
(cl, c2, c3, c4) = (0,0, 1, 1)
(cl, c2, c3, c4) = (0,1,0, 0)
(cl, c2, c3, c4) = (0,1, 0, 1)
(cl, c2,c3, c4) = (0,1, 1, 0)
(cl, c2, c3, c4 ) = (0,1, 1, 1)
(cl, c2, c3, c4 ) = (1,0, 0, 0)
(cl, c2, c3, c4 ) = (1,0,.0, 1)
(cl, c2, c3, c4) = (1,0,,1, 0)
(cl, c2, c3, c4) = (1,0,.1, 1)
(cl,. c2, c3, c4)= (1,1,0, 0)
(cl,. c2, c3, c4)= (1,1,.1,.1)
POWERSHIFTER5
PS bus<- Rimm *
(SHLL(Ra))
PS~bus<- Rimm * (SHRL(Ra))
PS~bus<- Rimm * (SHRA(Ra))
(c5,c6) = (0,1)
(c5,c6) = (1,0)
(c5,c6) = (1,1)
Table 4 . 1 Transfers and operations (continued)
^10, ell must have been set before any ALU operation
2(cl0,cll) = (0,0) None chosen
3(cl0,cll) = (0,1) Rb chosen
4(cl0,cll) = (1,0) Rimm chosen
5The contents of Ra are shifted as many times as the number contained in Rimm.
This number must be greater than 0 and less than 9.
-34-
4.4.1 The immediate registers
This is one of the four sub-paragraphs that follow the
above list with the control signals and their result on the
CPU transfers and operations, having as purpose to clarifysome of the written parts. The assignment :
Rimm <-Ri<5:0>,u
means that Rimm is loaded with the six (6) LSbits of the Ri
register filling the rest of the bits with zeros (unsigned) .
If the Ri register contains the word :
Ri -> 10010110101110101
then the above assignment will have as result the loading of
Rimm with the number :
Rimm -> 00000000000110101
In contrary, the assignment :
Rimm <- Ri<5:0>,s
first checks the MSbit of the 6-bit number (bit 5 of the word)
and then transfers this number to the Rimm register, fillingthe rest of the bits of Rimm with zeros or ones, depending on
that bit . Look what happens for example in the two followingcases (the
'=>'
symbol represents the above assignment) :
Ri = 10010110101110101 => Rimm = 1111111111110101
I
bit 5 is 1
Ri = 10010110101010101 => Rimm = 0000000000010101
I
bit 5 is 0
The same action is taken for the other assignments of data to
Rimm, except that other bit groups are used.
4.4.2 The register file
In the assignments concerning the registers of the
register file, for both loading them and transferring their
contents, the case that may cause confusion is the repre
sentation of the registers of the register file. In loading
any of the registers of the register file we have the
assignment :
Rf(Rd)<- register
-35-
where"register"
can be one of the Re, Rimm or zeros. The lastone is not actually a register but a state which is loaded
into all of the registers during the initialization of the
CPU. R (Rd) means that the destination is the register of the
register file (Rf) that its address is designated by the
register Rd. If Rd for example contains the binary number"001"
then the following assignment will actually take place:
Rl <-register
In the case that the byte is indicated, then only that byte of
the register will change, leaving the rest of the register
unchanged.
4.4.3 The Arithmetic Logic Unit
The Arithmetic Logic Unit (ALU) not only performs the
arithmetic and logical operations but it also transfers data
from/to the Processor Status Word (PSW) or passes the contents
of its input registers to the ALU_bus which is a 16-bit bus
that maintains the data dynamically. After an ALU operation is
complete and the output data are stable on the ALU_bus, the
ALU triggers the LOAD input of the Re register and so the
ALU_bus transfers the data to Re , where they are temporarilystored. ci0 is the control signal that loads the Re register
with the data carried by the ALU_bus and it is (indirectly)
controlled by the ALU and by the control unit (like the c41 is
controlled by the Power Shifter) . The ALU has the ability to
perform any of its operations within one clock cycle and every
operation is triggered by the LOW-to-HIGH transition of the
internal clock. It is performed if any of the control signals
cx to c4 is other than zero.
The sources for the ALU operation are the registers Ra
and one of the registers Rb or Rimm. The control point which
has as inputs the control signals c10 and cxl manages the
latter. As we can see in figure 4.1 two data paths enter the
control point (one from Rb and one from Rimm) but only one
data path leaves it and enters the ALU. It is important to
remember that before any ALU operation that needs any one of
the Rb or Rimm registers (see Table 4.1), c10 and cn must have
been set to the proper combination in order to provide the
proper data to the ALU.
4.4.4 The Power Shifter
This shifter obtained the adjective"power"
because it
has the ability to make from one to eight shifts (left or
right) in just one clock cycle. This important feature of our
CPU speeds up its operation, since shifts are needed for any
multiplication or division operation. In our design the Power
-36-
Shifter (PS) shifts left or right the contents of the Ra
register as many times as the number contained in Rimm. This
number must be greater than zero (0) and less than nine (9)and it is loaded as an immediate operand with the instruction.
Therefore, the checking for the number of shifts (to be within
these limits) must be done during the translation of the code
into machine language. The assembler should always provide an
error in the case that the number of shifts is zero or greater
than eight.
The operation of the PS regarding the storage of the
result looks like the one which we described for the ALU. It
first outputs the result to the PS_bus and once the data get
stable it triggers the control signal c41 and stores the
contents of the bus to the Re register.
4.5 Instruction Decomposition
This was one of the most difficult and time consuming
parts of the thesis project. During the decomposition of the
instructions into micro-operations, the data path inside the
CPU changed several times and more control nodes were added to
give better and faster performance. It is also true that a
VLSI implementation wasn't taken into consideration at this
point .
Each instruction, after it is fetched from the memory
following the steps given in 3.1, must be executed. The
execution cycle is not uniform for all the instructions and it
may be from two (2) to seven (7) clock cycles. When we talk
about clock cycles inside the CPU, as we explained in 4.2,
they may not necessarily coincide with the clock cycles
generated by the clock generator which are common and
uninterruptable to the various components of the system. So,
these two (2) to seven (7) internal clock cycles may sometimes
be less than the external clock cycles by three or more
cycles, when the instruction has to do a memory access and the
internal clock freezes.
In the next pages, every instruction has been decomposed
into micro-instructions . These micro-instructions are given in
ascending order, according to the clock cycle in which they
are executed. If two or more instructions belong to the same
clock cycle and they are separated by the conjunction operator
(A) that means that they can be executed concurrently. If they
are separated by the disjunction operator (V) it means that
only one of them can be executed at that cycle and it depends
on some other data, such as the flags, the branching
conditions, the addressing mode et cetera, about which one
will be (these conditions are also mentioned) . If the micro
instructions are not separated by either the (A ) or the (V )
operator it means that they belong to the same group (i.e.
they are control signals of the same control node or they
belong to the ALU or to the PS) .
-37-
On the right side of the micro-instructions appear the
control signals that they affect. In the cases that theyaffect a group of signals which is assigned to particular
node, then only the signals of that group that change (from 0
to 1) are mentioned. The rest are assumed zero. The control
signals are also separated by the (A ) or the (V ) operators .
Besides these operators there is the minus"-"
operator that
is used to show that the control signal on its left side
should have been set before the control signals on its right
side. To interpret the function of the control signals refer
to table 4 . 1 that describes all the control signals and the
result of their operation. The control signals inside the
parenthesis imply that they are triggered by either the ALU or
the PS through the Control Unit.
INSTRUCTION DECOMPOSITION
ADC - Add with Carry
1. (Rimm <- Ri<5:0>,u A Ra <-
Rf (Rd) )
V (Ra <-Rf(Rsl) A Ra <-
Rf(Rs2))
2. (ALU_bus <- Ra + Rimm + CF)
V (ALU_bus <- Ra + Rb + CF)
3 . Rf (Rd)<- Re
(IMM=1)
(IMM=0)
(IMM=1)
(IMM=0)
SBB - Subtract with Borrow
1. (Rimm <- Ri<5:0>,u A Ra <-
Rf (Rd) ) (IMM=1)
V (Ra<-
Rf(Rsl) A Ra<-
Rf(Rs2)) (IMM=0)
2. (ALU_bus<- Ra - Rimm -
CF) (IMM=1)
V (ALUJDUS<- Ra - Rb -
CF) (IMM=0)
3. Rf(Rd)<- Re
-li
c7
Cl
<=i
c
3A
A
c4
c
if
(C40)
(c40)
AND - Logical AND
1. (Rimm <- Ri<5:0>,s A Ra<-
R (Rd) )
V (Rimm <- Ri<5:0>,u A Ra<-
Rf (Rd) )
2
3
V (Ra<-
Rf(Rsl) A Ra<- Rf(Rs2))
(ALU_bus<- Ra AND Rimm) (IMM=1)
V (ALUjbus<- Ra AND Rb) (IMM=0)
R(Rd)<- Re
-14
(IMM=1, SIGN=1)
(IMM=1,SIGN=0)
=0) c7 A C9
c3
c3
c10 Ci
CiCn
Ci7
(C40)
(C40)
-38-
OR -
Logical OR
1. (Rimm <-Ri<5:0>,s A Ra <-
Rf (Rd) )
V (Rimm <-Ri<5:0>,u A Ra <-
Rf(Rd))
V (Ra <-
Rf(Rsl) A Ra <-
Rf(Rs2))
2. (ALU_bus <- Ra OR Rimm) (IMM=1)
V (ALU_bus <- Ra OR Rb) (IMM=0)
3. Rf(Rd)<- Re
XOR - Logical XOR
1. (Rimm <-Ri<5:0>,s A Ra <-
Rf (Rd) )
V (Rimm <- Ri<5:0>,u A Ra <-
Rf (Rd) )
V (Ra <-
Rf(Rsl) A Ra <-
Rf(Rs2)) (IMM=0)
2. (ALU_bus <- Ra XOR Rimm) (IMM=1)
V (ALU_bus <- Ra XOR Rb) (IMM=0)
3 . R (Rd)<- Re
NOP - No Operation
1. Null
(IMM=3
ci3 c14 A c8
.,SIGN=1)
Cl3
(IMM=1,SIGN=
A c8
=0)
(IMM=0) c7 A c9
o)C10 Ci c3 c4 (c4
Cn~~
Ci c3 c4 (c4 o)
Cl7
(IMM=1
C13 C14 A C8
,SIGN=1)
ci3
(IMM=1,SIGN=
\ ce
=0)
(IMM=0) c7 A c9
Cic~
Ci c2 (c40)
Cn cx c2 (c4(
|c17
)
HLT - Halt
1 . proc_state<- idle
STPSW - Store Processor Status Word
1 . ALU_bus <- PSW
2 . Rf (Rd)<- Re
LDPSW - Load Processor Status Word
1 . Ra <-
Rf (Rd)
2 . PSW <- Ra
LDHI - Load immediate High
1. Rimm <- Ri<7:0>,u
2. Rf(Rd)<15:8><- Rimm<7:0>
LDLO- Load immediate Low
1. Rimm <- Ri<7:0>,u
2 . Rf (Rd) <7 : 0> <- Rimm<7 : 0>
c; c4
c17
|c7]
fil
c12
Cl6
c12
Cl6 Cl7
(c40)
-39-
JMP -
Jump (conditional or not)
1 . Ra <-
Rf (Rd)
2 . ALU_bus <- Ra
3. MAR <- Re A PC <- Re
(if condition is true)
STW - Store Word
1. Ra <-
R(Rsl) A Ra <-
Rf(Rs2)
2 . ALUJbus <- Ra + Rb [cTT3 . MAR <- Re A Ra <-
Rf (Rd)
4 . ALUJbus <- Ra
5 . MDR <- Re
6. write_mem<- '1'
(write to memory)
LDW - Load Word
1. Ra <-
Rf(Rsl) A Ra <-
Rf(Rs2)
2 . ALUJbus <- Ra + Rb
3 . MAR <- Re
4. read__mem<- '1'
5 . Ri <- MDR
6 . Rimm <- Ri
7 . Rf (Rd)<- Rimm
STB - Store Byte
1. Ra <-
Rf(Rsl) A Ra <-
Rf(Rs2)
ALUJbus <- Ra + Rb
MAR <- Re A Ra <-
Rf (Rd)
-ii
5
6
ALUJdus<- Ra (MSB, MAR (0) =0)
V ALU_bus<7:0> <- Ra<15:8> (MSB, MAR (0) =1)
V ALU_bus<15:8><- Ra<7 : 0> (LSB,MAR(0) =0)
V ALUJdus<- Ra (LSB,MAR(0)=1)
MDR<- Re
write mem<- '1' (write to memory)
LDB - Load Byte
1. Ra <-Rf(Rsl) A Ra <-
Rf(Rs2)
2 .ALUJdus
<- Ra + Rb
3 .MAR <- Re
4. read_mem<- '1'
5 .Ri <- MDR
c8
c (C40)
c21 A c24
(c40)
(c40)
-14
C4 (C40)
c2 c3 (c<
c2 c3 C4
C4 (c40)
<c40)
-7A
c2 c3
C21
(c40)
-18
-40-
Rimm <- Ri<15,8>,u
Rimm <-Ri<15:8>,s
Rimm <- Ri<7:0>,u
Rimm <-Ri<7:0>,s
Rf (Rd)<- Rimm
(IMM=1,SIGN=0)
(IMM=1,SIGN=1)
(IMM=1,SIGN=1)
(IMM=1,SIGN=1)
LDSP - Load Stack Pointer
1 . Ra <-
Rf (Rd)
2 . ALUJdus <- Ra
3 . SP <- Re
STSP - Store Stack Pointer
1 . Re <- SP
2 . Rf (Rd)<- Re
CALL - Call Subroutine
1 . Re <- PC A Ra <-
Rf (Rd)
2 . MDR <- Re A MAR <- SP A ALUJdus <- Ra
3 . write_mem<- '
1'
4 . PC <- Re A SP <- SP - 2
RET - Return from Subroutine
1 . SP <- SP + 2
2 . MAR <- SP
3. read_mem<- '1'
4 . Ri <- MDR
5 . Rimm <- Ri
6 . ALUJdus <- Rimm
7 . PC <- Re
SHLL - Shift Left Logical
1. Rimm <- Ri<5:0>,u A Ra <-
R (Rd)
2. PSJdus <- Rimm * (SHLL(Ra)
3. Rf(Rd)<- Re
SHRL - Shift Right Logical
1. Rimm <- Ri<5:0>,u A Ra<-
Rf (Rd)
2. PSJbus <- Rimm * (SHRL(Ra)
3. Rf(Rd)<- Re
c12
Cl2
c12
c12
Cl5
-13
-14
(c40)
-43
-42
(c40)
C24 A c27
(c40)
Cl3 A Ce
c6 <c4
Cl7
C13 A ce
(c4i)
-41-
SHRA -
Shift Right Arithmetic
1. Rimm <- Ri<5:0>,u A Ra <-
Rf (Rd)
2. PSJdus <- Rimm *(SHLL(Ra)
3. Rf(Rd)<- Re
(var_to_push
(var_to_push
(var_to_push
(var_to_push
PUSH - Push into Stack
1. Ra <-
Rf(Rd)
V NULL
2. ALUJdus <- Ra
V ALUJdus <- PSW
3. MDR <- Re A MAR <- SP
4. SP <- SP - 2
POP -
Pop from Stack
1 . SP <- SP + 2
2 . MAR <- SP
3. read_mem<- '1'
4 . Ri <- MDR
5 . Rimm <- Ri
6 . PSW <- Rimm
V Rf (Rd)<- Rimm
(var_to_jDop =
Cl3
Cs
A ce
c6 ( --4l)
c17
l)
R0-R7) c
PSW)
R0-R7) c
3
4 (C4
PSW) c3 c4 (c4l)
c19 A c26
c 27
c28
c26
c18
c14
PSW) c10-
c2 C4
c15
Let's also give the micro-operations that we need for the
fetch cycle which is the same for all the instructions :
FETCH CYCLE
1
2
3
MAR <- PC
readmem<- ' 1'
PC <- PC + 2 A Ri <- MDR A Ri <- MDR<10:8>
Rsl <- MDR<5:3> A Rs2 <- MDR<2:0>
decode <- '1'
c22 A cie A C20
If one wonders about the loading of the MDR register (which is
not mentioned) with the contents of the data bus, we have to
mention that this happens inside the memory cycle initiated by
the read_mem signal every time it becomes'1'
. Both the
read mem and write_mem signals initiate processes for the
memory read and write cycles and inside those processes, the
correct timing of the bus (according to the read/write
protocol) , the loading of the registers or the transferring of
the data and address to the buses occur so that a successful
communication is established between the CPU and the memory .
-42-
5 VHDL Description of the Architecture
The first paragraph of this chapter is a brief intro
duction to hardware description languages and especially the
Very High Speed Integrated Circuits (VHSIC) Hardware
Description Language -
or VHDL. We are going to use VHDL in
the remainder of this chapter to describe and simulate (in the
next chapter) the architecture we described in the three
previous chapters .
5 . 1 Hardware Description Languages
After the design of any digital structure, follows the
phase of the evaluation. Because the latter is a"painful"
and
time consuming process, the use of computers was incorporated.
Hardware Description Languages (HDLs) are the connecting link
between the design and the evaluation of a computer system. Bythe use of these languages, every design can be transferred as
a schematic or a source file -
or the combination of both -to
computers, where the evaluation procedure can be done quickly
and accurately. This evaluation is nothing else but the
simulation of the design. Therefore, almost every HDL has an
incorporated simulator where the source file, after it has
been compiled to ensure error free description, is given as
input to the simulator and the final results are obtained. If
the results are not the ones that were expected, then the
designers should go back, check the design and after
corrections, they should again follow the verification
procedure. By validating the design through the simulation,
the very expensive task of prototyping the design is avoided
and a lot of money may be saved in the case of a design that
was defective. The main applications, thus, of the HDLs are
two : the documentation and the modeling of a design. After
that comes the simulation by an HDL supported simulator. Until
some years ago, the HDLs were mainly developed around a
specific level of description of the computer structures. Some
of them could only describe the architecture and therefore
they were called Architecture Description Languages (ADLs) ,
others could only describe the register or gate level and
finally there was one that could do all of the above and even
more .
5.1.1 VHDL
VHDL was first developed by the US Department of Defense,
initiated as part of its Very High Speed Integrated Circuits
program. Later it was proposed as an IEEE standard and after
a number of revisions and changes, it became standard in late
1987 (IEEE 1076) . VHDL has the unique ability to describe any
level of a digital system, starting from the overall
architecture and reaching down to the lowest level which is
the silicon implementation. The abstraction levels of a
-43-
/ PMS \
/ CHIP \
/ REGISTER \
/ GATE \
/ CIRCUIT \
/ SILICON \
Figure 5 . 1 Description Levels
of Digital Systems
digital system are shown in figure 5.1 [ARM89] . The shape of
the pyramid shows the amount of detail that each level
represents, which
gradually increases as we
approach the silicon
implementation. Our
description is concerned
with the three higher
levels of the pyramid
which are the Processor
Memory Switch level
(PMS) , the Chip level and
the Register level . The
PMS is an abstract look
at the CPU-memoryconnection through the
buses and the performance
specifications. The chip
level contains the various
parts of the system such as
the microprocessor, the
Random Access Memories (RAMs) and other components. Finallythere is the Register level which goes inside these components
and describes the operations among the registers, ALUs, MUXes
and other combinational or sequential parts.
Two are the descriptions that VHDL can provide for a
digital system : The structural and the behavioral. By the
structural description we mean a complete list of the
components of the system and their interconnection at any of
its levels. These levels can co-exist in the same description
file, giving a hierarchical decomposition of the system. By
behavioral description, we mean the algorithm (procedure) that
is performed at any description level of the system. Since the
behavioral model can exist at the chip, register, gate or
circuit level in a given design, we may have behavioral
modeling for different parts at different levels.
Now let's present some of the basic features of VHDL
without getting into details. We suppose that the reader is
already familiar with the language, its structure and its use.
This is not going to be a tutorial but a brief explanation of
some of the most important parts of the language that have
been used for the description of our system.
Entity : Every design is expressed in terms of entities.
Entities can be nested and the top-level entity
represents the uppermost level of our design.
Architecture : The architecture describes the behavior of
the entity- A single entity may have multiple archi
tectures but only one of them can be enabled for a
simulation run.
Package : A package is a file with a collection of
commonly used data types and subprograms in a design.
-44-
More than one package can be linked to a design. If theyhappen to define the same data types or subprograms, then
the definition of the last linked package is used.
Process : It is the basic unit of sequential execution in
VHDL. All of the commands inside aPROCESS1
are executed
sequentially and their execution is scheduled At time
after their activation. Any number of At units add up to
zero. Because of this strange behavior, but necessary for
proper simulation, implementations that use PROCESSes
need extra attention (see 5.8) .
Block : Blocks, like PROCESSes, represent the basic unit
of parallel execution in VHDL. That means that all of the
statements inside a BLOCK are executed concurrently (i.e.
all the events are activated at the same time and their
execution is scheduled after At) .
5.2 Getting started
We stared the description phase of the design with a big
problem for a project of this size. The version of the Mentor
Graphics Corporation VHDL compiler we had to use on the Apollo
Workstations was a preliuminary or Alpha-version. It was made
available to certain academic and corporate users to allow
them to obtain some preliminary experience with the language
before the complete compiler was finished. The compiler did
not recognize some very useful parts of the language. These
were the GENERICS, the Resolution Fuctions, the COMPONENT
declarations and the STABLE (x) and QUIET (x) attributes. With
the lack of GENERICS we couldn't pass some timing
characteristics into our design entities. With the lack of the
Resolution Fuctions there was no way to implement a data bus
that can be driven by both the CPU and the memory (generally,
Resolution Functions are used to define signals that are
driven by more that one active signal at a time) . The lack of
the COMPONENTS didn't permit us to give a structural
description of the system. With the use of COMPONENTS, one can
describe each component separately, using entities and
architectures, and then can map these architectures into
components of a higher level design (uppermost entity) . In
this way, the inputs and the outputs are clearly described for
each component and the interconnectionsbetween them are fully
demonstrated in the component declarations (see [ARM8 9] for
more information) . Finally, the lack of the STABLE (x) and
QUIET (x) attributes gave us some difficulty in determining if
a signal was stable for a period of time 'x'. Some other,
minor problems were also present, but like the ones mentioned
above, we found some ways to overcome them, even at theexp-
xFrom now on, all the VHDL keywords will be written in
capital letters.
-45-
ense of the integrity of our design as we will explain later
5.2.1 Packages
We briefly mentioned packages in 5.1.1. In this thesis
project, we used one package that contained all the timingconstants
- instead of using GENERICS we used constants-
of
our description and the functions that were mainly used for
conversion of variables of one data type to another. The
source file of the package must always be in the parent
directory of the directory that we have the file that we want
to link the package to. The directory structure looks like the
one in figure 5.2.
/
/no i n
pock . hdl
/no i n/cpu /no 1 n/rout ines
des i gn . hd 1
Figure 5 . 2 Directory Organization
In the'/main'
directory (or the'login'
directory) we have
the source file of the package "pack.hdl"
with the functions.
In a subdirectory(' /main/cpu'
) we have the description of our
main design which has the name "design . After we compile
the package with the command :
$ hdl main pack. hdl
from the root ('/') directory, the directory'/main/routines'
is created as a subdirectory of' /main'
. This directory
contains some other directories with the binary files that
were created by thecompilation. In order, now, to link these
binary files to our source file ("design.hdl")
we have to
include the line :
USE work. routines.ALL;
in the first lines of that file and before the use of any data
type, constant or function that was defined in the package.
The package that we used is given in Appendix A. It
-46-
contains the data types conversion functions, a resolution
function, the definition of some data types and some
constants .
5 . 3 Component description
We decided to represent each component by a BLOCK
structure since there was no chance to use COMPONENTS. The
BLOCK structure is a part of the code, that can be executed
concurrently with other BLOCK structures of the same level and
it can contain smaller structures such as BLOCKS or PROCESSes
which can also be executed concurrently. The way we assigned
the various components to BLOCKS or PROCESSes is shown in
figure 5.3.
ARCHITECTURE : SYSTEM
BLOCK : CPU
BLOCK : CONTROL UNIT
BLOCK : INTERRUPT UNIT
PROCESSES* : REGISTERS
PROCESS : ALU
PROCESS : POWER SHIFTER
BLOCK : CPU-MEMORY
HANDSHAKING UNIT
BLOCK : CLOCK GENERATOR
BLOCK DATA BUSFUNCTION
S RESOLUTION
BLOCK : MEMORY BANKSELECT UNIT
BLOCK : MEMORY
PROCESS : MEHORT IN1TIRLIZRTI0N
PROCESS : MEMORY BANK 1
PROCESS : MEMORY BANK 2
Figure 5.3 BLOCKS and PROCESSes
The+symbol in the cpu BLOCK means that there are as many
PROCESSes as registers. The control and interrupt units
consist also of some other PROCESSes as shown in figures 5.4
and 5.5. The execute BLOCK in the control unit BLOCK, contains
BLOCK : CONTROL UNIT
PROCESS : FETCH
PROCESS i DECODE znBLOCK : EXECUTE
PROCESS ; STATE C00RDINRTION)
PROCESS : INTERRUPT ACTION
Figure 5 . 4 Control Unit
BLOCK
BLOCK : INTERRUPT UNIT
PROCESS : RESET INTERRUPT
PROCESS : EXTERNAL INTERRUPT
PROCESS : OPCODE ERROR INTERRUPT
PROCESS : ADDRESS MISALIGNMENT
INTERRUPT
Figure 5 . 5 Interrupt
BLOCK
Unit
-47-
all the PROCESSes for the execution of each instruction and
the interrupts PROCESSes. There are actually four (4)
interrupt service PROCESSes which are called in the case of an
interrupt to produce some preliminary actions . CAUTION : These
interrupt PROCESSes are not the interrupt service routines
which reside in the memory. They are also different from the
four (4) PROCESSes in the interrupt unit BLOCK because the
interrupt unit recognizes and allows or prohibits the
interrupts; it is not responsible for any action taken after
an interrupt is issued. The next paragraphs explain with more
details some of the boxes in figures 5.3, 5.4 and 5.5.
5 . 4 The data bus
In contrast to the address bus which is unidirectional
and driven only by the CPU, the data bus is bidirectional and
can be driven by both the CPU and the memory. As we explained
in 5.2, the use of a Resolution Function wasn't available and
consequently we had to define two different signals as the
data bus, one driven by the CPU and another driven by the
memory. These two signals couldn't be defined as buses
-
another disadvantage of this
Gl
G2
G3
VCC
Figure 5 . 6 Wired OR logic
VHDL version-
sowe'
defined
them as arrays of 16 elements
where each element was of type
gsim_state. This type supports
four (4) different signal
states : LOW ('0'), HIGH ('1'),
HIGH IMPEDANCE ('z') and
UNKNOWN ('x') and therefore the
simulation can be quite reali
stic. This data type was also
used for all the signals that
were used in our system.
Before we continue with further explanations on the data
bus let's first see why we need a bus resolution function.
Suppose for example, that we have a single wire (figure 5.6)
that is driven by the two gates Gl and G2, which can have as
output one of the states HIGH ('1') or LOW ('0') when
G1\G2 0 1 X z
0 0 X X 0
1 X 1 X 1
X X X X X
z 0 1 X z
Table 5 . 1 Resolution Table for the input of G3
enabled or HIGH IMPEDANCE ('z') when disabled. This wire is
-48-
the input of G3 and according to the resolution table 5.1 it
can be in one of the states 'x', '0','1'
or'z'
. The input of
G3 enters the'x'
state if any of the driving gates have
unknown input (so the output is unknown too) ,or when one of
them drives the wire at logic HIGH and the other at logic LOW.
The above table is easily implemented by the function
below which resides in the package with the various functions:
1 FUNCTION wired_or (k,l : qsim state)
2 VARIABLE ret qsim : qsim state;
3 VARIABLE a,b : extra state;
4 VARIABLE dumvec : extra state vect
5 BEGIN
6 a := qsim to extra (k) ;
7 b := qsim to extra (1);
8 : dumvec := (a & b) ;
9 : CASE dumvec IS
1 D: WHEN"00"
=> ret qsim :='0'
1 1: WHEN"01"
=> ret qsim :='X'
1 2: WHEN"0Z"
=> ret qsim :='0'
1 3: WHEN"10"
=> ret_qsim :='X'
1 i : WHEN"11"
=> ret qsim :='1'
1 5: WHEN"1Z"
=> ret qsim :='1'
1 6: WHEN"ZO"
=> ret qsim :='0'
1 7: WHEN"Zl"
=> ret qsim : ='1'
1 3: WHEN"ZZ"
=> ret qsim :='Z'
1 9: WHEN OTHERS => ret qsim :='X'
2 0: END CASE;
2 1: RETURN ret qsim;
2 2: END wired or;
RETURN qsim_state IS
DOWNTO 0)
Figure 5 . 7 Resolution Function
In line 1, the k and 1 parameters are the two inputs of the
function. In lines 6 and 7 they are converted from data type
qsim state to extra_state (see 5.8 for the need of this
conversion) and after they form a two element array in line 8,
they are resolved by the CASE statement that follows and fully
implements the table 5.1. The "WHENOTHERS"
statement means
the"xx"
case which couldn't be mentioned because in every
CASE statement in which a row of n signals is examined, we can
only use3n_1
different cases plus a .last one which has always
to be the "WHEN OTHERS". If more than3n_1
cases are examined
or the "WHENOTHERS"
statement is missing, an error during the
compilation will be issued.
CPU
CPU_DATfl_0UTaDflTR BUSRESOLUTION
FUNCTIONvMEM_DflTA_0UT
<JDflTR BUS
MEMORY
Figure 5 . 8 Data bus decomposition
-49-
After this rather big digression, let's go back to the
discussion we had about the breaking up of the data bus to two
other buses, namely the cpu_data_out and the mem_data_out
which represent the data coming out of the CPU and the memory
respectively. The real data bus is formed after these two
signals pass through a resolution function (Fig. 5.8) . The
data bus then, contains the correct data that are available as
inputs to the CPU and the memory.
These two signals form the sensitivity list of the data bus
PROCESS which is described below (Fig. 5.9) and it is part of
the data bus resolution function BLOCK.
DATA BUS
data_bus_res : BLOCK
BEGIN
res_func : PROCESS (mem_data_out , cpu_data_out )
VARIABLE l,r : qsim_state;
VARIABLE dumbin : qsim_state_vector (15 DOWNTO 0) ;
BEGIN
FOR i INmem_data_out'
RANGE LOOP
data bus(i) <= wired_or (mem_data_out (i) ,cpu_data_out (i) ) ;
END LOOP;_
END PROCESS res_func;
END BLOCK data bus res;
Figure 5 . 9 Data bus PROCESS
The sensitivity list is a list of signals on which the
execution of the body of the PROCESS depends. If any of the
signals of the sensitivity list changes, then the statements
inside the PROCESS start to be executed.
In our case the PROCESS statement has nothing else but a
FOR-LOOP statement which assigns to each bit position of the
data bus the result of the resolution function, when this
function is applied to the same bit positions of both the
cpu data out and the mem_data_out signals. If for example the
data-out signal is the binary number"OlOlOlzx"
and the
cpu~data out signal is the binary number"zxlllzzl"
then the
number assigned to the data bus will be the one shown in
figure 5.10.
G 1 0 1 0 1 z x Z X
J
1 1 1 Z 2 1
Oxxlxlzx
Figure 5.10 Example of the data bus formation
-50-
5 . 5 The secondary units
The secondary units are the system clock generator, the
memory bank select unit and the CPU-Memory Handshaking Unit .
They are quite simple units to implement in VHDL and their
code is presented in figures 5.11, 5.12 and 5.13, followed bysome explanatory comments.
CLOCK GENERATOR
clk_gen : BLOCK
BEGIN
system_clk : PROCESS (run, clock)BEGIN
IF((run'
EVENT) AND (run = '1')) THEN
clock <= '1'; starts always from HIGH
ELSIF ((clock'
EVENT) AND (run = '1')) THEN
clock <= NOT (clock) AFTER period/2;
ELSE
clock <= '0'; if RUN is LOW then clock remains LOW
END IF;
END PROCESS system_clk;
END BLOCK elk gen;
Figure 5.11 System Clock Generator
MEMORY BANK SELECT UNIT
mem bank_sel_unit : BLOCK
BEGIN
mbsu : PROCESS (word, rd_bar, wr_bar, addr_lsb, vma)
VARIABLE int_l , int_2 , int_3 : qsim_state;
BEGIN
int 1 := (NOT(wr_bar) ) AND (word) ;
int~2 := (NOT (wr_bar) ) AND (addr_lsb) AND (NOT (word) ) ;
int_3 := (NOT (addr_lsb) ) AND (NOT (wr_bar) ) AND (NOT (word) )
ASSERT NOT((rd_bar = '0') AND (wr_bar = '0'))
REPORT "wr bar & rd_bar cannot be bothLOW"
SEVERITY ERROR;
oe_bar<= rd_bar;
cs_bar<= NOT (vma);
wrl bar <= NOT(int_l OR int_3) ;
wr2_bar<= NOT(int_l OR int_2) ;
PROCESS mbsu;
END BLOCK mem bank sel_unit;
Figure 5 . 12 Memory Bank Select Unit
CPU MEMORY TIME HANDSHAKING UNIT
cpu mem_time_unit : BLOCK
BEGIN
handshake : PROCESS
VARIABLE count : integer;
BEGIN
WAIT ON rd bar,wr_bar UNTIL ( (rd_bar = '0') OR
IF ((rdbar'
EVENT) AND (rd_bar = '0') AND (vma
mem rdy<= ' 0
'
;
WAIT ON clock UNTIL (clock ='1'
) ;
WAIT ON clock UNTIL (clock = '1');
mem rdy<=
'1' AFTER (w_states *period);
END IF;_
(wr_bar ='0'
) ) ;=
'1'
) ) THEN
Tl end
T2 end
wait states
-51-
IF ((wrjbar'
EVENT) AND (wr_bar = '0') AND (vma = '1')) THEN
mem_rdy<= '
0'
;
WAIT ON clock UNTIL (clock = '1'); Tl end
WAIT ON clock UNTIL (clock ='1
'
) ; T2 end
mem_rdy<= '1' AFTER (w_states *
period); wait states
END IF;
END PROCESS handshake;
END BLOCK cpu_mem_time_unit ;
Figure 5.13 CPU-memory handshaking unit
5 . 6 The memory
The memory BLOCK has three PROCESSes. The first one is
activated at the LOW-to-HIGH transition of the RUN signal and
it transfers to the two memory integer arrays that represent
the two memory banks, the interrupt vectors, the interrupt
service routines and some code which is used for the
simulation. This PROCESS is described in the next chapter
which is dedicated to the simulation of the entire system. The
other two PROCESSes are thp ones which describe the two memory
banks. Let's take a Ice one of them. The other is
implemented in a similar way .
l
2
3
4
5
6
7
8
9
10
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
bank2 access : PROCESS (oe_bar, cs_bar, wr2_bar)
VARIABLE mem_val : integer;
VARIABLE dum_int : integer;
VARIABLE dum_bin : qsim_state_vector (7 DOWNTO 0) ;
VARIABLE interm_dat : qsim_state_vector (7 DOWNTO 0);
BEGIN
IF ((oejbar'
EVENT) AND (oe_bar = '0') AND (cs_bar = '0')) THEN
dum int := qsim_to_int (address_bus) ;
val := mem_bank2 (dum_int ) ;
dum~bin(7 DOWNTO 0) := int_to_8bit (mem_val) ;
FOR i IN 7 DOWNTO 0 LOOP
mem_data_out (i) <= dum_bin(i) AFTER t_o;
END LOOP;
ELSIF ((wr2_bar'
EVENT) AND (wr2_bar = '0') AND (cs_bar = '0')) THEN
interm_dat := data_bus (7 DOWNTO 0) ;
mem val := qsim_to_int (address_bus) ;
int := qsim_to_int (interm_dat) ;
bank2 (mem_val)<= dum_int;
ELSIF ((oejbar'
EVENT) AND (oe_bar = '1')) THEN
FOR i IN 7 DOWNTO 0 LOOP
mem_data_out (i) <=' Z'
AFTER totd;
END LOOP;
ELSE
NULL;
END IF;
END PROCESS bank2 access;
Figure 5.14 Memory Bank #2
As figure 5.14 shows, this is the memory bank #2 and the
PROCESS that implements it, has as signals in the sensitivity
list the OE bar, CS_bar and WR2_bar. These signals are
provided by the Memory Bank Select Unit as explained in 2.2.
After a signal has changed, it is first checked if this is a
-52-
memory read (lines 7-13) . If it is, the binary number
contained in the address bus is converted to integer (line 8)in order to find the memory (array) location we want to read
from. In line 9, the number contained in that location is
stored in a temporary variable and in line 10 it is converted
to an8bit binary number. This number is transferred to the
eight (8) LSbits of the me/n_data_out bus (remember the data
bus decomposition?) in lines 11 to 13 and after time t0 (see
2.3 and table 2.2) . If it is a memory write then both the
contents of the address and data (bits <7 : 0>) buses are
converted to integers (lines 16-17) . The eight (8) LSbits of
the data bus have first to be transferred to a temporaryvariable which is an array of 8-bits long, and then the
conversion function has to be called. The reason for that is
that we cannot call a function by specifying as a parameter a
portion of a variable (scalar) . Therefore the followingcommand issues a compiler error :
dum_int := qsim_to_int (datajbus (7 DOWNTO 0) ) ;
After the conversion of the two binary numbers (address bus
and data bus (<7:0>)) the memory loading takes place (line
18) . In the third part of the PROCESS (lines 19-22) the memory
returns the eight LSbits of the data bus to the HIGH IMPEDANCE
state after its output is disabled.
The PROCESS for the memory bank #1 is almost identical
with the one we described with only difference that it works
with the eight MSbits of the data and jne.m_data_out buses.
5.7 The CPU
The CPU that we are going to describe in this paragraph
is the latest version of the CPU implemented (as of September
1, 1991) . The first CPU had only the ability to write and read
to/from the memory and we used it to verify the implementation
of the secondary units, the memory and the buses, as they
described in the previous paragraphs. After this first
version, the various units and registers were added-
one at
a time-
and by the use of small programs, they were simulated
and their properoperation was verified.
5.7.1 The registers
This was the easiest part of the CPU to describe. The
loading of each register depends on some control signals as
thev were described in 4.4 and table 4.1. These control
signals can consist of the sensitivity list of the PROCESSes
that describe the behavior of the registers. We will take as
an example the description of the Memory Address Register
(MAR) . By searching in table 4.1 all the assignments that have
as destination the MAR we find the following :
MAR<~ PC c:5
MAR<- SP c26
-53-
'1') AND (c23 ='1'
)) OR
'1') AND (c25 ='1'
)) OR
'1') AND (c26 ='1'
)) OR
'1') AND (c25 ='1'
)) OR
'1') AND (c26 ='1'
)) OR
'1') AND (c26 ='1'
)))
MAR <-RC C21
MAR <-int_vector c23
We take, thus, these control signals (c25, c26, c21, c23) and we
build the sensitivity list of a PROCESS with the name
jnem_addr_reg (Fig. 5.15).
mem_addr_reg : PROCESS (c21, c23, c25, c26)
VARIABLE dumbin : qsim_state vector (15 DOWNTO 0) ;BEGIN
ASSERT NOT( ( (c21
((c21
((c21
(<c23
((c23
<(c25
REPORT "MAR assignment error Multiplesources"
SEVERITY ERROR;IF
((c21'
EVENT) AND (c21 = '1')) THEN
MAR <= Re;
ELSIF((c25'
EVENT) AND (c25 = '1')) THEN
MAR <= PC;
ELSIF((c23'
EVENT) AND (c23 = '1')) THEN
dumbin (15 DOWNTO 0) := int_to_16bit (rom_int_addr (vec_num) ) ;MAR <= dumbin;
ELSTF((c26'
EVENT) AND (c26 = '1')) THEN
MAR <= SP;
ELSE
NULL;
END IF;
END PROCESS mem_addr_reg;
Figure 5 . 15 VHDL description for MAR
We first want to make sure that just one signal at a time is
asserted, so we have the ASSERT statement to check it, and
REPORT whenever it happens :
"MAR assignment error Multiplesources"
to the person who runs the simulation, causing at the same
time an ERROR (lines 4-11) . If everything is legal, then the
assignment takes place according to the control signal that
was asserted. In the case of the int_vector assignment (lines
16-18) the MAR is loaded with the number contained in the
position of an array of four 16-bit elements pointed by the
signal vec num. This array represents a 4xl6bit ROM inside the
CPU that "contains the memory locations of the interrupt
vectors that the CPU has to load every time that an interrupt
occurs .
The rest of the registers are implemented in the same way
and we don't think that we should mention them.
5.7.2 The control unit
This unit is a BLOCK itself and contains many PROCESSes
that arrange the normal operation of the CPU. These PROCESSes
are the following :
-54-
5.7.2.1 The internal clock
This is the clock that is distributed to the CPU parts .
Its operation is suspended during a memory read or write cycle
- that is when either the write_mem or the read_mem signal is
asserted-
and it resumes when these signals are deasserted
(they are deasserted by the MEMRDY signal) . Figure 5.16 shows
the code for the internal clock implementation.
internal_clock : PROCESS (clock,write_mem,.read mem)
BEGIN
IF ( (write_mem = '1') OR (read_mem = '1')) THEN
NULL;
ELSE
elk <=clock;
END IF;
END PROCESS internal_clock;
Figure 5.16 Internal Clock
5.7.2.2 The fetch PROCESS
The three steps of the fetch cycle were explained in 3.1
and the micro-operations were mentioned in 4.5. The imple
mentation is shown in figure 5.17 with comments on the use of
the commands .
fetch_instr : PROCESS (proc_state, f_cyc)
BEGIN
IF (proc_state = fetch) THEN
IF (f_cyc = 1) THEN 1st fetch cycle
c25 <= '1','0' AFTER period/2; MAR <- PC
ELSIF (f_cyc = 2) THEN
read_mem <= '1
'
; MDR <- MEM [MAR]
ELSIF (f_cyc = 3) THEN
cl8 <='1','0'
AFTER period/2; Ri <- MDR
c20 <='l'.'O'
AFTER period/2; decode <- '1
'
c22 <='1','0'
AFTER period/2; PC <- PC + 2
ELSE
NULL;
END IF;
END IF;
END PROCESS fetch_instr;
Figure 5.17 The fetch PROCESS
5.7.2.3 The execute BLOCK
This BLOCK contains twenty five (25) PROCESSes (i.e. as
many as the instructions) . Each PROCESS contains themicro-
operations that have to be executed at the proper clock cycle.
As an example, figure 5.18 shows the code for the execution
PROCESS of the OR instruction. The control signals that each
instruction uses, are easily obtained from 4.5 where the
instruction decomposition was given.
orr_in : PROCESS (proc_state, ex_cyc)
BEGIN
IF ( (proc_state= execute) AND (instruction =
orr) ) THEN
CASE ex_cyc IS
-55-
WHEN 1 => IF (immediate = '1') THEN
IF (sign ='1'
) THEN
cl3 <= '1','0' AFTER period/2;
cl4 <= '1','0' AFTER period/2;
ELSE
cl3 <= '1','0' AFTER period/2;
END IF;
c8 <= '1','0' AFTER period/2;
ELSE
c7 <= '1','0' AFTER period/2;
c9 <= '1','0' AFTER period/2;
END IF;
WHEN 2 => IF (immediate = '1') THEN
clO <= '1','0' AFTER period/2;
ELSE
ell <= '1','0' AFTER period/2;END IF;
cl <= '1','0' AFTER period/2;
c3 <= '1','0' AFTER period/2;
c4 <= '1','0' AFTER period/2;
WHEN 3 => cl7 <= '1','0' AFTER period/2;ex_end <= '
1'
;
WHEN OTHERS => NULL;
END CASE;
END IF;
END PROCESS orr_in;
Figure 5.18 The OR execution PROCESS
The "WHENnumber"
statements check the clock cycle that the
execution is at, and according to that the proper control
signals are asserted. When the execution of an instruction
reaches the end, it asserts the signal ex_end and at the next
clock cycle, after the IU finishes checking for an external
interrupt, the CU starts with the fetch of the next
instruction if no such an interrupt was issued.
5.7.2.4 The state coordination
This is the most important PROCESS of the control unit .
It maintains the right state sequence for the CPU's fetch and
execute states. This PROCESS (Fig. 5.19) is enabled every time
the internal clock goes from LOW-to-HIGH. If the CPU is in the
fetch state, it advances the fetch cycle (f_cyc) until it
reaches three (3) .Then the CPU changes state, from fetch to
execute, and the execution cycle (ex_cyc) is initiated to 1.
The execution cycle is increased until the ex_end signal
becomes HIGH ('1'). Then the state PROCESS changes again the
state, from execute to fetch, and it initializes the fetch
cycle to 1 if no external interrupt was issued.
state : PROCESS
BEGIN
WAIT ON elk UNTIL (elk ='1
'
) ;
IF ( (proc_state= fetch) AND (f_cyc < 3) ) THEN
f eye <= f_cyc +1;
((proc_state = fetch) AND (f_cyc = 3)) THEN
ex_cyc <= 1;
proc_state<= execute;
ELSIF ( (proc_state= execute) AND (ex_end /= '1')) THEN
-56-
ex eye <= ex_cyc + 1;ELSIF 7(proc_state =
execute) AND (ex_end = '1') AND
((intjoar = '1') OR (PSW (4) = '1'))) THEN
f_cyc <= 1;
proc_state <= fetch;ex_end <= '
0'
;
ELSE
NULL;
END IF;
END PROCESS state;
Figure 5.19 The state coordination PROCESS
5.7.2.5 The interrupts
In chapter 4, we didn't give any of the preliminary
actions that have to be taken in case of an interrupt. By
preliminary actions we mean the micro-operations that have to
be executed before the call of the interrupt service routines .
These actions may be the clearing of all registers, the
loading of the interrupt vector, the saving of the Program
Counter and the Processor Status Word and many others . Here
are the micro-operations for the external interrupt (Fig.
5.20) and their VHDL implementation (Fig. 5.21). The numbers
on the left of figure 5.20 represent clock cycles.
1. ex_end<- '0' A f_cyc <-
' 1' A write_mem<- '0'
A vec_num<- 1 A read_mem
<- '0' A ex_cyc<- '0'
A Re <- PC A MAR <- SP A INTA <- '1'
2. MDR <- Re A SP <- SP - 2 A write_word<- '1'
3. write_mem<- '1'
4 . ALUJbus<- PSW A Re <- ALU bus A MAR <- SP
5. PSWT4)<- '1' A MDR <- Re T SP <- SP - 2
6. write_mem<- '1'
7 . MAR <- int_vector
8 .read_mem
<- '1'
9 . Ri <- MDR
10 .Rimm
<- Ri
11. ALU_bus<- Rimm
12.<- Re A PC <- Re
13. INTA<- '0'
Figure 5.20 Micro-operations for the external interrupt
interrupt_action : PROCESS
BEGIN
WAIT ON proc_state UNTIL (proc_state = interrupt);
IF (int state = rst) THEN
<ACTIONS for the RESET interrupt>
ELSIF (int_state = ext) THEN
1: f_cyc <= 1; ex_cyc<= 1; ex_end <= '0';
vec num <= 1; read_mem<= '0'; write_mem <= '0';
<='1','0' AFTER period/2; Re <= PC
c26 <= '1''0' AFTER period/2; MAR <= SP
c34 <= '1'; INTA <= '1'
WAIT ON elk UNTIL (elk = '1');
2. cl9 <= '1','0' AFTER period/2; MDR <= Re
-57-
3:
4:
6
7
8
9
10:
11:
12:
13:
c27 <= '1','0' AFTER period/2;
write_word <= '1';WAIT ON elk UNTIL (elk = '1');write_mem <= '1';WAIT ON elk UNTIL (elk =
'1'
) ;c3 <= '1','0' AFTER period/2 ;
c4 <= '1','0' AFTER period/2;
c26 <= '1','0' AFTER period/2;WAIT ON elk UNTIL (elk = '1');PSW (4) <='!';cl9 <= '1','0' AFTER period/2;
c27 <= '1','0' AFTER period/2;
write_word <= '1'
;
WAIT ON elk UNTIL (elk = '1');write_mem <= '1';WAIT ON elk UNTIL (elk = '1')c23 <= '1','0' AFTER period/2
UNTIL (elk ='1'
)
'1';
UNTIL (elk ='1'
)0'
AFTER period/2
UNTIL (elk ='1'
)0'
AFTER period/2
UNTIL (elk ='1'
)0'
AFTER period/2
0'AFTER period/2
UNTIL (elk ='1'
)0'
AFTER period/2
0'AFTER period/2
UNTIL (elk ='1'
)
ON elk
mem <=
ON elk
WAIT
read
WAIT
cl8 <=
WAIT ON
Cl4 <=
WAIT ON
elO <=
c3 <=
WAIT ON
c21 <=
c24 <=
WAIT ON
proc state
1','
elk
1','
elk
1','
1'
,
'
elk
1','
1','
elk
<= fetch;
END
c34 <= ' 0'
;
ELSE
NULL; no actions for
END IF; ADDRESS MI VVVI
PROCESS interrupt_action;
SP <= SP-2
ALU_bus <= PSW
Re <= ALUJdus
MAR <= SP
MDR <= Re
SP <= SP-2
the OPCODE
IMENT have
ERROR and
been implemented
Figure 5.21 VHDL implementation of the external interrupt
The implementation of the micro-operations for the RESET
interrupt have been also included in the VHDL description. The
opcode error and the address misalignment interrupts are
recognized but not implemented. Their code should be similar
to that of the external interrupt.
5.7.2.6 The memory access PROCESS
This PROCESS contains the protocol for the proper buses
and external signals operation. It uses the time constants
that were declared in the package and explained in 2.3 and
the implementation looks like the one in figure 5.22.
mem_access : PROCESS
BEGIN
WAIT ON read_mem,write_mem UNTIL (read_mem ='1'
OR
write_mem ='1'
) ;
IF (read_mem = '1') THEN
c35 <='!'; address bus
c32 <= '1'; word <= 1
c33 <= ' 1'AFTER tsetup; vma <= 1
c31 <= '1'AFTER (tsetup+td) ; rd_bar <= 0
WAIT ON mem_rdy UNTIL (mem_rdy = '0');
WAIT ON mem rdy UNTIL (mem_rdy= '1');
<= MAR
-58-
END
c36 <= '1' '0'AFTER period/2; MDR <= data bus
c31 <= '0'
rd bar <= 1
c35 <= '0'
address bus <= high impc32 <= '0'
word <= 0
c33 <= '0'
vma <= 0
read mem <= '
0'
;
END IF;
IF (write mem = '1') THEN
c35 <= '1'
; address bus <= MAR
c37 <= '1'
; cpu data out <= MDR
IF (write word ='1'
) THEN word <= 1 or 0
c32 <= '1'
;
ELSE
c32 <= ' 0'
;
END IF;
c33 <= '1'
AFTER t setup; vma <= 1
c30 <= '1'
AFTER (tsetup+td) ; wr bar <= 0
WAIT ON mem rdy UNTIL (mem rdy=
'0
'
) ;WAIT ON mem rdy JNTIL rdy
='1
'
) ;c35 <= ' 0'
address bus <= high impc37 <= '0'
cpu data out <= high impc32 <= '0'
word <= 0
c33 <= ' 0'
vma <= 0
c30 <= '0'wr bar <= 1
write mem <= '0'
i
END IF;
-
PROCESS mem ac :ess;
Figure 5.22 The memory access PROCESS
If someone needs to change some of the timing characteristics,
he/she has to change the values of the time constants in the
package, then compile the package and finally compile the main
file to link it to the new package.
5.7.3 The interrupt unit
This unit issues or inhibits the interrupts to the
control unit. Its main purpose is to recognize the interrupts
according to the rules of 2.5. After it recognizes an
interrupt, it enables or disables it, in the case it is
maskable, and then it changes the state of the CPU to
interrupt and it sends the interrupt type (int_state) to the
CU in order, the latter, to take the analogous actions. The
code for the recognition of the RESET interrupt is shown in
figure 5.23.
interrupt_unit : BLOCK
BEGIN
resetjnt : PROCESS
BEGIN
WAIT ON elk UNTIL (elk = '1');
IF ( (reset'LAST_EVENT >= (3*period) ) AND
(reset' LAST_EVENT <= (4*period)) AND
(reset ='1'
) ) THEN
int_state <= rst;
proc_state<= interrupt;
END IF;
END PROCESS resetjnt;
END BLOCK interrupt_unit ;
-59-
Figure 5.23 RESET recognition by the IU
5 . 8 Hints for future VHDL users
This paragraph comes as a little help to the future VHDL
users so that they can avoid some of the most common mistakes
we made, or to learn how to solve them in the case that theyhave already make them. Especially when these mistakes are due
to the VHDL compiler implementation or to a general
misunderstanding of how this hardware description language
works .
Sensitivity list & WAIT statement
If a PROCESS includes a sensitivity list and inside the
PROCESS we want to use the WAIT statement we will get the
error :
? [Error 1594] Line Halt statement not allowed when process statement includes a sensitivity list
The way to avoid it is to delete the sensitivity list and use
a WAIT-ON-UNTIL statement at the first line of the PROCESS
(after the BEGIN statement). Figure 5.24 shows the PROCESS
that issues the error and figure 5.25 the error free version.
dummy : PROCESS (a, b)
BEGIN
c <= a;
WAIT FOR 10 ns;
c <= b;
END PROCESS dummy;
Figure 5.24 This PROCESS
will issue an error
dummy : PROCESS
BEGIN
WAIT ON a,b;
c <= a ;
WAIT FOR 10 ns;
c <= b;
END PROCESS dummy;
Figure 5.25 This PROCESS
will pass
Array shifts for qsim state
When we use the VHDL commands SLL and SRL to make a logical
shift left and right respectivelyto an array which is defined
as qsim state_vector (i.e. each element is of type
qsim state) ,then the variable that fills the shifted elements
is not'0' but 'x'. So, if we have the array :
"011010"
and we perform three left shifts to it, we will get as result
the array :
"0 1 0 x xx"
which can no longer be used in any operation. There are two
solutions to the above problem. The first is to make our own
SRL and SLL functions The second is to convert the array of
-60-
type qsim_state_vector to binary type and then perform the
shifts. In this case 'O's will fill the shifted positions.
The explanation for that is the following and comes from
the VHDL manual of Mentor Graphics :
"The shift left logical (SLL2) operator shifts the left
operand object type to the left and places the initial defaultvalue in the right-most position. The initial default value is
the predefined initial value for thetype."
Because qsim_state has been defined as :
TYPE qsim_state IS (' x'
,
' 0'
,
' 1'
,
' z'
) ;
then'x'
is the initial default value which is placed in the
empty positions.
'x'
and'z'
states
These two states gave great trouble in statements where we
wanted to compare a variable to either'x'
or'z'
state. In
cases where we were sure that our variable was in the'x'
state, the comparison :
IF (var ='x'
) THEN
was always FALSE and the statements inside the IF statement
were not executed. We solved the problem by developing a new
data type, the extra_state as shown in the package in Appendix
A. We also built a function to convert the variables from
qsim state to extra_state and then we used the converted
variables to compare them.
Later, we learnt from the VHDL manual of Mentor Graphics that:
"... anything compared to an'x'
with the equality operator
returns afalse."
and also,
"A'z'
as the left or right operand maps to an'x'
This manual suggested to use the SAME operator instead of the
'=' in cases we want to compare something to an'x'
or'z'
state .
Functions that don't work in packages
We had this strange experience in the very first steps of our
project, when we were developing the functions, one by one,
putting them into the package and then trying to call them
from the main program. Every function was working fine except
the function"qsim_to_int"
,which still resides in the main
program instead of the package and it was always giving arun-
2Same for the shift right logical (SRL)
-61-
time error when we were calling it. The explanation is not
obvious and we think that is the following :
When we defined the function and its input parameter we
didn't specify the size of its data type. We did that on
purpose because we wanted to use this function to convert a
qsim_state_vector signal of any size into an integer. If, now,
we define this function in the package, no memory is allocated
for the input parameter and obviously the compiler cannot
provide the right pointers to the actual parameters. These
problems are solved when we define the function in the main
file and no run-time error is issued.
Signal assignments
This is actually not a VHDL"secret"
but a mistake we
frequently made. It cost us a lot of time to debug the PROCESS
which was being executed without giving the expected results.
In figure 5.26 we first want the signal'd'
to take the value
of'a'
and after the execution of the <OTHER STATEMENTS> we
want it to take the value of'b'
. The result
is that the first assignment
will never happen. The' d'
dummy : PROCESS (a, b)
signal will finally have the BEGIN
value of'b'
without ever d <=a;
having the value of 'a'. If <OTHER STATEMENTS>
the reader remembers about d <= b; (b <= d; )
the PROCESS description we END PROCESS dummy;
made in the beginning of
this chapter and the At time Figure 5.26 A serious error
between the various
instructions inside a PROCESS, he/she will understand that the
two events (signal' d'
assignment) in figure 5.26 have a
finite number of At time difference in their execution. But we
already know that any number of Ats add up to zero. In a few
words, the second event cancels the first because it was
scheduled zero time after it.
The same error can also occur in the case that inside the
same PROCESS (see parenthesis in figure 5.26) we first assign
a value to a signal and later try to assign this signal to
another. The second signal then, will never take the new value
of the first because the execution of the assignment to the
latter has been scheduled but not happened yet.
If someone reads carefully chapter 5 he/she will discover
some other tips about VHDL. These were about the CASE
statements, theindirect construction of a resolution function
and the user definition of a bus.
The complete program listing is given in Appendix B. Not
many comments were included since the VHDL description is
self-explained and most of the important parts of the program
were thoroughlyexplained in this chapter.
-62-
6 Simulation of the System
The VHDL simulator for this project is supported by the
Mentor Graphic's Quicksim II tool. This simulator can load the
program in ASCII form and trace the execution, and it can also
give all the signals we need to observe, in binary, hexa
decimal or decimal form. In the following paragraphs we will
present the code that we ran to simulate the system and the
most important results of the simulation.
6 . 1 The code
We promised in 5.6 to talk about this PROCESS of the
memory BLOCK. It is activated by the LOW-to-HIGH transition of
the RUN signal and it transfers to the memory arrays the
interrupt vectors, the interrupt service routines for the
RESET and external interrupt and a small program with a
subroutine which is called after the execution of the RESET
interrupt (2.5) . The assignment of the code uses both memory
arrays. Every instruction is 16-bits long and the 8 MSbits are
saved in memory bank #1 while the 8 LSbits in memory bank #2.
Because the arrays that represent the memory banks in VHDL are
arrays of integers, every time we have to convert the
hexadecimal or binary number that represents the MSByte and
LSByte of the instruction to integers . The assignment of the
data to the memory is shown in figure 6.1. The memory
locations 0,2,4 and 6, contain the interrupt vectors. At memory
location 200H (512D) begins the code for the RESET interrupt
service routine and at 220H (544D) begins the code for the
external interrupt service routine. The program starts at the
memory location 300H (768D) and the subroutine at 320H (800D) .
memjnit : PROCESS (run)
BEGIN
IF((run'
EVENT) AND (run = '1')) THEN
Interrupt vectors
mem_bankl(0) <=2;"0200"
mem bank2(0)<= 0; reset
mem_bankl(l)<= 2;
"0220"
mem_bank2(l)<= 32; external interrupt
mem_bankl(2) <=2;"0240"
mem_bank2(2)<= 64; opcode error
mem_bankl(3) <=2;
mem bank2(3)<= 96; address misalignment
Zero memorylocations for I/O and stack
FOR i IN 5 TO 255 LOOP
mem_bankl (i) <= 0;
mem_bank2 (i)<= 0;
END LOOP;
Code for RESET
memjbankl (256) <= 105;"6900"
STPSW Rl
mem_bank2(256)<= 0;
Figure 6 . 1 Memory Loading
-63-
mem bankl (257) <= 161;"A18F"
^AND Rl, 01111bmem bank2 (257) <= 14 3;mem bankl (258) <= 73;
"4900"
LDPSW Rl
mem bank2 (258) <= 0;mem bankl (259) <= 145;
"9103"
LDHI Rl,03hmem bank2 (259) <= 3;mem bankl (260) <= 177;
"B100"
LDLO Rl,00hmem bank2 (260) <= 0;mem bankl (261) <= 121;
"7900"
JMP ALW,R1
mem_bank2 (261) <= 0;
Code for external interrupt
mem bankl (272) <= 201;"C900"
PUSH Rl
mem bank2 (272) <= 0;mem bankl (273) <= 105;
"6900"
STPSW Rl
mem bank2 (273) <= 0;mem bankl (274) <= 193;
"C187"
OR Rl, 00111bmem bank2 (274) <= 135;mem bankl (275) <= 73;
"4900"
LDPSW Rl
mem bank2 (275) <= 0;mem bankl (27 6) <= 233;
"E900"
POP Rl
mem bank2 (276) <= 0;mem bankl (277) <= 232;
"E800"
POP PSW
mem bank2 (277) <= 0;mem bankl (278) <= 168;
"A800"
RET
mem bank2 (278) <= 0;
Program code
mem bankl (384 ) <= 14 9;"9506"
LDHI R5,0 6h
mem bank2 (384) <= 6;mem bankl (385) <= 181;
'B520"
LDLO R5,20h
mem bank2 (385) <= 32;mem bankl (386) <= 189;
'BD00"
LDSP R5
mem bank2 (386) <= 0;
mem bankl (387) <= 14 8;9400"
LDHI R4,00h
mem bank2 (387) <= 0;
mem bankl (388) <= 18 0;B4FF"
LDLO R4,FFh
mem bank2 (388) <= 255;
mem bankl (38 9) <= 5;0520"
ADC R5,R4,R0
mem bank2 (389) <= 32;mem bankl (390) <= 6;
0624"
ADC R6,R4,R4
mem bank2 (390) <= 36;
mem bankl (391) <= 145;'9103"
LDHI Rl, 03h
mem bank2 (391) <= 3;
mem bankl (392) <= 177;'B120"
LDLO Rl,20h
mem_bank2 (392) <= 32;
mem bankl (393) <= 137;'8900"
CALL Rl
mem bank2 (393) <= 0;
mem bankl (394) <= 40;'2800"
HLT
mem bank2 (394)<= 0;
Subroutine
mem bankl (400)<= 14 6;
'9204"
LDHI R2,04h
mem bank2 (400) <= 4;
mem bankl (401)<= 178;
'B2B0"
LDLO R2,B0h
mem bank2 (401) <= 176;
mem bankl (402)<= 6;
0683"
ADC R6, 01 IB
mem_bank2 (402) <= 131;
mem bankl (403)<= 206;
CE00"
PUSH R6
mem_bank2 (403) <= 0;
mem bankl (404) <= 236;'EC00"
POP R4
mem bank2 (4 04 ) <= 0;
mem bankl (405) <= 219;'DB00"
STSP R3
mem bank2 (405) <= 0;
Figure 6 . 1 Memory Loading (continued)
-64-
mem bankl (4 06 <= 59;"3B06"
STW R3, [R2+R0]mem bank2 (4 0 6 <= 6;mem bankl (407 <= 26;
"1A06"
LDW R2, [R2+R0]mem bank2 (4 07 <= 6;mem bankl (4 08 <= 18;
"1284"
SHLL R2, 0010Bmem bank2 (4 08 <= 130,mem bankl (4 0 9 <= 50;
"3284"
SHRL R2, 0011Bmem bank2 (4 09 <= 131;mem bankl (410 <= 98; "62
98"
STB R2, [R3+R0] ,hmem bank2 (410 <= 152,mem bankl (411 <= 67;
"4318"
LDB R3, [R3+R0] ,1mem bank2 (411 <= 24;mem bankl (412 <= 19;
"1988"
SHLL R3,1000B
mem bank2 (412 <= 136;mem bankl (413 <= 168;
"A800"
RET
mem bank2 (413 <= 0;END IF;
END PROCESS mem init;
Figure 6 . 1 Memory loading (continued)
6 . 2 Powering up the system
As figure 6.2 shows, at the beginning of the simulation
and when the RUN signal is still low, no clock pulses are
.. 4 olook
elk
run
una
wr 1 t_nen
wr_Jor
r0od_nen
rd_bor
word
ri0n_rdy
reset
lnt_bor
into
eddras_bus
dote_bus
+
.. 4
r~
4
4
4
44 4
4 4 4 4
4
4
4
4
4
4
4
4
+
4
4
4
4
4
4
4
:;4
4
4
4
4
4
4
4
:4
4
4
4
4
4
4
4
[XXXX 4 4 4 4
[XXXX 4 4 4 4
1
100 200 300 400 5QI3
Figure 6 . 2 Beginning of the simulation
generated from the system clock generator and, as we explained
in the previous chapter, no data have been transferred yet to
the memory. At time 200ns when the RUN signal goes from LOW-
to-HIGH the clock cycles begin to get generated (clock) , and
the internal clock (elk) which follows the external clock is
distributed inside the CPU. The CPU is inactive at this time
-65-
and it waits for the RESET interrupt to start operating. In
appendix C (page Cl) the various registers and the processor'sstate are shown, Everything is in the unknown state and the
processor's state is idle.
6.3 Issuing the RESET interrupt
At time 500ns we make the RESET signal HIGH but only fortwo clock cycles. We do that to ensure that our Interrupt Unitfollows the rules for the RESET interrupt recognition. As
appendix C shows, the processor's state between the time 500ns
and 650ns didn't change but it remained idle. Now we assert
the RESET signal for more than three (3) cycles (Fig. 6.3).
Figure 6 . 3 RESET interrupt recognition
The CPU "wakes up", initializes the registers and the
flags and sets the processor's state to interrupt. The Control
Unit sends the proper control signals to the CPU registers and
loads the MAR with the address of the memory location that
contains the interrupt vector for the RESET (00H) . After that,
it performs a memory read. Figure 6.4 shows the signal
assignments for the memory read. Observe the similarity of
figure 6.4 with figure 2.8 where we first developed
theoretically the memory read and write protocol. As we can
see the read mem signal goes HIGH and the internal clock (elk)
freezes. address is transferred to the data bus from the
MAR and after time t the VMA signal goes HIGH,
nanoseconds after that, the RD_bar signals goes LOW. This
triggers the counter in the CPU-memory handshaking unit which
according to the external jumper setting will issue some wait
cycles (one in our case) after the second bus cycle (T2) . The
memory in the meantime and after time t0 from the HIGH to LOW
transition of the RD_signal, puts that data on the
mem data out bus which will be resolved with the cpu_data_out
which is in the HIGH IMPEDANCE state. Finally, the correct
data will appear on the data bus -
they will be the same with
-66-
the data of the mem_data_out bus -. The operation and the data
assignment to the buses is shown in figure 6.5.
clock
elk
vne
wrl t_n0n
wr_bor
reod_pen
rd_bor
word
nen_rdy
reset
lnt_bar
Into
oddreas_bue
dete_bus
4 | S [
? 1 1
4 4 4
4 4 4
T ? 1 ?
L 1
4 1
* L 1
4 4 4
4
4
4 4
4 4
XXXX X.1B1 4 xxxxx 4
xxxx 4 4XR18FXXXXX4
1800 1900 2000 2100
Figure 6 . 4 Memory read cycle
After the MEMRDY signal is asserted by the CPU-memory
handshaking unit (figure 6.4) the VMA and RDJoar signals get
deasserted and the address bus returns in the HIGH IMPEDANCE
state. Because of the memory deselection (VMA signal goes LOW)
the mem_data_out bus returns also to the HIGH IMPEDANCE state
after time t0TD and consequently the data bus (Fig. 6.5)
returns to the HIGH IMPEDANCE state too.
The execution is continued by transferring the interrupt
vector to the MAR and PC registers and by changing the
processor'
s state from interrupt to fetch (Appendix C at time
1350ns) . The CPU now is ready to execute the interrupt service
routine and immediately after that the program code, since the
last instruction of the interrupt service routine is a"jump"
to the address that the program begins.
7350
7490
7500
7505
7700
7850
8000
8140
8150
8155
8400
TIME
00000011
00000011
ZZZZ2Z2Z
ZZZZZZZZ
00000110
ZZZZZZZZ
00000011
00000011
ZZZZZZZZ
ZZZZZZZZ
00000011
0001001
0001001
zzzzzzz
zzzzzzz
0010000
zzzzzzz
0010000
0010000
zzzzzzz
zzzzzzz
0010001
'address bus
zzzz
zzzz
zzzz
zzzz
0000
zzzz
zzzz
zzzz
zzzz
zzzz
zzzz
zzzz
zzzz
zzzz
zzzz
0011
zzzz
zzzz
zzzz
zzzz
zzzz
zzzz
zzzz
zzzz
zzzz
zzzz
0001
zzzz
zzzz
zzzz
zzzz
zzzz
zzzz
zzzz
zzzz
zzzz
zzzz
0100
zzzz
zzzz
zzzz
zzzz
zzzz
zzzz
N
cpu_data_out
zzzzzzzzzzzzzzzz zzzzzzzzzzzzzzzz
1000100100000000 1000100100000000
1000100100000000 1000100100000000
zzzzzzzzzzzzzzzz zzzzzzzzzzzzzzzz
zzzzzzzzzzzzzzzz 0000001100010100
zzzzzzzzzzzzzzzz zzzzzzzzzzzzzzzz
zzzzzzzzzzzzzzzz zzzzzzzzzzzzzzzz
1001001000000100 1001001000000100
1001001000000100 1001001000000100
zzzzzzzzzzzzzzzz zzzzzzzzzzzzzzzz
zzzzzzzzzzzzzzzz zzzzzzzzzzzzzzzz
'"mem data out 'Mata bus
Figure 6 . 5 Operation of the buses
-67-
6 . 4 Program execution and external interrupt
Once the RUN signal is stable HIGH and the RESETinterrupt has been issued, the CPU is going to fetch and
execute instructions from the memory until it finds a HLTinstruction or until the RUN signal returns to the LOW state.
During the program execution the Stack Pointer (SP) isset. After the SP has been set, we issue the external
interrupt (the INTJoar goes LOW) . We have to be sure that theSP has been set before we issue this interrupt because the CPUsaves the flags and the Program Counter into the stack. Theservice routine for the external interrupt just changes theflags (to show that something is happening) and then it pops
the PSW (remember 2.5?) and returns to the program that was
under execution while the interrupt was issued. Figure 6.5shows the various signals during the INTJoar assertion.
4 4 4
clock
elk
vne
wrl te_nen
wr_bor
reod_ren
rd_bor
word
nen_rdg
reset
lnt_per
Into
eddre88_bu8
do to_bu8
! + 4 j j
1 ? 4
4 4 4 4 4_J
4 4 *
4
4
4
4
4
LJ +
1 + 4 4
4
4
4
4
4J +_J
1* 4 4
4
4
4
4
4
L4 4
t_ 4 4 4 4
4 4 4 4 Jxxxx XolBS 4 Xxxxx 4
4
4
4
4
4
&3i&
xxxx 4 XQ520+XXXXX~
X03BC
6000 6100 6200 6300 64G0 6500
Figure 6 . 6 External interrupt assertion
Looking again at appendix C we see that even if the INT_bar
signal was asserted during the fetch cycle of the CPU (6000ns)
it wasn't acknowledged until the completion of the execution
of the instruction (6350ns) . Then the processor changed state,
from execute to interrupt, and the INTA signal was asserted to
show that the interrupt has been acknowledged. In the next 13
cycles, the CPU saves the PSW and the PC in the memory and it
resumes by changing states, from interrupt to fetch, and
start executing the instructions of the external interrupt
service routine.
The contents of the most important registers during the
simulation as well as the processor state and the fetch and
execute cycles are given in appendix C. The address and data
buses are represented by 'x's when they are in the HIGH
IMPEDANCE state (Quicksim shows the'z'
state only in binary
-68-
representations) . Between the simulation results of appendix
C some comments have been inserted (from us) regarding the
actions that were externally taken (interrupt requests) so
that the reader can trace the simulation more easily.
Immediately after appendix C comes appendix D (page Dl) with
the contents of the eight (8) registers of the register file
in integer represenation . The results have been checked and
the proper operation of the system was verified.
That was also the purpose of the program which was shown
in the first paragraph. By the commands we had put in the
program, we tested all the data paths inside the CPU, two out
of the three operations of the Power Shifter, ten out of the
possible thirteen operations of the ALU, twenty out of the
twenty-five instructions of our instruction set in various
formats, included unconditional jumps, subroutine calls and
stack operations. We also tested the buses operation, the
memory read and write protocol and we issued two different
interrupts (RESET and INTjDar) to check the operation of the
interrupt unit and the execution of the interrupt service
routines .
If the reader is patient enough to go through appendices
C and D which start on page Cl and Dl respectively, he/she
will discover all the necessary steps that every computer
system has to follow in order to execute a program.
-69-
Conclusion - Recommendations
The objectives of this thesis project have been clearlyfulfilled. Even the most ambitious plans we had made
- to run
a program on the simulated system-
were obtained.
VHDL offers a great way of structural system
decomposition and behavioral description by the use of BLOCKS
and PROCESSes . One can start describing the system from the
highest level first and then one can gradually decompose everylevel into the parts that constitute that level. This
procedure can continue until the designer reaches the lowest
description level which is the silicon implementation.
The most difficult part of the thesis project was the use
of VHDL. To use VHDL one must be sure that the various aspects
of the language are understand, one must be able to deal with
thecompiler'
s messages and correct the errors in a relatively
short time and one must also know how the different events are
scheduled during simulation time. One should always start the
description and simulation from the higher level of the system
representation and must be certain that the various functions
that are used in the main file have been previously checked
with small programs for their proper operation. It is
important to know that in the cases that the simulator aborts
during the simulation of a design issuing an an error, then
this is due to an incorrect use of a function, either by
passing to it wrong parameter types or by assigning its result
to an improper signal or variable. It is highly recommended to
the VHDL users, to check the proper operation of their
functions by using simple and small programs, before they
incorporate them in large programs .
Some improvements and further work can be done for this
thesis project. First, the Power Shifter could be included
inside the ALU unit and its control signals could be
transferred as inputs to the ALU. Second, since we have space
for seven (7) more instructions in our instruction set, some
very essential and frequently used instructions could be
added. These instructions could be used for clearing or
setting the flags, issuing a software interrupt or returning
from an interrupt service routine (so there is no more need
for the POP PSW command at the end of such a routine) . The
address bus, could be also made 20-bits long, giving the
ability to have a memory space of one (1) Megabyte (this may
need the use of the segment concept) and an external pin for
I/O addressing could be added so that the addresses of the I/O
don't need to be mapped in the memory.
In the first opportunity of a new VHDL compiler, it
should be desirable to give a real structural description of
the system by the use of COMPONENTS-
and not with BLOCKS and
PROCESSes-
and develop a data bus without declaring the
auxiliarysignals cpu_data_out and mem_data_out .
Finally, the CPU could be described at the gate level and
all the structures that the control points represent could be
decomposed to gates for a more detailed simulation.
-70-
References
[ARM8 9] Armstrong, James R. : Chip level modeling with VHDL,
Prentice-Hall, Inc., 198 9.
[DAS8 9] Dasgupta, Subrata : Computer Architecture, John
Wiley & Sons, Inc., 1989.
[GLA91] Glass, Brett : "SPARC Revealed", BYTE magazine,
April 1991.
[GRE88] Greenfield, Joseph D. & Wray, Williams C. : Usingmicroprocessors and microcomputers
- The Motorola
family, John Wiley & Sons, Inc., 1988.
[HAR77] Hartenstein, Reiner W. : Fundamentals of structured
hardware design, North Holland Publishing Company,
Amsterdam 1977.
[HAY88] Hayes, John P. : Computer architecture and orga
nization, McGraw-Hill, Inc., 1988.
[INT8 8] INTEL : Memory Components Handbook, Intel Corpo
ration, 1988 .
[INT8 8] INTEL : Microprocessor and Peripheral Handbook -
Volume I Microprocessor, Intel Corporation, 1988.
[KAI8 9] Kain, Richard Y. : Computer Architecture- Volume I,
Prentice-Hall, Inc., 1989.
[KAN87] Kane, Gerry : MIPS R2000 RISC Architecture, Prentice
Hall, Inc., 1987.
[KAT83] Katevenis, Manolis : Reduced Instruction Set
Computer Architectures for VLSI - ACM Doctoral
Dissertation, The MIT Press, 1985.
[KLI77] Kline, Raymond M. : Digital Computer design,
Prentice-Hall, Inc., 1977.
[LIU8 6] Liu, Yu-Ching & Gibson, Glenn A. : Microcomputer
Systems, The 8086/8088 Family, Prentice-Hall, Inc.,
1986.
[MEN90] Mentor Graphics : VHDL System-1076 Reference Manual
Alpha Release, Mentor Graphics Corporation, 1990.
[PER91] Perry, Douglas L. : VHDL, McGraw-Hill, Inc., 1991
[SMA84] Smardzewski, Richard R. : Microprocessor programming
and applications for scientists and engineers,
Elsevier Science Publishers B.V., 1984.
[TAB90] Tabak, Daniel : RISC systems, Research Studies Press
LTD, 1990.
-71-
APPENDIX A
PACKAGE LISTING
USE std.mentor_base.ALL;
USE std.mentor extended.ALL;
PACKAGE routines IS
CONSTANT period
CONSTANT ta
CONSTANT tw
CONSTANT t_o
CONSTANT totd
CONSTANT tsetup
CONSTANT td
CONSTANT w states
TIME
TIME
TIME
TIME
TIME
TIME
TIME
integer
50 ns; clock period
100 ns; Access Time
100 ns; Write Time
70 ns; Output Enabled to Output Valid
5 ns; Output 3-State from Deselection
25 ns; Address Setup Time
15 ns; VMA HIGH to RD (or WR) LOW
:= 1;
TYPE
TYPE
END
extra_extra
state
state
IS(' 0'
,
'1'
,
'X'
,
vector IS ARRAY
'Z'
) ;
(NATURAL RANGE <>) OF extra state;
FUNCTION int_to_16bit (input
FUNCTION int_to_8bit (input :
FUNCTION qsim_to_bin(in-
FUNCTION bin_to_qsim (inp^'.
FUNCTION qsim_to_extra (input
integer) RETURN qsim_state_vector;
integer) RETURN qsim_state_vector;
state_vector) RETURN bit_vector;
=:tor) RETURN qsim_state_yector;
: qoj.ii. sLate) RETURN extra state;
FUNCTION wired or (a,b
routines;
qsim_state; RETURN qsim_state;
PACKAGE BODY routines IS
FUNCTION int to 16bit (input : integer) RETURN qsim_state_vector IS
VARIABLE ret vec : qsim_state_vector (15 DOWNTO 0) ;
VARIABLE dummy : integer;
VARIABLE inp : integer;
BEGIN
inp := input ;
ASSERT NOT (inp > 65535)
REPORT "Integer too large to fit into 16bits"
SEVERITY ERROR;
FOR i IN ret_vec'REVERSE_RANGE LOOP
dummy:= inp REM 2;
CASE dummy IS
WHEN 0 => ret_vec(i):= '0';
WHEN 1 => ret_vec(i):= '1';
WHEN OTHERS => NULL;
END CASE;
inp:= (inp-dummy) /2;
END LOOP;
RETURN ret_vec;
END int_toJ6bit;
FUNCTION int to 8bit (input : integer) RETURN qsim_state_vector IS
VARIABLE ret_vec : qsim_state_vector(7 DOWNTO 0) ;
VARIABLE dummy : integer;
VARIABLE inp : integer;
BEGIN
inp:= input;
ASSERT NOT (inp > 255)
REPORT "Integer too large to fit into 8bits"
SEVERITY ERROR;
FOR i IN retvec' REVERSE_RANGE LOOP
-Al-
dummy := inp REM 2;
CASE dummy IS
WHEN 0 => ret_vec(i)
WHEN 1 => ret_vec(i)
WHEN OTHERS => NULL;
END CASE;
inp := (inp-dummy) /2;END LOOP;
RETURN ret_vec;
END int to 8bit;
FUNCTION qsim_to_bin (input : qsim_state_vector (15 DOWNTO 0)) RETURN
bit_vector IS
VARIABLE ret_bin : bit_vector (15 DOWNTO 0) ;BEGIN
FOR i IN input'REVERSE_RANGE LOOP
CASE input (i) IS
WHEN'1'
=> ret_bin(i):= '1';
WHEN OTHERS => ret_bin(i):= '0';
END CASE;
END LOOP;
RETURN retjbin;
END qsim to_bin;
bit vector (15 DOWNTO 0))FUNCTION bin_to_qsim (input
qsim_state_vector IS
VARIABLE ret_bin : qsim_state_vector (15 DOWNTO 0) ;
VARIABLE dummy : bit;
BEGIN
FOR i IN input' REVERSE_RANGE LOOP
dummy:= input (i) ;
IF (dummy=
' 0'
) THEN
retJoin <i) :='0'
;
ELSE
retjoin(i):='1'
;
END IF;
END LOOP;
return ret_bin;
END bin_to_qsim;
FUNCTION qsim_to_extra (input : qsim_state) RETURN extra_state IS
BEGIN
CASE input IS
WHEN'0'
=>
WHEN'1
'=>
WHEN'X'
=>
WHEN OTHERS => return' Z'
;
END CASE;
END qsim_to_extra;
FUNCTION wired_or (k,l : qsim_state) RETURN qsim_state IS
VARIABLE ret qsim : qsim_state;
RETURN
return'0'
return' 1'
return'X'
VARIABLE a ,b : extra St ate;
VARIABLE dumvec : extra "state
BEGIN
a := qsim to e stra(k) ;
b := qsim to extra (1) ;
dumvec := (a & b) t
CASE dumvec IS
WHEN"00"
=> ret_qsim' 0'
;
WHEN"01"
=> ret_qsim='X'
;
WHEN"0Z"
=> ret_qsim=
' 0'
;
WHEN"10"
=> ret_qsim^='X'
;
WHEN"11"
=> ret_qsim=
' l'
;
WHEN"1Z"
=> ret qsim~ '1'
;
WHEN"Z0"
=> ret qsim=
' 0'
;
WHEN"Zl"
=> ret_qsim=
' 1'
;
WHEN"ZZ"
=> ret_qsim=
' Z'
;
-A2-
WHEN OTHERS => ret_qsim := 'X';
END CASE;
RETURN ret_qsim;
END wired_or;
END routines;
-A3-
APPENDIX B
VHDL PROGRAM LISTING
USE std.mentor_base.ALL;
USE std.mentor_extended.ALL;
USE work. routines.ALL;
ENTITY system IS
PORT ( run
reset
int_bar
int a
END system;
IN qsim_state;
IN qsim_state;
IN qsim_state;
OUT qsim state) ;
ARCHITECTURE behave OF system IS
TYPE mem_type
TYPE states
TYPE interrupts
TYPE push_pop_vars
TYPE byte_order
TYPE jump_conditions
TYPE instruction set
IS ARRAY (natural RANGE <>) OF integer;IS (idle, fetch, execute, interrupt) ;
IS (rst , ext, ope, addr) ;
IS (CCR, R1,R2,R3,R4,R5,R6,R7) ;IS (msb,lsb);
IS (ALW,C,NC,Z,NV,N,V,P) ;IS (error, sbb, andd, orr,xorr, shll, shrl,
shra, ldw, ldb, ldhi, adc, stsp, ldsp,
ldlo, ldpsw, stw, stb, stpsw, jmp, call,
ret, push, pop, nop, hit) ;
CONSTANT zeros
CONSTANT unknown
CONSTANT highjmpCONSTANT rom int addr
qsim_state_vector
qsim_state_vector
qsim_state_vector
mem_type
="0000000000000000'
="XXXXXXXXXXXXXXXX'
="ZZZZZZZZZZZZZZZZ'
= (0,2,4,6,8);
SIGNAL clock, oe_bar, vma, addrJsb
SIGNAL rd_bar,wr_bar, word,mem_rdy
SIGNAL wrl_bar, wr2_bar, cs_bar
SIGNAL cl, c2, c3, c4, c5, c6,c7
SIGNAL c8,c9, clO, ell, cl2, cl3
SIGNAL Cl4,cl5,cl6,cl7,cl8,cl9
SIGNAL C20,c21,c22,c23,c24,c25
SIGNAL c26, c27, c28, c29, c30, c31
SIGNAL c32, c33, c34, c35, c36, c37
SIGNAL C40, c41, c42, c43
SIGNAL read_mem, write_mem
SIGNAL immediate, sign,write_word
SIGNAL inte,ex_end, elk
S IGNAL cpu_data_out ,mem_data_out
SIGNAL data_bus,ALU_bus,PS_bus
SIGNAL MDR, PC, SP, MAR, PSW
SIGNAL Ri,Rimm,Rc,Ra,Rb
SIGNAL address_bus
SIGNAL Rsl,Rs2,Rd
SIGNAL registers
SIGNAL mem_bankl,mem_bank2
SIGNAL proc_state
SIGNAL int_state
SIGNAL f_cyc, ex_cyc,vec_num
SIGNAL instruction
SIGNAL condition
SIGNAL stack_var
SIGNAL byte
qsim_state=
' '
qsim_state
qsim_state;
qsim_state
qsim_state
qsim_state
qsim_state
qsim_state
qsim_state
qsim_state
qsim_state
qsim_state
qsim_state
qs im_state_vect c
:= "ZZZZZZZZZZZ2
qsim_state_vectc
qsim_state_vectc
qsim_state_vectc
qsim_state_vectc
qsim_state_vectc
mem_type(0 TO 7)mem_type(0 TO 7!
states := idle;
interrupts;
integer;
instruction_set ;
jump_conditions;
push_pop_vars;
byte order;
0'
l';
0'
;0'
0'
0'
0'
0'
0'
0'
0'
0'
or (15 DOWNTO 0)
ZZZZZ";
or (15 DOWNTO 0)
or (15 DOWNTO 0)
or (15 DOWNTO 0)or (14 DOWNTO 0)
or (2 DOWNTO 0) ;
);
99 >;
FUNCTION qsim_to_int (input : qsim_state_vector) RETURN integer IS
VARIABLE retint : integer;
-Bl-
BEGIN
ret int := 0;FOR i IN input
'REVERSE_RANGE LOOP
ASSERT NOT ( (input (i) = 'X') OR (input (i) = 'Z'))
REPORT "Invalid state in integerconversion"
SEVERITY ERROR;
CASE input (i) IS
WHEN'0'
=> NULL;
WHEN'1'
=> retint := (2**i) + retint;
WHEN OTHERS => NULL;
END CASE;
END LOOP;
RETURN retint;
END qsim_to_int;
BEGIN
CLOCK GENERATOR
clk_gen : BLOCK
BEGIN
system_clk : PROCESS (run, clock)
BEGIN
IF((run'
EVENT) AND (run = '1')) THEN
clock <= '1'
;
ELSIF ((clock'
EVENT) AND (run = '1')) THEN
clock <= NOT (clock) AFTER period/2;
ELSE
clock <= ' 0'
;
END IF;
END PROCESS system_clk;
END BLOCK elk gen;
__###########f###########################################################
cpu : BLOCK
BEGIN
interrupt_unit : BLOCK
BEGIN
resetjnt : PROCESS
BEGIN
WAIT ON elk UNTIL (elk ='1'
) ;
IF ((reset'
LAST_EVENT >= (3*period)) AND
(reset'LAST_EVENT <= (4*period) ) AND
(reset ='1'
) ) THEN
int_state <=rst;
proc_state<= interrupt;
END IF;
END PROCESS reset int;
externaljnt : PROCESS
BEGIN
WAIT ON clock UNTIL ((clock = '1') AND (ex_end = '1'));
IF ((int_bar = '0') AND (PSW (4) = '0')) THEN
int_state <= ext;
proc_state<= interrupt;
END IF;
END PROCESS externaljnt;
opcodejnt : PROCESS
BEGIN
WAIT ON instruction UNTIL (instruction =
error) ;
IF (proc_state = fetch) THEN
int_state <= ope;
proc_state<= interrupt;
END IF;
-B2-
END PROCESS opcode int;
addressjnt : PROCESS
BEGIN
WAIT ON write_mem UNTIL (write_mem = '1');
IF ((word = '1') AND (MAR(O) = '1')) THEN
int_state <=addr;
proc_state <= interrupt;
END IF;
END PROCESS opcodejnt;
END BLOCK interrupt_unit ;
control_unit : BLOCK
BEGIN
internal_clock : PROCESS (clock,write_mem, read_mem)BEGIN
IF ( (write_mem = '1') OR (read_mem = '1')) THEN
NULL;
ELSE
elk <=clock;
END IF;
END PROCESS internal clock;
interrupt_BEGIN
WAIT ON
IF (int
FOR
action PROCESS
proc_state UNTIL (proc_state = interrupt)
state =rst) THEN
"i IN 15 DOWNTO 0 LOOP
PSW(i)
END LOOP;
PSW (4) <=
vec
cl
c4
c8
cl2
cl6
c20
c24
c28
c32
c36
FOR
num
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
i IN
<=
0'
0'
0'
0'
0'
0'
0'
0'
0'
0'
0
<= '0'
;
1'
; f_cyc <= 1;
0; read mem <=
c2
c5
c9
cl3
cl7
c21
c25
c29
c33
c37
TO 7
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
LOOP
<= 0;
'0'
,
'0'
0'
'0'
'0'
'0'
'0'
'0'
' 0'
'0'
c3
c6
clO
cl4
cl8
c22
c26
c30
c34
ex
0'
<=
<=
<=
<=
<=
<=
<=
<=
<=
eye <= 1;
write mem
'0'
;' 0'
,
0'.
'0'.' 0'
0'
'0'
'0'
'0'
registers (i)
END LOOP;
WAIT ON elk UNTIL (elk = '1')
c23 <='1','0'
AFTER period/2
WAIT ON elk UNTIL (elk = '1')
read_mem<= '
1'
;
WAIT ON elk UNTIL (elk = '1');
cl8 <='1','0'
AFTER period/2;
elk UNTIL (elk = '1');1','0' AFTER period/2;
elk UNTIL (elk ='1'
} ;1'
,
' 0' AFTER period/ 2 ;
1','0' AFTER period/ 2;
elk UNTIL (elk ='1'
) ;1','0' AFTER period/2;1','0'
AFTER period/2;
WAIT ON
cl4 <=
WAIT ON
ClO<=
c3<=
WAIT ON
c21 <=
c24 <=
WAIT ON
c7
ell
cl5
cl9
c23
c27
c31
c35
elk UNTIL (elk =' 1'
)
proc_state<= fetch;
ELSIF (int state = ext) THEN
f eye<= 1; ex eye
<= 1; ex end <='0'
<=
<=
<=
<=
<=
<=
<=
<=
<=
' 0'
'0'
' 0'
'0'
' 0'
' 0'
'0'
'0'
vec
c2
c26
c34
num
"<=
<=
<=
<= 1; read_mem<= '0';
1','0' AFTER period/2;
1','0'AFTER period/2;
1';
write_mem <= '0';
Re <= PC
MAR <= SP
INTA <= '
1'
-B3-
END
WAIT ON elk UNTIL (elk = '1');cl9 <= '1','0' AFTER period/2;
c27 <= '1','0' AFTER period/2;
write_word <= '1';WAIT ON elk UNTIL (elk =
'1
'
) ;write mem <= '
1'
;
WAIT ON elk UNTIL (elk ='1'
) ;c3 <= '1','0' AFTER period/2;
c4 <= '1','0' AFTER period/2 ;
c2 6 <= '1','0' AFTER period/2;
WAIT ON elk UNTIL (elk ='1'
) ;PSW (4) <= '1'
;
cl9 <= '1','0' AFTER period/2;
c27 <= '1','0' AFTER period/2;
write word <= '1';WAIT ON elk UNTIL (elk = '1');write_mem <= '1';
WAIT ON elk UNTIL (elk = '1')c23 <= '1','0' AFTER period/2,
WAIT ON elk UNTIL (elk = '1')read_mem <= '1';
WAIT ON elk UNTIL (elk = '1')cl8 <= '1','0' AFTER period/2,
UNTIL (elk =' 1'
)'0'
AFTER period/2,
UNTIL (elk =' 1'
'0'
AFTER period/2,' 0'
AFTER period/2
UNTIL (elk =' 1'
)'
0'AFTER period/2,
'0'
AFTER period/2,
UNTIL (elk =' 1'
)
proc_state <= fetch;
c34 <= '0';
ELSE
NULL; no actions for the OPCODE
END IF; ADDRESS MISALIGNMENT have
PROCESS interrupt action;
WAIT ON elk
Cl4 <= 1',WAIT ON elk
ClO <= 1',
c3 <= 1',WAIT ON elk
C21 <= 1',C24 <= 1',WAIT ON elk
MDR <= Re
SP <= SP-2
ALUJdus <= PSW
Re <= ALUJms
MAR <= SP
MDR <= Re
SP <= SP-2
ERROR and
been implemented
state : PROCESS
BEGIN
WAIT ON elk UNTIL (elk = '1');
IF ( (proc_state= fetch) AND (f_cyc < 3)) THEN
f eye<= f_cyc + 1;
( (proc_state= fetch) AND (f_cyc = 3)) THEN
ex_cyc <= 1;
proc state<= execute;
ELSIF ( (proc_state=execute) AND (ex_end /= '1')) THEN
ex_cyc<= ex_cyc + 1;
ELSIF ((proc state =execute) AND (ex_end = '1') AND
(<int_bar = '1') OR (PSW (4) = '1'))) THEN
f_cyc <= 1;
proc_state<= fetch;
ex_end<= '
0'
;
ELSE
NULL;
END IF;
END PROCESS state;
fetch instr : PROCESS (proc_state, f_cyc)
BEGIN
IF (proc_state = fetch) THEN
IF (f eye = 1) THEN
C25 <='1','0' AFTER period/2;
ELSIF (f_cyc = 2) THEN
read_mem<= '
1'
;
ELSIF (f_cyc = 3) THEN
cl8 <='1','0'
AFTER period/2;
-B4-
c20 <= '1',' 0' AFTER pe riod/2;
c22 <= '1',' 0' AFTER pe riod/2;
ELSE
NULL;
END IF;
END IF;
END PROCESS fetch instr,
decode : PROCESS
VARIABLE dumbin : qsim_state_vector (4 DOWNTO 0) ;
BEGIN
WAIT ON c20 UNTIL
dumbin := MDR (15
CASE dumbin IS
WHEN"00000"
(c20 ='1'
);
DOWNTO 11) ;
WHEN"00001"
WHEN"00010"
WHEN"00011"
WHEN"00100"
WHEN"00101"
WHEN"00110"
WHEN"00111"
WHEN"01000"
WHEN"01001"
WHEN"01010"
WHEN"01100"
=>
=>
=>
WHEN"01101"
WHEN"01111"
instruction <=adc;
immediate <= MDR (7) ;instruction <=
nop;
instruction <=shll;
immediate <= '1';
instruction <= ldw;instruction <=
sbb;
immediate <= MDR (7) ;=> instruction <= hit;
=> instruction <=shrl;
immediate <= '1';
=> instruction <=stw;
write_word <= '1';
=> instruction <= ldb;
sign <= MDR (6) ;
=> instruction <= ldpsw;
=> instruction <=shra;
immediate <= ' 1'
;
=> instruction <= stb;
IF (MDR (7) ='1'
) THEN
byte <= msb;
ELSE
byte <= lsb;
END IF;
write_word<= '0';
=> instruction <= stpsw;
=> instruction <= jmp;
CASE MDR (2 DOWNTO 0) IS
WHEN
WHEN
WHEN
WHEN
WHEN
'000"
'001"
010"
'011"
'100"
=> condition
=>
=>
=>
condition
condition
condition
=> condition
WHEN"101"
=>
WHEN"110"
=>
condition
condition
WHEN => condition
WHEN"10001"
WHEN"10010"
WHEN"10100"
WHEN"10101"
WHEN"10110"
WHEN"10111"
WHEN"11000"
WHEN"11001"
=>
111
WHEN OTHERS => NULL;
END CASE;
=> instruction <= call;
write_word<= '1';
instruction <= ldhi;
instruction <= andd;
immediate <= MDR(7);
sign<= MDR(6) ;
instruction <= ret;
=> instruction <= ldlo;
=> instruction <= ldsp;
=> instruction <= orr;
immediate <= MDR(7);
sign<= MDR (6) ;
instruction <= push;
write_word<= '1';
CASE MDR(10 DOWNTO 8) IS
WHEN"000"
=> stack var
<= ALW;<= C;<= V;<= N;<= Z;<= NV;<= NC;<= P;
=>
=>
=>
<= CCR;
-B5-
WHEN"001"
=> stack var <= Rl
WHEN"010"
=> stack var <= R2
WHEN"Oil"
=> stack var <= R3
WHEN"100"
=> stack var <= R4
WHEN"101"
=> stack var <= R5
WHEN"110"
=> stack var <= R6
WHEN"111"
=> stack var <= R7
WHEN OTHERS => NULL;
END CASE;
WHEN"11011"
=> instruction <=stsp;
WHEN"11100"
=> instruction <=xorr;
immediate <= MDR(7);
sign <= MDR (6) ;
WHEN"11101"
=> instruction <=pop;
CASE MDR (10 DOWNTO 8) 15
WHEN OTHERS
END CASE;
END PROCESS decode;
WHEN"000"
=> stack var <= CCR
WHEN"001"
=> stack var <= Rl;
WHEN"010"
=> stack var <= R2;
WHEN"011"
=> stack var <= R3;
WHEN"100"
=> stack var <= R4;
WHEN"101"
=> stack var <= R5;
WHEN"110"
=> stack var <= R6;
WHEN"111"
=> stack var <= R7;
WHEN OTHERS => NULL;
END CASE;
=> instruction <= error;
executeJnstr
BEGIN
BLOCK
stpswjn : PROCESS (proc_state, ex_cyc)
BEGIN
IF ( (proc state =execute) AND (instruction =
stpsw) ) THEN
CASE ex_cyc IS
WHEN 1 => c3 <='1','0'
AFTER period/2;
c4 <='1','0'
AFTER period/2 ;
WHEN 2 => cl7 <='1','0'
AFTER period/2;
ex_end <='
1'
;
WHEN OTHERS => NULL;
END CASE;
END IF;
END PROCESS stpswjn;
ldpswjn : PROCESS (proc_state,ex_cyc)
BEGIN
IF ( (proc_state= execute) AND (instruction = ldpsw) ) THEN
CASE ex eye IS
WHEN 1 => c8<='1','0'
AFTER period/2;
WHEN 2 => c2<='1','0'
AFTER period/2;
ex_end<= '
1'
;
WHEN OTHERS => NULL;
END CASE;
END IF;
END PROCESS ldpswjn;
ldhijn : PROCESS (proc_state, ex_cyc)
RFCIN
IF ( (proc_state= execute) AND (instruction = ldhi) ) THEN
CASE ex eye IS
WHEN 1 => Cl2<='1','0'
AFTER period/2;
WHEN 2 => Cl6 <='1','0'
AFTER period/2;
ex_end<= '
1'
;
WHEN OTHERS => NULL;
END CASE;
END IF;
END PROCESS ldhijn;
-B6-
ldlojn : PROCESS (proc_state,ex_cyc)BEGIN
IF ( (proc_state =execute) AND (instruction = ldlo) ) THEN
CASE ex_cyc IS
WHEN 1 => cl2 <= '1','0' AFTER period/2;
WHEN 2 => cl6 <= '1','0' AFTER period/2;
cl7 <= '1','0' AFTER period/2;
ex_end <= '1'
;
WHEN OTHERS => NULL;
END CASE;
END IF;
END PROCESS ldlojn;
anddjn : PROCESS (proc_state, ex_cyc)
BEGIN
IF ( (proc_state =execute) AND (instruction =
andd) ) THEN
CASE ex_cyc IS
WHEN 1 => IF (immediate = '1') THEN
IF (sign ='1'
) THEN
cl3 <= '1','0' AFTER period/2;
cl4 <= '1','0' AFTER period/2;
ELSE
cl3 <= '1','0' AFTER period/2;
END IF;
c8 <='1','0'
AFTER period/2;
ELSE
c7 <= '1',0'
AFTER period/2;
c9 <='1','0'
AFTER period/2;
END IF;
WHEN 2 => IF (immediate = '1') THEN
clO <='1','0'
AFTER period/2;
ELSE
ell <='1','0'
AFTER period/2;
END IF;
cl <='1','0'
AFTER period/2;
c3<='1','0'
AFTER period/2;
WHEN 3 => cl7 <='1','0'
AFTER period/2;
ex_end <= '
1'
;
WHEN OTHERS => NULL;
END CASE;
END IF;
END PROCESS anddjn;
orr in : PROCESS (proc_state, ex_cyc)
"BEGIN
IF ( (proc_state= execute) AND (instruction = orr)) THEN
CASE ex eye IS
WHEN 1 => IF (immediate = '1') THEN
IF (sign ='1'
) THEN
cl3<='1','0'
AFTER period/2;
cl4<='1','0'
AFTER period/2;
ELSE
cl3<='1','0' AFTER period/2;
END IF;
c8 <='1','0'
AFTER period/2;
ELSE
C7 <='1','0'
AFTER period/2;
C9 <='1','0'
AFTER period/ 2;
END IF;
WHEN 2 => IF (immediate = '1') THEN
clO<='1','0'
AFTER period/2;
ELSE
Cll <='1','0'
AFTER period/2;
END IF;
cl <='1','0'
AFTER period/2;
C3 <='1','0' AFTER period/2;
c4 <='1','0'
AFTER period/2;
-B7-
WHEN 3 => Cl7 <= '1','0' AFTER period/2;
ex_end <= '1'
;
WHEN OTHERS => NULL;
END CASE;
END IF;
END PROCESS orr_in;
xorrjn : PROCESS (proc_state, ex_cyc)BEGIN
IF ( (proc_state =execute) AND (instruction =
xorr) ) THEN
CASE ex_cyc IS
WHEN 1 => IF (immediate = '1') THEN
IF (sign =' 1'
) THEN
cl3 <= '1','0' AFTER period/2;
cl4 <= '1','0' AFTER period/2;
ELSE
cl3 <= '1','0' AFTER period/2;
END IF;
c8 <= '1','0' AFTER period/2;
ELSE
c7 <= '1','0' AFTER period/2;
c9 <= '1','0' AFTER period/2;
END IF;
WHEN 2 => IF (immediate = '1') THEN
clO <= '1','0' AFTER period/2;
ELSE
ell <= '1','0' AFTER period/2;
END IF;
cl <='1','0'
AFTER period/2;
c2 <='1','0'
AFTER period/2;
WHEN 3 => cl7 <='1','0'
AFTER period/2;
ex_end <= '1'
;
WHEN OTHERS => NULL;
END CASE;
END IF;
END PROCESS xorr_in;
jmpjn : PROCESS (proc_state, ex_cyc)
BEGIN
IF ( (proc state=execute) AND (instruction = jmp) ) THEN
CASE ex eye IS
WHEN 1 => c8<='1','0'
AFTER period/2;
WHEN 2 => c4 <='1','0'
AFTER period/2;
WHEN 3 => CASE condition IS
WHEN ALW => c21 <= ' 1','0' AFTER period/2;
c24 <='1','0'
AFTER period/2;
ex_end<= '
1'
;
WHEN C => IF (PSW(O) = '1') THEN
c21 <= ' 1'
,
' 0'AFTER period/2;
c24 <='1','0'
AFTER period/ 2;
ex_end<= '
1'
;
ELSE
ex_end<=
'1
'
;
END IF;
WHEN NC => IF (PSW(O)= '0') THEN
c21<='1','0'
AFTER period/2;
c24 <=' 1'
,
' 0'AFTER period/2;
ex_end<=
'1'
;
ELSE
ex_end<= '
1'
;
END IF;
WHEN Z => IF (PSW (2) = '1') THEN
c21 <='1','0'
AFTER period / 2;
c24 <='1','0'
AFTER period/2;
ex_end<= '1'
;
ELSE
ex_end<= '
1'
;
END IF;.
-B8-
WHEN NV => IF (PSW(l) = '0') THEN
c21 <= '1','0' AFTER period/2;
c24 <= '1','0' AFTER period/2;
ex_end <= '1'
;
ELSE
ex_end <= '1'
;
END IF;
WHEN N => IF (PSW (3) = '1') THEN
c21 <= '1'
,
' 0'AFTER period/2;
c24 <= '1'
,
'0'AFTER period/2;
ex_end <= '1'
;
ELSE
ex_end <= '1'
;
END IF;WHEN V => IF (PSW(l) = '1') THEN
c21 <= '1'
,
' 0'
AFTER period/2;
c24 <= '1','0' AFTER period/2;
ex_end <= '1'
;
ELSE
ex_end <= '1'
;
END IF;
WHEN P => IF (PSW (3) = '0') THEN
c21 <= ' 1'
,
' 0'AFTER period/2;
c24 <= '1','0' AFTER period/ 2;
ex_end <= '1
'
;
ELSE
ex_end <= '1'
;
END IF;
WHEN OTHERS => NULL;
END CASE;
WHEN OTHERS => NULL;
END CASE;
END IF;
END PROCESS xorrjn;
adcjn : PROCESS (proc_state, ex_cyc)
"BEGIN
IF ((proc state =execute) AND (instruction =
adc) ) THEN
CASE ex_cyc IS
WHEN 1 => IF (immediate = '1') THEN
cl3 <='1','0'
AFTER period/2;
c8 <='1','0'
AFTER period/2;
ELSE
c7 <='1','0'
AFTER period/2;
c9 <='1','0'
AFTER period/2;
END IF;
WHEN 2 => IF (immediate = '1') THEN
clO <='1','0'
AFTER period/2;
cl <='1','0'
AFTER period/2;
ELSE
ell <='1','0'
AFTER period/2;
cl <='1','0'
AFTER period/2;
END IF;
WHEN 3 => cl7 <='1','0'
AFTER period/2;
ex_end<= '
1'
;
WHEN OTHERS => NULL;
END CASE;
END IF;
END PROCESS adcjn;
sbbjn : PROCESS (proc_state, ex_cyc)
BEGIN
IF ((proc state= execute) AND (instruction =
sbb) ) THEN
CASE ex eye IS
WHEN 1 => IF (immediate = '1') THEN
cl3 <='1','0'
AFTER period/2;
c8 <='1','0'
AFTER period/2;
ELSE
-B9-
c7 <= '1'
,
c9 <= '1'
,
END IF;
WHEN 2 => IF (immediate
clO <= '1'
cl <= '1'
,
c4 <= '1'
,
ELSE
ell <= '1'
cl <= '1'
,
c4 <= '1'
,
END IF;
WHEN 3 => cl7 <= '1','0'
ex_end <= '1'
;
WHEN OTHERS => NULL;
END CASE;END IF;
END PROCESS sbb in;
'0'AFTER period/2 ;
'0'AFTER period/2;
='1'
) THEN
AFTER period/2,'0'
AFTER period/2;'0'
AFTER period/2,
AFTER period/2,'0'
AFTER period/2;' 0'
AFTER period/2;
AFTER period/2;
stwjn : PROCESS (proc_state,ex_cyc)BEGIN
IF ( (proc_state =
execute) AND
CASE ex_cyc IS
WHEN 1 => c7 <= '1'
,
c9 <= 'I',
'0'
'0'
WHEN 2 => ell <= '1'
cl <= '1'
,
c2 <= '1'
,
c3 <= '1'
,
c4 <= '1'
,
,'0
' 0'
'0'
'0'
'0'
WHEN 3 => c21 <= '1'
c8 <= '1'
,
,'0
'0'
WHEN 4 => c4 <= '1'
,
' 0'
WHEN 5 => cl9 <= '1'
,'0
WHEN 6 => write mem
ex end <=
<=
'1'
WHEN OTHERS => NULL;
END CASE
END IF;
END PROCESS stw in
(instruction =
stw) ) THEN
AFTER period/2;
AFTER period/2;'AFTER period/2;
AFTER period/2;
AFTER period/2;
AFTER period/2;
AFTER period/2;'AFTER period/2;
AFTER period/2;
AFTER period/2;
'AFTER period/2;
'1';
ldwjn : PROCESS (proc_state,ex_cyc)
BEGIN
IF ( (proc_state= execute) AND
CASE ex eye IS
WHEN
WHEN
WHEN
WHEN
WHEN
WHEN
WHEN
=>
=>
=>
=>
=>
=>
=>
0'
0'
'00'
0'
0'
0'
'
0
(instruction = ldw) ) THEN
AFTER period/2;
AFTER period/2;
'AFTER period/2;
AFTER period/2;
AFTER period/2;
AFTER period/2;
AFTER period/2;'
AFTER period/2;
c7 <= '1'
c9 <='1'
ell <= '1
cl <='1'
c2 <= '1'
c3 <='1'
c4 <='1'
c21 <= '1.
read mem <= '
cl8<=
'1'
, '0
cl4<=
'1'
,'0
cl5<=
'1','0
ex_end<= '
1'
;
WHEN OTHERS => NULL;
END CASE;
END IF;
END PROCESS ldwjn;
stbjn : PROCESS (proc_state,ex_cyc)
BEGIN
IF ( (proc_state=execute) AND (instruction =
stb) ) THEN
CASE ex eye IS
WHEN 1 => c7 <='1','0'
AFTER period/2;
AFTER period/2;
AFTER period/2;
AFTER period/2;
-B10-
WHEN 2 =>
WHEN 3 =>
WHEN 4 =>
END
END
END IF;
PROCESS
WHEN
WHEN
WHEN
CASE ;
c9 <= '1'
,
ell <= '1'
cl <= '1'
,
c2 <= '1'
,
c3 <= '1',
c4 <= '1'
,
c21 <= '1'
c8 <= '1'
,
IF (byte =
IF (MAR(c4 <=
ELSE
c2 <=
c3 <=
END IF;
ELSE
IF (MAR(C2 <=
c3 <=
c4 <=
ELSE
c4 <=
END IF;
END IF;
5 => cl9 <= ' 1'
6 => write_mem
ex_end <=
OTHERS => NULL;
'0'AFTER period/2;
,
' 0'AFTER period/2;
'0'
AFTER period/2;'0'
AFTER period/2 ;'0'
AFTER period/2;'0'
AFTER period/2;
,
'0'AFTER period/2;
'0'AFTER period/2;
msb) THEN
0 ) ='0'
) THEN1','0'
AFTER period/2;
1','0'AFTER period/2;
1','0'AFTER period/2 ;
0 ) = '0'
) THEN1','0'
AFTER period/2 ;1','0'
AFTER period/2;1','0'
AFTER period/2;
1','0'AFTER period/2;
,
'0'
AFTER period/ 2;
'1'
;
stb in;
ldbjn : PROCESS (proe_state, ex_cyc
BEGIN
IF ( (proc_state =
execute) AND
CASE ex eye IS
WHEN 1 => c7 <= '1'
, '0
c9 <= '1'
, '0
WHEN 2 => ell <= '1'
,
'
cl <= '1'
, '0
c2 <= '1'
,
'0
c3 <= '1'
, '0
c4 <= '1'
, '0
WHEN 3 => c21 <= '1'
,
'
WHEN 4 => read mem <=
WHEN 5 => cl8 <='1'
,
'
WHEN 6 => IF (MAR(0) =
IF (sign =
cl2 <=
cl3 <=
ELSE
cl2 <=
cl3 <=
cl4 <=
END IF;
ELSE
IF (sign =
cl2 <=
ELSE
cl2 <=
cl4 <=
END IF;
END IF;
WHEN 7 => cl5<='1','
ex end<= '
1
WHEN OTHERS => NULL;
END CASE;
END IF;
(instruction = ldb) ) THEN
'AFTER period/2;
'
AFTER period/2;0'
AFTER period/2 ;'AFTER period/2
'AFTER period/2
'
AFTER period/2
'AFTER period/2,
0'AFTER period/2
'1';0'
AFTER period/2;
'0') THEN
'0') THEN
'1','0'AFTER period/2;
'1','0'AFTER period/2;
'1','0'AFTER period/2;
'1','0'AFTER period/2;
'1','0'AFTER pe riod/2 ;
'0'
) THEN
'1','0'AFTER period/ 2 ;
'1','0'AFTER period/2;
'1','0'AFTER period/2;
0'AFTER period/2;
-Bll-
END PROCESS ldbjn;
nopjn : PROCESS (proc_state, ex_cyc)BEGIN
IF ( (proc_state =
execute) AND (instruction =
nop) ) THEN
CASE ex_cyc IS
WHEN 1 => ex_end <= '1
'
;
WHEN OTHERS => NULL;
END CASE;
END IF;
END PROCESS nopjn;
hltjn : PROCESS (proc_state, ex_cyc)BEGIN
IF ( (proc_state =
execute) AND (instruction = hit)) THEN
CASE ex_cyc IS
WHEN 1 => proc_state <= idle;WHEN OTHERS => NULL;
END CASE;
END IF;
END PROCESS hitJn;
ldspjn : PROCESS (proc_state, ex_cyc)
BEGIN
IF ( (proc_state =
execute) AND (instruction = ldsp) ) THEN
CASE ex_cyc IS
WHEN 1 => c8 <= '1','0' AFTER period/2;
WHEN 2 => c4 <= '1','0' AFTER period/2;
WHEN 3 => c4 3<='1','0'
AFTER period/2;
ex_end <= '1
'
;
WHEN OTHERS => NULL;
END CASE;
END IF;
END PROCESS ldsp_in;
stspjn : PROCESS (proc_state,ex_cyc)
BEGIN
IF ((proc state =execute) AND (instruction =
stsp) ) THEN
CASE ex_cyc IS
WHEN 1 => c42 <='1','0'
AFTER period/2;
WHEN 2 => cl7 <='1','0'
AFTER period/2;
ex_end<= '
1'
;
WHEN OTHERS => NULL;
END CASE;
END IF;
END PROCESS stspjn;
call_in : PROCESS (proc_state, ex_cyc)
BEGIN
IF ((proc state= execute) AND (instruction =
call)) THEN
CASE ex eye IS
WHEN 1 => c2 9 <='1','0'
AFTER period/2;
c8 <='1','0'
AFTER period/2;
WHEN 2 => cl9<='1','0'
AFTER period/2;
c26 <='1','0'
AFTER period/2;
c4 <-'1','0'
AFTER period/2;
WHEN 3 => write_mem<= '1';
WHEN 4 =>c24<=
'1','0'AFTER period/2;
C27 <='1','0'
AFTER period/2;
ex_end<= '
1'
;
WHEN OTHERS => NULL;
END CASE;
END IF;
END PROCESS calljn;
retjn : PROCESS (proc_state, ex_cyc)
BEGIN
IF ((proc state= execute) AND (instruction =
ret)) THEN
-B12-
CASE ex eye IS
WHEN 1 => c28 <= '1'
WHEN 2 => c26 <= '1'
WHEN 3 => read mem <
WHEN 4 => cl8 <= '1'
WHEN 5 => cl4 <= '1'
WHEN 6 => clO <= '1'
c3 <= '1',
WHEN 7 => c24 <= '1'
ex end <=
WHEN OTHERS => NULL;END CASE;
END IF;
END PROCESS ret in,
AFTER period/2;
AFTER period/2;
'0'
'0'
= '1'0'
AFTER period/2' 0'
AFTER period/2'0'
AFTER period/20'
AFTER period/2;'0'
AFTER period/2;
'1'
,
'0'
'1'
,
'0'
<= '1',
0'AFTER period/2;
AFTER period/2;
AFTER period/2;0'
AFTER period/2;
pushjn : PROCESS (proc_state, ex eye)
BEGIN~~
IF ( (proc_state =
execute) AND (instruction =
push) ) THEN
CASE ex_cyc IS
WHEN 1 => CASE stack_var IS
WHEN CCR => NULL;
WHEN OTHERS => c8 <= ' 1'
,
END CASE;WHEN 2 => CASE stack_var IS
WHEN CCR => c4 <=
c3 <=
WHEN OTHERS => c4
END CASE;WHEN 3 => cl9 <= '1','0
c2 6 <= '1'
, '0
WHEN 4 => c27 <= ' 1'
,
'0
write_mem <= '1';
ex_end <= '1'
;
WHEN OTHERS => NULL;
END CASE;
END IF;
END PROCESS push_in;
pop in : PROCESS (proc_state, ex_cyc)
BEGIN
IF ( (proc_state =
execute) AND (instruction =
pop) ) THEN
CASE ex_cyc IS
AFTER period/2
AFTER period/2
AFTER period/2
WHEN 1 => c2 8 <= '1','0'
WHEN 2 => c2 6 <= '1'
,
' 0'
WHEN 3 => read_mem <= ':
WHEN 4 => cl8 <= '1'
,
'0'
WHEN 5 => cl4 <= '1'
,
'0'
WHEN 6 => CASE stack_var IS
WHEN CCR => clO <= '1
AFTER period/2;
AFTER period/2;
AFTER period/2;
AFTER period/2;
0'AFTER period/2;
c2 <= '1','0' AFTER period/2 ;
c4 <= '1','0' AFTER period/2;
=> cl5 <= '1','0' AFTER period/2;WHEN OTHERS
END CASE;
ex_end <= '1'
;
WHEN OTHERS => NULL;
END CASE;
END IF;
END PROCESS popjn;
shlljn : PROCESS (proc_state,ex_cyc)
BEGIN
IF ((proc state =execute) AND (instruction =
shll) ) THEN
CASE ex~cyc IS
WHEN 1 => cl3 <= '1','0' AFTER period/2;
c8 <='1','0'
AFTER period/2;
WHEN 2 => c6 <= '1','0' AFTER period/2;
WHEN 3 => Cl7 <= '1','0' AFTER period/2;
ex end <= '1'
;
-B13-
WHEN OTHERS => NULL;
END CASE;
END IF;
END PROCESS shlljn;
shrljn : PROCESS (proc_state, ex_cyc)BEGIN
IF ( (proc_state =
execute) AND (instruction =
shrl) ) THEN
CASE ex_cyc IS
WHEN 1 => cl3 <= '1','0' AFTER period/2;c8 <= '1','0' AFTER period/2;
WHEN 2 => c5 <= '1','0' AFTER period/2;
WHEN 3 => cl7 <= '1','0' AFTER period/2;
ex_end <= '1
'
;
WHEN OTHERS => NULL;
END CASE;
END IF;
END PROCESS shrljn;
shra_in : PROCESS (proc_state, ex_cyc)BEGIN
IF ( (proc_state =execute) AND (instruction =
shra) ) THEN
CASE ex_cyc IS
WHEN 1 => cl3 <= '1','0' AFTER period/2;
c8 <= '1','0' AFTER period/2;
WHEN 2 => c5 <= '1','0' AFTER period/2;
c6 <= '1','0' AFTER period/2;
WHEN 3 => c^7- 'l','0'
AFTER period/2;
WHEN OTHERS
END CASE;
END IF;
END PROCESS shrajn;
END BLOCK executeJnstr;
END BLOCK control_unit ;
ALU_regs : PROCESS (c7, c8 , c9)
VARIABLE dumint : integer;
VARIABLE dumbin : qsim_state_vector (15 DOWNTO 0) ;
BEGIN
IF <(c9'EVENT) AND (c9 = '1')) THEN
dumint := qsim_to_int (Rs2) ;
dumbin(15 DOWNTO 0) := int_to_16bit (registers (dumint) ) ;
Rb <= dumbin;
END IF;
ASSERT NOT((c7 = '1') AND (c8 = '1'))
REPORT "Ra assignment error Multiplesources"
SEVERITY ERROR;
IF((c7'
EVENT) AND (c7 = '1')) THEN
dumint := qsim_toJnt (Rsl) ;
dumbin (15 DOWNTO 0) := int_to_16bit (registers (dumint )) ;
Ra <= dumbin;
END IF;
IF ((c8'EVENT) AND (c8 = '1')) THEN
dumint := qsim_to_int (Rd) ;
dumbin(15 DOWNTO 0) := int_to_16bit (registers (dumint )) ;
Ra <= dumbin ;
END IF;
END PROCESS ALU_regs;
Rc_reg : PROCESS (c40, c41, c42 , c29)
BEGIN
ASSERT NOT(((c40 = '1') AND (c41 = '1')) OR
((C40 = '1') AND (c42 = '1')) OR
((c40 = '1') AND (c29 = '1')) OR
((c41 = '1') AND (c42 = '1')) OR
-B14-
((c41 = '1') AND (c29 = '1')) OR
(<c42 = '1') AND (c29 = '1')))REPORT "Rc assignment error Multiple
sources"
SEVERITY ERROR;
IF ((c40'EVENT) AND (c40 = '1')) THEN
Rc <= ALU_bus;
END IF;
IF((c41'
EVENT) AND (c41 = '1')) THEN
Rc <= PS_bus;
END IF;
IF((c42'
EVENT) AND (c42 = '1')) THEN
Rc <= SP;
END IF;
IF((c29'
EVENT) AND (c29 = '1')) THEN
Rc <= PC-
END IF;
END PROCESS Rc_reg;
ALU : PROCESS (cl, c2, c3, c4 )VARIABLE carry, borrow
sum, diff
res, operand
concat
j
VARIABLE
VARIABLE
VARIABLE
VARIABLE
BEGIN
concat := (cl & c2 & c3 & c4);
IF (cl =' 1'
) THEN
ASSERT NOT((clO = '0') AND (ell =
REPORT "ALU input error Rb
SEVERITY ERROR;
IF (clO =' 1'
) THEN
operand := Rimm;
ELSE
operand := Rb;
END IF;
CASE concat IS
WHEN"1000"
|"1111"
=>
qsim_state;
qsim_state_vector (2 DOWNTO 0) ;qsim_state_vector (15 DOWNTO 0)qsim_state_vector (3 DOWNTO 0) ;
integer;
'0'
or
))Rimm missing
IF (concat = "1000") THEN
carry:= PSW(0) ;
ELSE
carry:=
' 0'
;
END IF;
FOR i IN Ra'REVERSE_RANGE LOOP
sum := (Ra(i) & operand (i) & carry)
CASE sum IS
=>
=>
=>
=>
=>
=>
=>
=>
000"
001"
'010"
011"
'100"
'101"
110"
111"
res (i)res (i)
res (i)
res (i)
res (i)
res (i)
res (i)
res (i)
0'; carry : ='0'
l'
; carry : =' 0'
1'; carry : ='0'
0'
; carry : =' 1'
1'; carry : =' 0'
0'
; carry : ='1'
0'; carry : ='1'
l'; carry :='1'
OTHERS => NULL;
WHEN"1001"
=>
WHEN
WHEN
WHEN
WHEN
WHEN
WHEN
WHEN
WHEN
WHEN
END CASE;
END LOOP;
IF (concat = "1000") THEN
PSW(0)<= carry; carry bit
PSW (1) <= ( (NOT(Ra (15) ) )
(NOT (operand (15) ) )
AND (res (15))) OR
(operand (15) ) AND
ELSE
NULL;
END IF;
borrow := PSW(0) ;
FOR i IN Ra'REVERSE_RANGE LOOP
diff := (Ra(i) & operand (i) & borrow)
CASE diff IS
AND
(((Ra(15))) AND
(NOT (res (15) ) ) ) ;
-B15-
= '0';
borrow : ='0'
= 'l';
borrow : ='0'
= 'l';
borrow : ='0'
= '0';
borrow : ='1'
= '1';
borrow : =' 0'
= '0'
;
borrow : ='1'
='0'
;
borrow : ='1'
= '1';
borrow : ='1'
WHEN"000"
=> res (i)
WHEN"001"
=> res(i)
WHEN"010"
=> res(i)
WHEN"011"
=> res (i)
WHEN"100"
=> res (i)
WHEN"101"
=> res(i)
WHEN"110"
=> res (i)
WHEN"111"
=> res(i)
WHEN OTHERS => NULL;
END CASE;
END LOOP;
PSW(0) <= borrow; carry bit
PSW(l) <= ((Ra(15)) AND (NOT (operand (15) ) )AND (NOT(res(15) ) ) ) OR ( (NOT (Ra (15) ) )AND (operand (15) ) AND (res (15) ) ) ;
WHEN"1010"
=> res := Ra AND operand;
PSW(0) <= '0'; carry bit
PSW(l) <= '0'; overflow bit
WHEN"1011"
=> res := Ra OR operand;
PSW(0) <= '0'
;
PSW(l) <= '0';
WHEN"1100"
=> res := Ra XOR operand;
PSW(0) <= ' 0'
;
PSW(l) <= '0'
;
WHEN OTHERS => NULL;
END CASE;
IF (concat = "1111") THEN
NULL;
ELSE
IF (res =zeros) THEN
PSW (2) <= '1'; zero bit
ELSE
PSW (2) <= ' 0'
;
END IF;
IF (res (15) = '1') THEN
PSW (3) <= '1'; negative bit
ELSE
PSW (3) <='0'
;
END IF;
END IF;
ALU_bus <= res;
c4 0 <='1','0'
AFTER period/2;
ELSE
CASE concat IS
WHEN"0000"
=> NULL;
WHEN"0001"
=> ALU_bus <= Ra;
c40 <='1','0'
AFTER period/2;
WHEN"0010"
=> IF (clO = '1') THEN
ALU bus <= Rimm;
c4 0 <='1'
AFTER period/2,'0'
AFTER period;
ELSE
ALU_bus <= Rb;
c40 <='1','0' AFTER period/2;
END IF;
WHEN"0011"
=> ALU_bus <= PSW;
c4 0 <='1','0'
AFTER period/2;
WHEN"0100"
=> PSW <= Ra;
WHEN"0101"
=> IF (clO = '1') THEN
PSW <= Rimm;
ELSE
-B16-
PSW <= Rb;
END IF;
WHEN"0110"
=> FOR i IN 7 DOWNTO 0 LOOP
j := i+8;
ALUJdus ( i ) <= Ra ( j ) ;END LOOP;
c40 <= '1','0' AFTER period/2;
WHEN"0111"
=> FOR i IN 15 DOWNTO 8 LOOP
j := i-8;
ALUJms ( i ) <= Ra ( j ) ;END LOOP;
c40 <= '1','0' AFTER period/2;
WHEN OTHERS => NULL;
END CASE;
END IF;
END PROCESS ALU;
POWER_SHIFTER : PROCESS (c5, c6)
VARIABLE dumint, j : integer;
VARIABLE dumbit
"
: bit_vector (15 DOWNTO 0) ;
VARIABLE res : qsim_state_vector (15 DOWNTO 0);
VARIABLE concat : qsim_state_vector (1 DOWNTO 0) ;
VARIABLE store_sign : qsim_state;
BEGIN
IF (<c5 = '1') OR (c6 = '1')) THEN
dumint := qsim_to_int (Rimm) ;
ASSERT NOT ((dumint < 1 ) OR (dumint > 8))
REPORT "POWER SHIFTER error Number ofshifts"
SEVERITY ERROR;
store_sign := Ra(15);
concat := (c5 & c6) ;
CASE concat IS
WHEN"00"
=> NULL;
WHEN"01"
=> j:= 16 - dumint;
PSW(0)<= Ra(j) ;
dumbit (15 DOWNTO 0) := qsim_to_bin (Ra) ;
dumbit := dumbit SLL dumint;
res (15 DOWNTO 0) := bin_to_qsim (dumbit ) ;
WHEN"10"
=> j:= dumint - 1;
PSW(0)<= Ra( j) ;
dumbit (15 DOWNTO 0) := qsim_to_bin (Ra) ;
dumbit := dumbit SRL dumint;
res (15 DOWNTO 0) := bin_to_qsim (dumbit ) ;
WHEN"11"
=> j:= dumint - 1 ;
PSW(0)<= Ra(j) ;
dumbit (15 DOWNTO 0) := qsim_to_bin (Ra) ;
dumbit := dumbit SRA dumint;
res(15 DOWNTO 0) := bin_to_qsim (dumbit ) ;
WHEN OTHERS => NULL;
END CASE;
IF (res = zeros) THEN
PSW (2) <='1'
;
ELSE
PSW (2)<= '0';
END IF;
IF (res (15)= '1') THEN
PSW (3)<=
'1'
;
ELSE
PSW (3)<=
'0'
;
IFn)(:(store_sign = '1') AND (res (15) = '0')) THEN
psw(i)<= 'l';
ELSE
PSW(l)<= '0';
END IF;
PS bus <= res;
c41 <='1','0'
AFTER period/2;
END IF;
-B17-
END PROCESS POWER_SHIFTER;
stack_ptr : PROCESS (c27, c28, c43)VARIABLE dumbin : qsim_state_vector (15 DOWNTO 0) ;VARIABLE concat : qsim_state_vector (1 DOWNTO 0);VARIABLE dumint : integer;
BEGIN
ASSERT NOT(((c27 = '1') OR (c28 = '1')) AND (c43 = '1'))REPORT "SP assignment error Multiple
sources"
SEVERITY ERROR;
concat := (c27 & c28);
CASE concat IS
WHEN"01"
=> dumint := qsim_to_int (SP) ;dumint : = dumint + 2 ;
dumbin (15 DOWNTO 0) := int_to_16bit (dumint) ;SP <= dumbin;
WHEN"10"
=> dumint := qsim_to_int (SP) ;dumint : = dumint - 2 ;
dumbin(15 DOWNTO 0) := int_toJ6bit (dumint ) ;SP <= dumbin;
WHEN OTHERS => NULL;
END CASE;
IF ((c43'
EVENT) AND (c43 = '1')) THEN
SP <= Rc;
END IF;
END PROCESS stack_ptr;
Ri_reg : PROCESS
BEGIN
WAIT ON cl8 UNTIL (cl8 = '1');
Ri <= MDR;
END PROCESS Ri_reg;
Rimm_reg : PROCESS (cl2 , cl3, cl4 )
VARIABLE concat : qsim_state_vector (2 DOWNTO 0) ;
VARIABLE ptr : integer;
BEGIN
concat:= (cl2 & cl3 & cl4);
CASE concat IS
WHEN"000"
=> NULL;
WHEN"001"
=> Rimm <= Ri;
WHEN"010"
=> FOR i IN 5 DOWNTO 0 LOOP
Rimm ( i ) <= Ri ( i ) ;
END LOOP;
FOR i IN 15 DOWNTO 6 LOOP
Rimm(i)<= '0';
END LOOP;
WHEN"011"
=> FOR i IN 5 DOWNTO 0 LOOP
Rimm(i)<= Ri (i) ;
END LOOP;
IF (Ri(5) = '1') THEN
FOR i IN 15 DOWNTO 6 LOOP
Rimm(i)<= '1'
;
END LOOP;
ELSE
FOR i IN 15 DOWNTO 6 LOOP
Rimm(i)<= '0'
;
END LOOP;
END IF;
WHEN"100"
=> FOR i IN 7 DOWNTO 0 LOOP
Rimm(i)<= Ri (i) ;
END LOOP;
FOR i IN 15 DOWNTO 8 LOOP
Rimm(i)<=
'0'
;
END LOOP;
WHEN"101"
=> FOR i IN 7 DOWNTO 0 LOOP
Rimm(i)<= Ri (i) ;
END LOOP;
-B18-
IF (Ri(7) ='1'
) THEN
FOR i IN 15 DOWNTO 8 LOOP
Rimm(i) <= ' 1'
;
END LOOP;
ELSE
FOR i IN 15 DOWNTO 8 LOOP
Rimm(i) <= ' 0'
;
END LOOP;
END IF;
WHEN"110"
=> FOR i IN 7 DOWNTO 0 LOOP
ptr := 8+i;
Rimm(i) <= Ri (ptr) ;END LOOP;
FOR i IN 15 DOWNTO 8 LOOP
Rimm ( i ) <= '0
'
;
END LOOP;
WHEN"111"
=> FOR i IN 7 DOWNTO 0 LOOP
ptr := 8+i;
Rimm(i) <= Ri (ptr) ;
END LOOP;
IF (Ri(15) = '1') THEN
FOR i IN 15 DOWNTO 8 LOOP
Rimm(i) <= ' 1'
;
END LOOP;
ELSE
FOR i IN 15 DOWNTO 8 LOOP
Rimm(i) <= ' 0'
;
END LOOP;
END IF;
> NULL;WHEN OTHERS
END CASE;
END PROCESS Rimm reg;
reg_file_ptrs : PROCESS
BEGIN
WAIT ON c20 UNTIL (c20 ='1
'
) ;
Rd <= MDR(10 DOWNTO 8);
Rsl <= MDR(5 DOWNTO 3) ;
Rs2 <= MDR(2 DOWNTO 0);
END PROCESS reg_file_ptrs ;
reg file : PROCESS (cl5, cl6, cl7)_
VARIABLE dumbin : qsim_state_vector (15 DOWNTO 0);
VARIABLE concat : qsim_state_vector (2 DOWNTO 0) ;
VARIABLE dumint : integer;
VARIABLE ptr : integer;
BEGIN
concat:= (cl5 & cl6 & cl7) ;
CASE concat IS
=> NULL;
=> IF (Rd = "000") THEN
NULL;
ELSE
dumint := qsim_to_int (Rd) ;
registers (dumint)<= qsim_to_int (Rc) ;
END IF;
=> dumint := qsim_to_int (Rd) ;
dumbin (15 DOWNTO 0) :=
int to_16bit (registers (dumint) ) ;
FOR i IN 15 DOWNTO 8 LOOP
ptr := i-8;
dumbin(i):= Rimm(ptr);
END LOOP;
registers (dumint)<= qsim_to_int (dumbin) ;
=> dumint := qsim_to_int (Rd) ;
dumbin (15 DOWNTO 0) :=
int to_16bit (registers (dumint) ) ;
FOR i IN 7 DOWNTO_0 LOOP
WHEN"000"
WHEN"001'
WHEN"010'
WHEN"011"
-B19-
dumbin (i) := Rimm(i);END LOOP;
registers (dumint) <=qsim_to_int (dumbin) ;
WHEN"100"
=> dumint :=qsim_to_int (Rd) ;
registers (dumint) <=qsim to int (Rimm) ;
WHEN"101"
=> FOR i IN 0 TO 7 LOOP~ ~
registers (i) <= 0;END LOOP;
WHEN OTHERS => NULL;END CASE;
END PROCESS regjile;
mem_data_reg : PROCESS (cl9, c36)BEGIN
ASSERT NOT((cl9 = '1') AND (c36 = '1'))REPORT "MDR assignment error Multiple sources"
SEVERITY ERROR;IF (
(cl9'
EVENT) AND (cl9 = '1')) THEN
MDR <= Rc;
ELSIF ((c36'
EVENT) AND (c36 = '1')) THEN
MDR <= data_bus;ASSERT NOT( (data_bus =
highjmp) OR (datajbus =
unknown))REPORT "MDR assignment error Floating
bus"
SEVERITY ERROR;ELSE
NULL;
END IF;
END PROCESS mem_data_reg;
mem_addr_reg : PROCESS (c21 , c23, c25, c26)
VARIABLE dumbin : qsim_state_vector (15 DOWNTO 0) ;BEGIN
ASSERT NOT(((c21 = '1') AND (c23 = '1')) OR
((c21 = '1') AND (c25 = '1')) OR
((c21 = '1') AND (c26 = '1')) OR
((c23 = '1') AND (c25 = '1')) OR
((c23 = '1') AND (c26 = '1')) OR
((c25 = '1') AND (c26 = '1')))REPORT "MAR assignment error Multiple
sources"
SEVERITY ERROR;
IF((C21'
EVENT) AND (c21 = '1')) THEN
MAR <= Rc;
ELSIF ((C25'
EVENT) AND (c25 = '1')) THEN
MAR <= PC;
ELSIF((c23'
EVENT) AND (c23 = '1')) THEN
dumbin (15 DOWNTO 0) := int_to_16bit (rom_int_addr (vec_num) ) ;
MAR <= dumbin;
ELSIF((c26'
EVENT) AND (c26 = '1')) THEN
MAR <= SP;
ELSE
NULL;
END IF;
END PROCESS mem_addr_reg;
prgm_cntr : PROCESS (c22, c24 )
VARIABLE dumint : integer;
VARIABLE dumbin : qsim_state_vector (15 DOWNTO 0);
BEGIN
ASSERT NOT(((c22 = '1') AND (c24 = '1')))
REPORT "PC assignment error Multiplesources"
SEVERITY ERROR;
IF <<c22'EVENT) AND (c22 = '1')) THEN
dumint := qsim_to_int (PC) ;
dumint := dumint + 2;
dumbin(15 DOWNTO 0) := int_to_16bit (dumint) ;
PC <= dumbin;ELSIF
((c24'
EVENT) AND (c24 = '1')) THEN
PC <= Rc;
-B20-
ELSE
NULL;
END IF;
END PROCESS prgm_cntr;
mem_access : PROCESS
BEGIN
WAIT ON read_mem,write_mem UNTIL (read_mem ='1'
OR
write_mem =' 1'
) ;IF (read_mem = '1') THEN
c35 <='!'; address bus <= MAR
c32 <='!'; word <= 1
c33 <= '1'AFTER tsetup; vma <= 1
c31 <= '1'AFTER (tsetup+td) ; rd_bar <= 0
WAIT ON mem_rdy UNTIL (mem_rdy = '0');WAIT ON mem_rdy UNTIL (mem_rdy = '1');
c36 <= '1','0' AFTER period/2; MDR <= databus
c31 <= '0'
c35 <= '0'
c32 <= '0'
c33 <= '0'
read_mem <= '0';
END IF;
IF (write_mem = '1') THEN
c35 <= '1'; address bus <= MAR
c37 C= '1'; cpu_data_out <= MDR
IF (write_word = '1') THEN word <= 1 or 0
c32 <= '1'
;
ELSE
c32 <= '0'
;
END IF;
c33 <= '1'AFTER tsetup; vma <= 1
c30 <= '1'AFTER (tsetup+td) ; wr_bar <= 0
WAIT ON mem_rdy UNTIL (mem_rdy= '0');
WAIT ON mem rdy UNTIL (mem_rdy= '1')
rd_bar <= 1
address bus <= highjmpword <= 0
vma <= 0
c35 <= '0'
c37 <= '0'
c32 <= '0'
c33<=
'0'
c30 <= '0'
write_mem<= ' 0'
;
END IF;
END PROCESS mem_access;
i_o : PROCESS (C30,c31,c32,c33,c34,c35,c37)
BEGIN
IF((c30'
EVENT) AND (c30 = '1')) THEN
wr bar <='0'
;
ELSIF T(c30'EVENT) AND (c30 = '0')) THEN
wr_bar<= ' 1'
;
ELSE
NULL;
END IF;
IF<(c31'
EVENT) AND (c31 = '1')) THEN
ELSIF7(c31'
EVENT) AND (c31 = '0')) THEN
rd_bar<= ' 1
'
;
ELSE
NULL;
END IF;
IF ((c32'EVENT) AND (c32 = '1')) THEN
word<= ' 1'
;
ELSIF <(c32'EVENT) AND (c32 = '0')) THEN
word<= '0'
;
ELSE
NULL;
END IF;
IF((c33'
EVENT) AND (c33 = '1')) THEN
-B21-
address bus <= highjmpcpu_data_out <= high_impword <= 0
vma <= 0
wr bar <= 1
vma <= '1
'
;
ELSIF((c33'
EVENT) AND (c33 = '0')) THEN
vma <= '0
'
;
ELSE
NULL;
END IF;
IF<(c34'
EVENT) AND (c34 = '1')) THEN
inta <= ' 1'
;
ELSIF((c34'
EVENT) AND (c34 = '0')) THEN
inta <= ' 0'
;
ELSE
NULL;
END IF;
IF ((c35'EVENT) AND (c35 = '1')) THEN
address_bus <= MAR(15 DOWNTO 1);addrjsb <= MAR(O);
ELSIF((c35'
EVENT) AND (c35 = '0')) THEN
FOR i IN 14 DOWNTO 0 LOOP
addressjDus (i) <= ' Z'
;
END LOOP;
addrjsb <= ' Z'
;
ELSE
NULL;
END IF;
IF((c37'
EVENT) AND (c37 = '1')) THEN
cpu_data_out <= MDR;
ELSIF((c37'
EVENT) AND (c37 = '0')) THEN
cpu_data_out <= highjmp;
ELSE
NULL;
END IF;
END PROCESS i_o;
END BLOCK cpu;
MEMORY BANK SELECT UNIT
mem_bank_sel_unit : BLOCK
BEGIN
mbsu : PROCESS (word, rd_bar,wr_bar, addrjsb, vma)
VARIABLE intJ, int_2, int_3 : qsim_state;
BEGIN
int_l := (NOT(wr_bar) ) AND (word) ;
int 2 := (NOT (wr_bar) ) AND (addrjsb) AND (NOT (word) ) ;
int_3 := (NOT (addrjsb) ) AND (NOT (wr_bar) ) AND (NOT (word) ) ;
ASSERT NOT((rd_bar = '0') AND (wr_bar = '0'))
REPORT "wr bar & rd_bar cannot be bothLOW"
SEVERITY ERROR;
oe_bar<= rd_bar;
cs_bar<= NOT (vma);
wrl_bar<= NOT(int_l
wr2_bar<= NOT (intJ
END PROCESS mbsu;
OR int_3 ) ;
OR int 2 ) ;
END BLOCK mem bank sel unit;
__###########f####f
###?###################################################
CPU MEMORY TIME HANDSHAKING UNIT
cpu mem_time_unit : BLOCK
"BEGIN
handshake : PROCESS
VARIABLE count : integer;
BEGIN
WAIT ON rd bar,wr_bar UNTIL ( (rd_bar= '0') OR (wr_bar = '0'));
IF ((rdjbar'
EVENT) AND (rd_bar = '0') AND (vma = '1')) THEN
mem_rdy<=
'
0'
;
WAIT ON clock UNTIL (clock = '1'); Tl end
-B22-
WAIT ON clock UNTIL (clock ='1
'
) ;
mem_rdy<= '1' AFTER (w_states *
period);
END IF;
IF ((wr_bar'
EVENT) AND (wr_bar =
mem_rdy<= '
0'
;
WAIT ON clock UNTIL (clock =
WAIT ON clock UNTIL (clock =
mem_rdy<= ' 1'
AFTER (w_states *period);
END IF;
END PROCESS handshake;
T2 end
wait states
0') AND (vma = '1')) THEN
'1');'1
'
) ;
Tl end
T2 end
wait states
END BLOCK cpu_mem_time_unit ;
DATA BUS
data_bus_res : BLOCK
BEGIN
resjunc : PROCESS (mem_data_out, cpu_data_out)
VARIABLE l,r : qsim_state;
VARIABLE dumbin : qsim_state_vector (15 DOWNTO 0) ;
BEGIN
FOR i INmem_data_out'
RANGE LOOP
data_bus (i) <= wired_or (mem_data_out (i) ,cpu_data_out (i) ) ;
END LOOP;
END PROCESS resjunc;
END BLOCK data bus res;
MEMORY
memory : BLOCK
BEGIN
memjnit : PROCESS (run)
BEGIN
IF((run'
EVENT) AND (run = '1')) THEN
Interrupt vectors
mem_bankl (0) <= 2;
mem_bank2(0)<= 0;
mem_bankl (1) <= 2;
mem_bank2(l)<= 32
mem_bankl (2) <= 2;
mem_bank2(2)<= 64
mem_bankl (3) <= 2;
mem bank2(3)<= 96
"0200"
reset
"0220"
external interrupt"0240"
opcode error
address misalignment
Zero memorylocations for I/O and stack
FOR i IN 5 TO 255 LOOP
mem_bankl (i)<= 0;
mem_bank2 (i) <= 0;
END LOOP;
Code for RESET
mem_bankl (256)<=
mem_bank2(256)<=
mem_bankl(257)<=
mem_bank2 (257)<=
mem_bankl (258)<=
mem_bank2(258)<=
mem_bankl (259)<=
mem_bank2(259)<=
mem_bankl(2 60)<=
mem_bank2(2 60)<=
mem_bankl (261)<=
mem bank2 (261)<=
105;"6900"
0;161;
"A18F"
143;
73;
0;145;
"9103"
3;
177;"B100"
0;
121;"7900"
0;
Code for externalinterrupt
mem bankl (272) <=201;
"C900'
STPSW Rl
AND Rl, 01111b
LDPSW Rl
LDHI Rl,03h
LDLO Rl, OOh
JMP ALW,R1
PUSH Rl
-B23-
mem
mem
mem
mem
mem
mem
mem
mem
mem
mem
mem
mem
mem
bank2
"bankl
"bank2
bankl
"bank2
bankl
"bank2
bankl
bankl
"bank2
(272)
(273)
(273)
(274)
(274)
(275)
(275)
(276)
(276)
(277)
(277)
(278)
(278)
<= 0;<= 105;-
<= 0;<= 193;-
<= 135;<= 73;<= 0;<= 233;-
<= 0;<= 232;<= 0;<= 168;<= 0;
Program
mem_bankl
mem_bank2
mem_bankl
mem_bank2
mem_bankl
mem_bank2
mem_bankl
mem_bank2
mem bankl
mem_bank2
mem bankl
mem bank2
mem_bankl
mem_bank2
mem_bankl
mem_bank2
mem_bankl
mem_bank2
mem_bankl
mem_bank2
mem_bankl
mem bank2
code
(384) <=
(384) <=
(385) <=
(385) <=
(386) <=
(386) <=
(387) <=
(387) <=
(388) <=
(388)
(389)
(389)
(390)
(390)
(391) <
(391) <
(392)
(392)
(393)
(393)
(394)
(394)
149;-
6;181;-
32;189;-
0;148;-
0;180;-
255;
5;-
32;
6;-
36;145;-
3;177;-
32;137;-
0;
4 0;
0;
END
Subroutine
mem_bankl (400)<= 146;-
mem_bank2 (400)<= 4 ;
mem_bankl(4 01) <= 178;-
mem_bank2 (401)<= 176;
mem_bankl (4 02) <= 6;-
mem_bank2(4 02) <= 131;
mem_bankl(4 03)<= 206;-
mem_bank2 (403)<= 0;
mem_bankl(4 04) <= 236;-
mem bank2(404)<= 0;
mem_bankl(4 05)<= 219;-
mem_bank2(4 05)<= 0;
mem_bankl(4 06)<= 59;
mem bank2(406)<= 6;
mem_bankl(4 07)<= 26;
mem_bank2(4 07)<= 6;
mem_bankl(4 08)<= 18;
mem bank2(408)<= 130;
mem bankl (409)<= 50;
mem bank2(409)<= 131;
mem_bankl(410)<= 98;
mem_bank2(410)<= 152;
mem_bankl (411)<= 67;
mem_bank2(411)<= 24;
mem_bankl(412)<= 19;
mem_bank2(412)<= 136;
mem bankl (413)<= 168;
mem_bank2(413)<= 0;
IF;
-"6900"
STPSW Rl
-"C187"
OR Rl, 00111b
-"4900"
LDPSW Rl
-"E900"
POP Rl
-"E800"
POP PSW
-"A800"
RET
-"9506"
LDHI R5,06h
-"B520"
LDLOR5,20h
-"BD00"
LDSP R5
-"9400"
LDHI R4,00h
LDLO R4,FFh
-"0520"
ADC R5,R4,R0
-"0624"
ADC R6,R4,R4
LDHI Rl,03h
"B120"
LDLO Rl,20h
CALL Rl
HLT
LDHI R2,04h
"B2B0"LDLO R2,B0h
ADC R6,011B
"CE00"PUSH R6
"EC00"
POP R4
"DB00" STSP R3
"3B06" STW R3, [R2+R0]
"1A06" LDW R2, [R2+R0]
SHLLR2,0010B
SHRLR2,0011B
"6298" STB R2, [R3+R0] ,h
"4318" LDB R3, [R3+R0] ,1
"1988" SHLLR3,1000B
"A800" RET
-B24-
END PROCESS memjnit;
bankl_access : PROCESS (oejbar, cs_bar,wrl_bar)VARIABLE mem_val : integer;VARIABLE dum_int,j : integer;VARIABLE dum_bin : qsim_state_vector (7 DOWNTO 0) ;VARIABLE interm dat : qsim state vector(7 DOWNTO 0)
BEGIN_ _
IF ((oejbar'
EVENT) AND (oejbar = '0') AND (csjbar =
'0')) THENdumjnt :=
qsim_to_int (address_bus) ;mem_val := mem_bankl (dumjnt ) ;dum_bin(7 DOWNTO 0) := int_to_8bit (mem val) ;FOR i IN 15 DOWNTO 8 LOOP
_
j := i-8;
mem_data_out (i) <= dum_bin(j) AFTER t o;END LOOP;
'"
_
ELSIF ((wrl_bar'
EVENT) AND (wrl_bar = '0') AND (cs bar = '0')) THEN
interm_dat := data_bus(15 DOWNTO 8) ;mem_val :=
qsim_to_int (address bus);dumjnt :=
qsim_to_int (interm_dat) ;mem_bankl (mem_val) <= dumjnt;
ELSIF ((oe_bar'
EVENT) AND (oejbar = '1')) THEN
FOR i IN 15 DOWNTO 8 LOOP
mem_data_out (i) <= ' Z'AFTER totd;
END LOOP;
ELSE
NULL;
END IF;
END PROCESS bankl_access;
bank2_access : PROCESS (oe_bar, cs_bar,wr2_bar)VARIABLE mem_val : integer;
VARIABLE dumjnt : integer;VARIABLE dum_bin : qsim_state_vector (7 DOWNTO 0) ;VARIABLE interm_dat : qsim_state_vector (7 DOWNTO 0) ;
BEGIN
IF ((oejbar'
EVENT) AND (oe_bar = '0') AND (csjbar = '0')) THEN
dum_int := qsim_to_int (addressjous) ;
mem_val := mem_bank2 (dum_int ) ;
dum_bin(7 DOWNTO 0) := int_to_8bit (mem_val) ;
FOR i IN 7 DOWNTO 0 LOOP
mem_dat a_out ( i ) <= dum_bin(i) AFTER t_o;
END LOOP;
ELSIF ((wr2_bar'
EVENT) AND (wr2_bar = '0') AND (cs_bar = '0')) THEN
interm_dat := data_bus (7 DOWNTO 0) ;
mem val := qsim_to_int (addressjbus) ;
int := qsim_to_int (interm_dat ) ;
mem_bank2 (mem_val)<= dumjnt;
ELSIF ((oe_bar'
EVENT) AND (oe_bar = '1')) THEN
FOR i IN 7 DOWNTO 0 LOOP
mem_data_out (i) <= 'Z'AFTER totd;
END LOOP;
ELSE
NULL;
END IF;
END PROCESS bank2_access;
END BLOCK memory;
END behave ;
-B25-
APPENDIX C
SIMULATION OF PROGRAM EXECUTION (1)
Results of Program Execution
(buses, MDR, MAR, SP, PC, PSW, processor's state,
instructions, fetch & execution cycles)
0 XXXX XXXX XXXX xxxx xxxx xxxx error idle -2 -2 xxxxx
RESET <- ' 1'for more than 3 clock cycles
850 XXXX XXXX XXXX xxxx xxxx XXXX error inte 1 1 10000
.900 XXXX 0000 XXXX xxxx xxxx xxxx error inte 1 1 10000
950 XXXX 0000 000 xxxx xxxx xxxx error inte 1 1 10000
1060 xxxx 0000 000 0200 xxxx xxxx error inte 1 1 10000
inte rrupt vector is fetched from memory
1100 XXXX 0000 XXXX 0200 0200 xxxx error inte 1 1 10000
1105 XXXX 0000 XXXX xxxx 0200 xxxx error inte 1 1 10000
1300 0200 0200 xxxx xxxx 0200 xxxx error inte 1 1 10000
1350 0200 0200 xxxx xxxx 0200 xxxx error fete 1 1 10000
1400 0200 0200 100 xxxx 0200 xxxx error fete 2 1 10000
1510 0200 0200 100 6900 0200 xxxx error fete 2 1 10000
1550 0200 0200 xxxx 6900 6900 xxxx error fete 2 1 10000
1555 0200 0200 xxxx xxxx 6900 xxxx error fete 2 1 10000
inte rrupt service routine starts executed
1600 0202 0200 xxxx xxxx 6900 xxxx stpsw fete 31'
10000
1650 0202 0200 xxxx xxxx 6900 xxxx stpsw exec 3 1 10000
1700 0202 0200 xxxx xxxx 6900 xxxx stpsw exec 3 2 10000
1750 0202 0202 xxxx xxxx 6900 xxxx stpsw fete 1 2 10000
1800 0202 0202 101 xxxx 6900 xxxx stpsw fete 2 2 10000
1910 0202 0202 101 A18F 6900 xxxx stpsw fete 2 2 10000
1950 0202 0202 xxxx A18F A18F xxxx stpsw fete 2 2 10000
1955 0202 0202 xxxx xxxx A18F xxxx stpsw fete 2 2 10000
2000 0204 0202 xxxx xxxx A18F xxxx andd fete 3 2 10000
2050 0204 0202 xxxx xxxx A18F xxxx andd exec 3 1 10000
2100 0204 0202 xxxx xxxx A18F xxxx andd exec 3 2 10100
2150 0204 0202 xxxx xxxx A18F xxxx andd exec 3 3 10100
2200 0204 0204 xxxx xxxx A18F xxxx andd fete 1 3 10100
2250 0204 0204 102 xxxx A18F xxxx andd fete 2 3 10100
2360 0204 0204 102 4900 A18F xxxx andd fete 2 3 10100
2400 0204 0204 xxxx 4900 4900 xxxx andd fete 2 3 10100
2405 0204 0204 xxxx XXXX 4900 xxxx andd fete 2 3 10100
2450 0206 0204 xxxx XXXX 4900 xxxx ldpsw fete 3 3 10100
2500 0206 0204 xxxx xxxx 4900 xxxx ldpsw exec 3 1 10100
2550 0206 0204 xxxx xxxx 4900 xxxx ldpsw exec 3 2 ooooo
clear the Interrupt Disable Flag
2600 0206 0206 xxxx xxxx 4900 xxxx ldpsw fete 1 2 ooooo
2650 0206 0206 103 xxxx 4900 xxxx ldpsw fete 2 2 ooooo
2760 0206 0206 103 9103 4900 xxxx ldpsw fete 2 2 ooooo
2800 0206 0206 xxxx 9103 9103 xxxx ldpsw fete 2 2 ooooo
2805 0206 0206 xxxx XXXX 9103 xxxx ldpsw fete 2 2 ooooo
2850 0208 0206 xxxx xxxx 9103 xxxx ldhi fete 3 2 ooooo
2900 0208 0206 xxxx xxxx 9103 xxxx ldhi exec 3 1 ooooo
2950 0208 0206 xxxx xxxx 9103 xxxx ldhi exec 3 2 ooooo
3000 0208 0208 xxxx xxxx 9103 xxxx ldhi fete 1 2 ooooo
3050 0208 0208 104 xxxx 9103 xxxx ldhi fete 2 2 ooooo
3160 0208 0208 104 B100 9103 xxxx ldhi fete 2 2 ooooo
3200 0208 0208 xxxx B100 B100 xxxx ldhi fete 2 2 ooooo
3205 0208 0208 xxxx xxxx B100 xxxx ldhi fete 2 2 ooooo
3250 020A 0208 xxxx xxxx B100 xxxx ldlo fete 3 2 ooooo
3300 020A 0208 xxxx xxxx B100 xxxx ldlo exec 3 1 ooooo
TIME VPC AMAR ~address_busAMDR
Adata bus
'SP ^instruction Af_cyc APSW
Aproc state Aex eye
-Cl-
3350 020A 0208 xxxx XXXX B100 XXXX ldlo exec 3 2 ooooo
3400 020A 02 0A xxxx xxxx B100 XXXX ldlo fete 1 2 ooooo
3450 020A 020A 105 xxxx B100 XXXX ldlo fete 2 2 ooooo
3560 020A 020A 105 7900 B100 XXXX ldlo fete 2 2 ooooo3600 020A 020A XXXX 7900 7900 XXXX ldlo fete 2 2 ooooo3605 02 0A 020A XXXX XXXX 7900 XXXX ldlo fete 2 2 ooooo3650 020C 020A XXXX XXXX 7900 xxxx jmp fete 3 2 ooooo3700 020C 020A XXXX XXXX 7900 xxxx jmp exec 3 1 ooooo3750 020C 020A xxxx XXXX 7900 xxxx jmp exec 3 2 ooooo3800 0300 0300 xxxx xxxx 7900 xxxx jmp exec 3 3 ooooo3850 0300 0300 xxxx xxxx 7900 xxxx jmp fete 1 3 ooooo3900 0300 0300 180 xxxx 7900 xxxx jmp fete 2 3 ooooo4010 0300 0300 180 9506 7900 xxxx jmp fete 2 3 ooooo4050 0300 0300 xxxx 9506 9506 xxxx jmp fete 2 3 ooooo4055 0300 0300 xxxx XXXX 9506 xxxx jmp fete 2 3 ooooo
jump toprogram'
s code address
4100 0302 0300 xxxx XXXX 9506 xxxx ldhi fete 3 3 ooooo
4150 0302 0300 xxxx XXXX 9506 xxxx ldhi exec 3 1 ooooo4200 0302 0300 xxxx XXXX 9506 xxxx ldhi exec 3 2 ooooo
4250 0302 0302 xxxx XXXX 9506 xxxx ldhi fete 1 2 ooooo
4300 0302 0302 181 xxxx 9506 xxxx ldhi fete 2 2 ooooo
4410 0302 0302 181 B520 9506 xxxx ldhi fete 2 2 ooooo
4450 0302 0302 xxxx B520 B520 xxxx ldhi fete 2 2 ooooo
4455 0302 0302 xxxx XXXX B520 xxxx ldhi fete 2 2 ooooo
4500 0304 0302 xxxx XXXX B520 xxxx ldlo fete 3 2 ooooo
4550 0304 0302 xxxx XXXX B520 xxxx ldlo exec 3 1 ooooo
4600 0304 0302 xxxx XXXX B520 xxxx ldlo exec 3 2 ooooo
4650 0304 0304 xxxx xxxx B520 xxxx ldlo fete 1 2 ooooo
4700 0304 0304 182 xxxx B520 xxxx ldlo fete 2 2 OoCOO
4810 0304 0304 182 BD00 B520 xxxx ldlo fete 2 2 ooooo
4850 0304 0304 XXXX BD00 BD00 xxxx ldlo fete 2 2 ooooo
4855 0304 0304 xxxx XXXX BD00 xxxx ldlo fete 2 2 ooooo
4900 0306 0304 xxxx XXXX BD00 xxxx ldsp fete 3 2 ooooo
4950 0306 0304 xxxx xxxx BD00 xxxx ldsp exec 3 1 ooooo
5000 0306 0304 xxxx xxxx BD00 xxxx ldsp exec 3 2 ooooo
5050 0306 0304 xxxx xxxx BD00 0620 ldsp exec 3 3 ooooo
load Stack Pointer
5100 0306 0306 xxxx xxxx BD00 0620 ldsp fete 1 3 ooooo
5150 0306 0306 183 xxxx BD00 0620 ldsp fete 2 3 ooooo
5260 0306 0306 183 9400 BD00 0620 ldsp fete 2 3 ooooo
5300 0306 0306 XXXX 9400 9400 0620 ldsp fete 2 3 ooooo
5305 0306 0306 XXXX XXXX 9400 0620 ldsp fete 2 3 ooooo
5350 0308 0306 xxxx xxxx 9400 0620 ldhi fete 3 3 ooooo
5400 0308 0306 xxxx xxxx 9400 0620 ldhi exec 3 1 ooooo
5450 0308 0306 xxxx xxxx 9400 0620 ldhi exec 3 2 ooooo
5500 0308 0308 xxxx xxxx 9400 0620 ldhi fete 1 2 ooooo
5550 0308 0308 184 xxxx 9400 0620 ldhi fete 2 2 ooooo
5660 0308 0308 184 B4FF 9400 0620 ldhi fete 2 2 ooooo
5700 0308 0308 XXXX B4FF B4FF 0620 ldhi fete 2 2 ooooo
5705 0308 0308 XXXX XXXX B4FF 0620 ldhi fete 2 2 ooooo
5750 030A 0308 xxxx XXXX B4FF 0620 ldlo fete 3 2 ooooo
5800 030A 0308 xxxx XXXX B4FF 0620 ldlo exec 3 1 ooooo
5850 030A 0308 xxxx XXXX B4FF 0620 ldlo exec 3 2 ooooo
5900 030A 030A xxxx XXXX B4FF 0620 ldlo fete 1 2 ooooo
issuina of external interrupt (at 6000ns )
5950 030A 030A 185 xxxx B4FF 0620 ldlo fete 2 2 ooooo
6060 030A 030A 185 0520 B4FF 0620 ldlo fete 2 2 ooooo
6100 030A 030A xxxx 0520 0520 0620 ldlo fete 2 2 ooooo
6105 030A 030A xxxx XXXX 0520 0620 ldlo fete 2 2 ooooo
6150 030C 030A xxxx XXXX 0520 0620 adc fete 3 2 ooooo
6200 030C 030A xxxx XXXX 0520 0620 adc exec 3 1 ooooo
6250 030C 030A xxxx xxxx 0520 0620 adc exec 3 2 ooooo
6300 030C 030A xxxx xxxx 0520 0620 adc exec 3 3 ooooo
6350 030C 0620 xxxx xxxx 0520 0620 adc inte 1 1 ooooo
. -reindan i t ion of the interrupt (after the execution of the inst ructio
TIME "PC "MAR "address_bus"MDR
Adata bus
'SP "instruction "f_cyc "PSW
"proc_state "ex_cyc
-C2-
6400 030C 0620 XXXX xxxx 030C 061E adc inte 1 1 ooooo
6450 030C 0620 310 030C 030C 061E adc inte 1 1 ooooo
6600 030C 0620 XXXX xxxx 030C 061E adc inte 1 1 ooooo
6650 030C 061E XXXX xxxx 030C 061E adc inte 1 1 ooooo
6700 030C 061E 30F 0000 0000 061C adc inte 1 1 10000
6850 030C 061E XXXX xxxx 0000 061C adc inte 1 1 10000
6900 030C 061E 30F 0000 0000 061C adc inte 1 1 10000
7050 030C 061E XXXX xxxx 0000 061C adc inte 1 1 100007100 030C 0002 XXXX xxxx 0000 061C adc inte 1 1 10000
7150 030C 0002 001 xxxx 0000 061C adc inte 1 1 100007260 030C 0002 001 0220 0000 061C adc inte 1 1 100007300 030C 0002 XXXX 0220 0220 061C adc inte 1 1 10000
7305 030C 0002 XXXX xxxx 0220 061C adc inte 1 1 10000
7500 0220 0220 xxxx xxxx 0220 061C adc inte 1 1 10000
7550 0220 0220 xxxx xxxx 0220 061C adc fete 1 1 10000
7600 0220 0220 110 xxxx 0220 061C adc fete 2 1 10000
7710 0220 0220 110 C900 0220 061C adc fete 2 1 10000
7750 0220 0220 xxxx C900 C900 061C adc fete 2 1 10000
7755 0220 0220 xxxx xxxx C900 061C adc fete 2 1 10000
7800 0222 0220 xxxx xxxx C900 061C push fete 3 1 10000
7850 0222 0220 xxxx xxxx C900 061C push exec 3 1 10000
7900 0222 0220 xxxx xxxx C900 061C push exec 3 2 10000
7950 0222 061C xxxx xxxx 0300 061C push exec 3 3 10000
8000 0222 061C 30E 0300 0300 061A push exec 3 4 10000
8150 0222 061C xxxx xxxx 0300 061A push exec 3 4 10000
8200 0222 0222 xxxx xxxx 0300 061A push fete 1 4 10000
8250 0222 0222 111 xxxx 0300 061A push fete 2 4 10000
8360 0222 0222 111 6900 0300 061A push fete 2 4 10000
8400 0222 0222 xxxx 6900 r.o^r) 0 61A push fete 2 4 10000
8405 0222 0222 xxxx xxxx 061A push fete 2 4 10000
8450 0224 0222 xxxx xxxx 6900 0 61A stpsw fete 3 4 10000
8500 0224 0222 xxxx xxxx 6900 0 61A stpsw exec 3 1 10000
8550 0224 0222 xxxx xxxx 6900 061A stpsw exec 3 2 10000
8600 0224 0224 xxxx xxxx 6900 061A stpsw fete 1 2 10000
8650 0224 0224 112 xxxx 6900 061A stpsw fete 2 2 10000
8760 0224 0224 112 C187 6900 061A stpsw fete 2 2 10000
8800 0224 0224 xxxx C187 C187 061A stpsw fete 2 2 10000
8805 0224 0224 xxxx xxxx C187 061A stpsw fete 2 2 10000
8850 0226 0224 xxxx xxxx C187 061A orr fete 3 2 10000
8900 0226 0224 xxxx xxxx C187 061A orr exec 3 1 10000
8950 0226 0224 xxxx xxxx C187 061A orr exec 3 2 10000
9000 0226 0224 xxxx xxxx C187 061A orr exec 3 3 10000
9050 0226 0226 xxxx xxxx C187 061A orr fete 1 3 10000
9100 0226 0226 113 xxxx C187 0 61A orr fete 2 3 10000
9210 0226 0226 113 4900 C187 0 61A orr fete 2 3 10000
9250 0226 0226 xxxx 4900 4900 061A orr fete 2 3 10000
9255 0226 0226 xxxx xxxx 4900 061A orr fete 2 3 10000
9300 0228 0226 xxxx xxxx 4900 061A ldpsw fete 3 3 10000
9350 0228 0226 xxxx xxxx 4900 061A ldpsw exec 3 1 10000
9400 0228 0226 xxxx xxxx 4900 061A ldpsw exec 3 2 10111
9450 0228 0228 xxxx xxxx 4900 061A ldpsw fete 1 2 10111
9500 0228 0228 114 xxxx 4900 061A ldpsw fete 2 2 10111
9610 0228 0228 114 E900 4900 061A ldpsw fete 2 2 10111
9650 0228 0228 xxxx E900 E900 061A ldpsw fete 2 2 10111
9655 0228 0228 xxxx XXXX E900 061A ldpsw fete 2 2 10111
9700 022A 0228 xxxx xxxx E900 061A pop fete 3 2 10111
9750 022A 0228 xxxx xxxx E900 061C pop exec 3 1 10111
9800 022A 061C xxxx xxxx E900 061C pop exec 3 2 10111
9850 022A 061C 30E xxxx E900 061C pop exec 3 3 10111
9960 022A 061C 30E 0300 E900 061C pop exec 3 3 10111
10000 022A 061C xxxx 0300 0300 061C pop exec 3 3 10111
10005 022A 061C xxxx xxxx 0300 061C pop exec 3 3 10111
10050 022A 061C xxxx xxxx 0300 061C pop exec 3 4 10111
10100 022A 061C xxxx xxxx 0300 061C pop exec 3 5 10111
TIME "PC "MAR "address_bus"MDR
"data bus
"SP "instruction "f_cyc "PSW
"proc_state "ex eye
-C3-
10150 022A 061C XXXX XXXX 0300 061C pop exec 3 6 1011110200 022A 022A XXXX xxxx 0300 061C pop fete 1 6 1011110250 022A 022A 115 xxxx 0300 061C Pop fete 2 6 1011110360 022A 022A 115 E800 0300 061C pop fete 2 6 1011110400 022A 022A XXXX E800 E800 061C pop fete 2 6 1011110405 022A 022A XXXX XXXX E800 061C pop fete 2 6 1011110450 022C 022A XXXX XXXX E800 061C pop fete 3 6 1011110500 022C 022A XXXX xxxx E800 061E pop exec 3 1 1011110550 022C 061E XXXX xxxx E800 061E pop exec 3 2 1011110600 022C 061E 30F xxxx E800 061E Pop exec 3 3 1011110710 022C 061E 30F 0000 E800 061E pop exec 3 3 1011110750 022C 061E XXXX 0000 0000 061E pop exec 3 3 1011110755 022C 061E XXXX xxxx 0000 061E pop exec 3 3 1011110800 022C 061E XXXX xxxx 0000 061E pop exec 3 4 1011110850 022C 061E xxxx xxxx 0000 061E pop exec 3 5 1011110900 022C 061E xxxx xxxx 0000 061E pop exec 3 6 ooooo10950 022C 022C xxxx xxxx 0000 061E pop fete 1 6 ooooo11000 022C 022C 116 xxxx 0000 061E pop fete 2 6 ooooo11110 022C 022C 116 A800 0000 061E pop fete 2 6 ooooo11150 022C 022C XXXX A800 A800 061E pop fete 2 6 ooooo11155 022C 022C xxxx xxxx A800 061E pop fete 2 6 ooooo11200 022E 022C xxxx xxxx A800 061E ret fete 3 6 ooooo11250 022E 022C xxxx xxxx A800 0620 ret exec 3 1 ooooo11300 022E 0620 xxxx xxxx A800 0620 ret exec 3 2 ooooo11350 022E 0620 310 xxxx A800 0620 ret exec 3 3 ooooo11460 022E 0620 310 030C A800 0620 ret exec 3 3 ooooo11500 022E 0620 XXXX 030C 030C 0620 ret exec 3 3 ooooo
11505 022E 0620 xxxx xxxx 030C 0620 ret exec 3 3 ooooo
11550 022E 0620 xxxx xxxx 030C 0620 ret exec 3 4 ooooo
11600 022E 0620 xxxx xxxx 030C 0620 ret exec 3 5 ooooo
11650 022E 0620 xxxx xxxx 030C 0620 ret exec 3 6 ooooo
11700 030C 0620 xxxx xxxx 030C 0620 ret exec 3 7 ooooo
return from interrupt service rout ine
11750 030C 030C xxxx XXXX 030C 0620 ret fete 1 7 ooooo
11800 030C 030C 186 xxxx 030C 0620 ret fete 2 7 ooooo
11910 030C 030C 186 0624 030C 0620 ret fete 2 7 ooooo
11950 030C 030C XXXX 0624 0624 0620 ret fete 2 7 ooooo
11955 030C 030C xxxx XXXX 0624 0620 ret fete 2 7 ooooo
12000 030E 030C xxxx XXXX 0624 0620 adc fete 3 7 ooooo
12050 030E 030C xxxx XXXX 0624 0620 adc exec 3 1 ooooo
12100 030E 030C xxxx xxxx 0624 0620 adc exec 3 2 ooooo
12150 030E 030C xxxx xxxx 0624 0620 adc exec 3 3 ooooo
12200 030E 030E xxxx xxxx 0624 0620 adc fete 1 3 ooooo
12250 030E 030E 187 xxxx 0624 0620 adc fete 2 3 ooooo
12360 030E 030E 187 9103 0624 0620 adc fete 2 3 ooooo
12400 030E 030E XXXX 9103 9103 0620 adc fete 2 3 ooooo
12405 030E 030E XXXX XXXX 9103 0620 adc fete 2 3 ooooo
12450 0310 030E xxxx xxxx 9103 0620 ldhi fete 3 3 ooooo
12500 0310 030E xxxx xxxx 9103 0620 ldhi exec 3 1 ooooo
12550 0310 030E xxxx xxxx 9103 0620 ldhi exec 3 2 ooooo
12600 0310 0310 xxxx xxxx 9103 0620 ldhi fete 1 2 ooooo
12650 0310 0310 188 xxxx 9103 0620 ldhi fete 2 2 ooooo
12760 0310 0310 188 B120 9103 0620 ldhi fete 2 2 ooooo
12800 0310 0310 xxxx B120 B120 0620 ldhi fete 2 2 ooooo
12805 0310 0310 XXXX xxxx B120 0620 ldhi fete 2 2 ooooo
12850 0312 0310 XXXX XXXX B120 0620 ldlo fete 3 2 ooooo
12900 0312 0310 xxxx xxxx B120 0620 ldlo exec 3 1 ooooo
12950 0312 0310 xxxx xxxx B120 0620 ldlo exec 3 2 ooooo
13000 0312 0312 xxxx xxxx B120 0620 ldlo fete 1 2 ooooo
13050 0312 0312 189 xxxx B120 0620 ldlo fete 2 2 ooooo
13160 0312 0312 189 8900 B120 0620 ldlo fete 2 2 ooooo
13200 0312 0312 XXXX 8900 8900 0620 ldlo fete 2 2 ooooo
13205 0312 0312 XXXX XXXX 8900 0620 ldlo fete 2 2 ooooo
13250 0314 0312 XXXX XXXX 8900 0620 call fete 3 2 ooooo
TIME "PC "MAR ~address_bus"MDR
"data bus
'SP "instruction "f_cyc "PSW
"proc_state "ex_cyc
-C4-
13300 0314 0312 XXXX xxxx 8900 0620 call exec 3 1 ooooo13350 0314 0620 XXXX xxxx 0314 0620 call exec 3 2 ooooo13400 0314 0620 310 0314 0314 0620 call exec 3 3 ooooo13550 0314 0620 XXXX XXXX 0314 0620 call exec 3 3 ooooo13600 0320 0620 XXXX xxxx 0314 061E call exec 3 4 ooooo13650 0320 0320 XXXX xxxx 0314 061E call fete 1 4 ooooo13700 0320 0320 190 xxxx 0314 061E call fete 2 4 ooooo13810 0320 0320 190 9204 0314 061E call fete 2 4 ooooo13850 0320 0320 XXXX 9204 9204 061E call fete 2 4 ooooo13855 0320 0320 XXXX XXXX 9204 061E call fete 2 4 ooooo13900 0322 0320 XXXX XXXX 9204 061E ldhi fete 3 4 ooooo13950 0322 0320 xxxx XXXX 9204 061E ldhi exec 3 1 ooooo14000 0322 0320 xxxx XXXX 9204 061E ldhi exec 3 2 ooooo14050 0322 0322 xxxx xxxx 9204 061E ldhi fete 1 2 ooooo14100 0322 0322 191 xxxx 9204 061E ldhi fete 2 2 ooooo14210 0322 0322 191 B2B0 9204 061E ldhi fete 2 2 ooooo14250 0322 0322 XXXX B2B0 B2B0 061E ldhi fete 2 2 ooooo14255 0322 0322 xxxx XXXX B2B0 061E ldhi fete 2 2 ooooo14300 0324 0322 xxxx XXXX B2B0 061E ldlo fete 3 2 ooooo14350 0324 0322 xxxx XXXX B2B0 061E ldlo exec 3 1 ooooo14400 0324 0322 xxxx XXXX B2B0 061E ldlo exec 3 2 ooooo14450 0324 0324 xxxx XXXX B2B0 061E ldlo fete 1 2 ooooo14500 0324 0324 192 xxxx B2B0 061E ldlo fete 2 2 ooooo14610 0324 0324 192 0683 B2B0 061E ldlo fete 2 2 ooooo14650 0324 0324 XXXX 0683 0683 061E ldlo fete 2 2 ooooo14655 0324 0324 XXXX XXXX 0683 061E ldlo fete 2 2 ooooo14700 0326 0324 xxxx XXXX 0683 061E adc fete 3 2 ooooo14750 0326 0324 xxxx XXXX 0683 061E adc exec 3 1 ooooo14800 0326 0324 xxxx XXXX 0683 061E adc exec 3 2 ooooo
14850 0326 0324 xxxx xxxx 0683 061E adc exec 3 3 ooooo14900 0326 0326 xxxx xxxx 0683 061E adc fete 1 3 ooooo
14950 0326 0326 193 xxxx 0683 061E adc fete 2 3 ooooo
15060 0326 0326 193 CE00 0683 061E adc fete 2 3 ooooo
15100 0326 0326 XXXX CE00 CE00 061E adc fete 2 3 ooooo
15105 0326 0326 xxxx xxxx CE00 061E adc fete 2 3 ooooo
15150 0328 0326 xxxx xxxx CE00 061E push fete 3 3 ooooo
15200 0328 0326 xxxx xxxx CE00 061E push exec 3 1 ooooo
15250 0328 0326 xxxx xxxx CE00 061E push exec 3 2 ooooo
15300 0328 061E xxxx xxxx 0201 061E push exec 3 3 ooooo
15350 0328 061E 30F 0201 0201 061C push exec 3 4 ooooo
15500 0328 061E xxxx xxxx 0201 061C push exec 3 4 ooooo
15550 0328 0328 xxxx xxxx 0201 061C push fete 1 4 ooooo
15600 0328 0328 194 xxxx 0201 061C push fete 2 4 ooooo
15710 0328 0328 194 EC00 0201 061C push fete 2 4 ooooo
15750 0328 0328 XXXX EC00 EC00 061C push fete 2 4 ooooo
15755 0328 0328 xxxx xxxx EC00 061C push fete 2 4 ooooo
15800 032A 0328 xxxx xxxx EC00 061C pop fete 3 4 ooooo
15850 032A 0328 xxxx xxxx EC00 061E pop exec 3 1 ooooo
15900 032A 061E xxxx xxxx EC00 061E pop exec 3 2 ooooo
15950 032A 061E 30F xxxx EC00 061E pop exec 3 3 ooooo
16060 032A 061E 30F 0201 EC00 061E pop exec 3 3 ooooo
16100 032A 061E XXXX 0201 0201 061E pop exec 3 3 ooooo
16105 032A 061E XXXX xxxx 0201 061E pop exec 3 3 ooooo
16150 032A 061E XXXX xxxx 0201 061E pop exec 3 4 ooooo
16200 032A 061E xxxx xxxx 0201 061E pop exec 3 5 ooooo
16250 032A 061E xxxx xxxx 0201 061E pop exec 3 6 ooooo
16300 032A 032A xxxx xxxx 0201 061E pop fete 1 6 ooooo
16350 032A 032A 195 xxxx 0201 061E pop fete 2 6 ooooo
16460 032A 032A 195 DB00 0201 061E pop fete 2 6 ooooo
16500 032A 032A XXXX DB00 DB00 061E pop fete 2 6 ooooo
16505 032A 032A XXXX XXXX DB00 061E pop fete 2 6 ooooo
16550 032C 032A XXXX xxxx DB00 061E stsp fete 3 6 ooooo
16600 032C 032A XXXX xxxx DB00 061E stsp exec 3 1 ooooo
16650 032C 032A xxxx xxxx DB00 061E stsp exec 3 2 ooooo
TIME "PC "MAR "address_bus"MDR
"data bus
'SP "instruction "f_cyc "PSW
"proc_state "ex eye
-C5-
16700 032C 032C xxxx XXXX DB00 061E stsp fete 1 2 ooooo16750 032C 032C 196 XXXX DB00 061E stsp fete 2 2 ooooo16860 032C 032C 196 3B06 DB00 061E stsp fete 2 2 ooooo16900 032C 032C xxxx 3B06 3B06 061E stsp fete 2 2 ooooo16905 032C 032C XXXX XXXX 3B06 061E stsp fete 2 2 ooooo16950 032E 032C XXXX XXXX 3B06 061E StW fete 3 2 ooooo17000 032E 032C XXXX XXXX 3B06 061E StW exec 3 1 ooooo17050 032E 032C xxxx XXXX 3B0 6 061E stw exec 3 2 ooooo17100 032E 0201 xxxx XXXX 3B06 061E StW exec 3 3 ooooo17150 032E 0201 xxxx XXXX 3B06 061E StW exec 3 4 ooooo17200 032E 0201 xxxx xxxx 061E 061E StW exec 3 5 ooooo17250 032E 0201 100 061E 061E 061E stw exec 3 6 ooooo17400 032E 0201 xxxx XXXX 061E 061E StW exec 3 6 ooooo17450 032E 032E xxxx xxxx 061E 061E stw fete 1 6 ooooo17500 032E 032E 197 xxxx 061E 061E stw fete 2 6 ooooo17610 032E 032E 197 1A0 6 061E 061E StW fete 2 6 ooooo17650 032E 032E XXXX 1A06 1A06 061E stw fete 2 6 ooooo17655 032E 032E xxxx XXXX 1A06 061E stw fete 2 6 ooooo17700 0330 032E xxxx XXXX 1A0 6 061E ldw fete 3 6 ooooo17750 0330 032E xxxx XXXX 1A06 061E ldw exec 3 1 ooooo17800 0330 032E xxxx xxxx 1A0 6 061E ldw exec 3 2 ooooo17850 0330 0201 xxxx xxxx 1A0 6 061E ldw exec 3 3 ooooo17900 0330 0201 100 xxxx 1A0 6 061E ldw exec 3 4 ooooo
18010 0330 0201 100 061E 1A0 6 061E ldw exec 3 4 ooooo
18050 0330 0201 xxxx 061E 061E 061E ldw exec 3 4 ooooo
18055 0330 0201 xxxx XXXX 061E 061E ldw exec 3 4 ooooo
18100 0330 0201 xxxx XXXX 061E 061E ldw exec 3 5 ooooo
18150 0330 0201 xxxx XXXX 061E 061E ldw exec 3 6 ooooo
18200 0330 0201 xxxx xxxx 061E 061E ldw exec 3 7. ooooo
18250 0330 0330 xxxx xxxx 061E 061E ldw fete 1 7 ooooo
18300 0330 0330 198 xxxx 061E 061E ldw fete 2 7 ooooo
18410 0330 0330 198 1282 061E 061E ldw fete 2 7 ooooo
18450 0330 0330 xxxx 1282 1282 061E ldw fete 2 7 ooooo
18455 0330 0330 xxxx XXXX 1282 061E ldw fete 2 7 ooooo
18500 0332 0330 xxxx xxxx 1282 061E shll fete 3 7 ooooo
18550 0332 0330 xxxx xxxx 1282 061E shll exec 3 1 ooooo
18600 0332 0330 xxxx xxxx 1282 061E shll exec 3 2 ooooo
18650 0332 0330 xxxx xxxx 1282 061E shll exec 3 3 ooooo
18700 0332 0332 xxxx xxxx 1282 061E shll fete 1 3 ooooo
18750 0332 0332 199 xxxx 1282 061E shll fete 2 3 ooooo
18860 0332 0332 199 3283 1282 061E shll fete 2 3 ooooo
18900 0332 0332 XXXX 3283 3283 061E shll fete 2 3 ooooo
18905 0332 0332 xxxx XXXX 3283 061E shll fete 2 3 ooooo
18950 0334 0332 xxxx XXXX 3283 061E shrl fete 3 3 ooooo
19000 0334 0332 xxxx XXXX 3283 061E shrl exec 3 1 ooooo
19050 0334 0332 xxxx XXXX 3283 061E shrl exec 3 2 ooooo
19100 0334 0332 xxxx XXXX 3283 061E shrl exec 3 3 ooooo
19150 0334 0334 xxxx xxxx 3283 061E shrl fete 1 3 ooooo
19200 0334 0334 19A xxxx 3283 061E shrl fete 2 3 ooooo
19310 0334 0334 19A 6298 3283 061E shrl fete 2 3 ooooo
19350 0334 0334 xxxx 6298 6298 061E shrl fete 2 3 ooooo
19355 0334 0334 xxxx XXXX 6298 061E shrl fete 2 3 ooooo
19400 0336 0334 xxxx XXXX 6298 061E stb fete 3 3 ooooo
19450 0336 0334 xxxx XXXX 6298 061E stb exec 3 1 ooooo
19500 0336 0334 xxxx XXXX 6298 061E Stb exec 3 2 ooooo
19550 0336 061E xxxx XXXX 6298 061E stb exec 3 3 ooooo
19600 0336 061E xxxx xxxx 6298 061E stb exec 3 4 ooooo
19650 0336 061E xxxx xxxx 030F 061E stb exec 3 5 ooooo
19700 0336 061E 30F 030F 030F 061E stb exec 3 6 ooooo
19850 0336 061E xxxx XXXX 030F 061E stb exec 3 6 ooooo
19900 0336 0336 xxxx XXXX 030F 061E stb fete 1 6 ooooo
19950 0336 0336 19B xxxx 030F 061E stb fete 2 6 ooooo
20060 0336 0336 19B 4318 030F 061E stb fete 2 6 ooooo
20100 0336 0336 XXXX 4318 4318 061E stb fete 2 6 ooooo
TIME "PC "MAR "address_bus"MDR
"data bus
SSP "instruction "f_cyc "PSW
"proc_state "ex_cyc
-C6-
20105 0336 0336 XXXX XXXX 4318 061E stb fete 2 6 ooooo
20150 0338 0336 XXXX xxxx 4318 061E ldb fete 3 6 ooooo
20200 0338 0336 xxxx xxxx 4318 061E ldb exec 3 1 ooooo
20250 0338 0336 xxxx xxxx 4318 061E ldb exec 3 2 ooooo
20300 0338 061E xxxx xxxx 4318 061E ldb exec 3 3 ooooo
20350 0338 061E 30F xxxx 4318 061E ldb exec 3 4 ooooo20460 0338 0 61E 30F 0301 4318 061E ldb exec 3 4 ooooo20500 0338 061E XXXX 0301 0301 061E ldb exec 3 4 ooooo20505 0338 061E XXXX xxxx 0301 061E ldb exec 3 4 ooooo20550 0338 061E xxxx xxxx 0301 061E ldb exec 3 5 ooooo20600 0338 061E xxxx xxxx 0301 061E ldb exec 3 6 ooooo20650 0338 061E xxxx xxxx 0301 061E ldb exec 3 7 ooooo20700 0338 0338 xxxx xxxx 0301 061E ldb fete 1 7 ooooo20750 0338 0338 19C xxxx 0301 061E ldb fete 2 7 ooooo20860 0338 0338 19C 1388 0301 061E ldb fete 2 7 ooooo20900 0338 0338 xxxx 1388 1388 061E ldb fete 2 7 ooooo
20905 0338 0338 xxxx xxxx 1388 061E ldb fete 2 7 ooooo
20950 033A 0338 xxxx xxxx 1388 061E shll fete 3 7 ooooo
21000 033A 0338 xxxx xxxx 1388 061E shll exec 3 1 ooooo
21050 033A 0338 xxxx xxxx 1388 061E shll exec 3 2 ooooo
21100 033A 0338 xxxx xxxx 1388 061E shll exec 3 3 ooooo
21150 033A 033A xxxx xxxx 1388 061E shll fete 1 3 ooooo
21200 033A 033A 19D xxxx 1388 061E shll fete 2 3 ooooo
21310 033A 033A 19D A800 1388 061E shll fete 2 3 ooooo
21350 033A 033A XXXX A800 A800 061E shll fete 2 3 ooooo
21355 033A 033A xxxx xxxx A800 061E shll fete 2 3 ooooo
21400 033C 033A xxxx xxxx A800 061E ret fete 3 3 ooooo
21450 033C 033A xxxx xxxx A800 0620 ret exec 3 1 ooooo
21500 033C 0620 xxxx xxxx A800 0620 ret exec 3 2 ooooo
21550 033C 0620 310 xxxx A800 0620 ret exec 3 3 ooooo
21660 033C 0620 310 0314 A800 0620 ret exec 3 3 ooooo
21700 033C 0620 xxxx 0314 0314 0620 ret exec 3 3 ooooo
21705 033C 0620 xxxx XXXX 0314 0620 ret exec 3 3 ooooo
21750 033C 0620 xxxx xxxx 0314 0620 ret exec 3 4 ooooo
21800 033C 0620 xxxx xxxx 0314 0620 ret exec 3 5 ooooo
21850 033C 0620 xxxx xxxx 0314 0620 ret exec 3 6 ooooo
21900 0314 0620 xxxx xxxx 0314 0620 ret exec 3 7 ooooo
21950 0314 0314 xxxx xxxx 0 1 1 4 0620 ret fete 1 7 ooooo
22000 0314 0314 18A xxxx Oil 4 0620 ret fete 2 7 ooooo
22110 0314 0314 18A 2800 0314 0620 ret fete 2 7 ooooo
22150 0314 0314 xxxx 2800 2800 0620 ret fete 2 7 ooooo
22155 0314 0314 xxxx xxxx 2800 0620 ret fete 2 7 ooooo
22200 0316 0314 xxxx xxxx 2800 0620 hit fete 3 7 ooooo
22250 0316 0314 xxxx xxxx 2800 0620 hit idle 3 1 ooooo
TIME "PC "MAR "address bus"MDR "SP "instruction "f eye "PSW
"data bus "proc state "ex eye
-C7-
APPENDIX D
SIMULATION OF PROGRAM EXECUTION (2)
Results of Program Execution
(registers of register file)
0 -2147 -2147 -2147 -2147 -2147 -2147 -2147 -2147
850 0 0 0 0 0 0 0 0
900 0 0 0 0 0 0 0 0
950 0 0 0 0 0 0 0 0
1060 0 0 0 0 0 0 0 0
1100 0 0 0 0 0 0 0 0
1105 0 0 0 0 0 0 0 0
1300 0 0 0 0 0 0 0 0
1350 0 0 0 0 0 0 0 0
1400 0 0 0 0 0 0 0 0
1510 0 0 0 0 0 0 0 0
1550 0 0 0 0 0 0 0 0
1555 0 0 0 0 0 0 0 0
1600 0 0 0 0 0 0 0 0
1650 0'
0 0 0 0 0 0 0
1700 0 16 0 0 0 0 0 0
1750 0 16 0 0 0 0 0 0
1800 0 16 0 0 0 0 0 0
1910 0 16 0 0 0 0 0 0
1950 0 16 0 0 0 0 0 0
1955 0 16 0 0 0 0 0 0
2000 0 16 0 0 0 0 0 0
2050 0 16 0 0 0 0 0 0
2100 0 16 0 0 0 0 0 0
2150 0 0 0 0 0 0 0 0
2200 0 0 0 0 0 0 0 0
2250 0 0 0 0 0 0 0 0
2360 0 0 0 0 0 0 0 0
2400 0 0 0 0 0 0 0 0
2405 0 0 0 0 0 0 0 0
2450 0 0 0 0 0 0 0 0
2500 0 0 0 0 0 0 0 0
2550 0 0 0 0 0 0 0 0
2600 0 0 0 0 0 0 0 0
2650 0 0 0 0 0 0 0 0
2760
2800
2805
2850
2900
2950
3000
3050
3160
3200
3205
3250
3300
3350
3400
3450
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
768
768
768
768
768
768
768
768
768
768
768
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
TIME "registers (0) "registers (3) "registers (6) "registers (6)
"registers (1) "registers (3) "registers (5)
registers (7)"
-Dl-
3560 0 768 0 0 0 0 0 0
3600 0 768 0 0 0 0 0 0
3605 0 768 0 0 0 0 0 0
3650 0 768 0 0 0 0 0 0
3700 0 768 0 0 0 0 0 0
3750 0 768 0 0 0 0 0 0
3800 0 768 0 0 0 0 0 03850 0 768 0 0 0 0 0 03900 0 768 0 0 0 0 0 04010 0 768 0 0 0 0 0 04050 0 768 0 0 0 0 0 0
4055 0 768 0 0 0 0 0 04100 0 768 0 0 0 0 0 0
4150 0 768 0 0 0 0 0 04200 0 768 0 0 0 1536 0 04250 0 768 0 0 0 1536 0 0
4300 0 768 0 0 0 1536 0 0
4410 0 768 0 0 0 1536 0 0
4450 0 768 0 0 0 1536 0 0
4455 0 768 0 0 0 1536 0 0
4500 0 768 0 0 0 1536 0 0
4550 0 768 0 0 0 1536 0 0
4600 0 768 0 0 0 1568 0 0
4650 0 768 0 0 0 1568 0 0
4700 0 768 0 0 0 1568 0 0
4810 0 768 0 0 0 1568 0 0
4850 0 768 0 0 0 1568 0 0
4855 0 768 0 0 0 1568 0 0
4900 0 768 0 0 0 1568 0 0
4950 0 768 0 0 0 1568 0 0
5000 0 768 0 0 0 1568 0 0
5050 0 768 0 0 0 1568 0 0
5100 0 768 0 0 0 1568 0 0
5150 0 768 0 0 0 1568 0 0
5260 0 768 0 0 0 1568 0 0
5300 0 768 0 0 0 1568 0 0
5305 0 768 0 0 0 1568 0 0
5350 0 768 0 0 0 1568 0 0
5400 0 768 0 0 0 1568 0 0
5450 0 768 0 0 0 1568 0 0
5500 0 768 0 0 0 1568 0 0
5550 0 768 0 0 0 1568 0 0
5660 0 768 0 0 0 1568 0 0
5700 0 768 0 0 0 1568 0 0
5705 0 768 0 0 0 1568 0 0
5750 0 768 0 0 0 1568 0 0
5800 0 768 0 0 0 1568 0 0
5850 0 768 0 0 255 1568 0 0
5900 0 768 0 0 255 1568 0 0
5950 0 768 0 0 255 1568 0 0
6060 0 768 0 0 255 1568 0 0
6100 0 768 0 0 255 1568 0 0
6105 0 768 0 0 255 1568 0 0
6150 0 768 0 0 255 1568 0 0
6200 0 768 0 0 255 1568 0 0
6250 0 768 0 0 255 1568 0 0
6300 0 768 0 0 255 255 0 0
6350 0 768 0 0 255 255 0 0
6400 0 768 0 0 255 255 0 0
6450 0 768 0 0 255 255 0 0
6600 0 768 0 0 255 255 0 0
6650 0 768 0 0 255 255 0 0
6700 0 768 0 0 255 255 0 0
TIME "registers (0) "registers (3) "registers (6) "registers (6)
"registers (1) "registers (3) "registers (5)
registers (7)"
-D2-
6850 0 768 0 0 255 255 0 0
6900 0 768 0 0 255 255 0 0
7050 0 768 0 0 255 255 0 0
7100 0 768 0 0 255 255 0 0
7150 0 768 0 0 255 255 0 0
7260 0 768 0 0 255 255 0 0
7300 0 768 0 0 255 255 0 0
7305 0 768 0 0 255 255 0 0
7500 0 768 0 0 255 255 0 0
7550 0 768 0 0 255 255 0 0
7600 0 768 0 0 255 255 0 0
7710 0 768 0 0 255 255 0 0
7750 0 768 0 0 255 255 0 0
7755 0 768 0 0 255 255 0 0
7800 0 768 0 0 255 255 0 0
7850 0 768 0 0 255 255 0 0
7900 0 768 0 0 255 255 0 0
7950 0 768 0 0 255 255 0 0
8000 0 768 0 0 255 255 0 0
8150 0 768 0 0 255 255 0 0
8200 0 768 0 0 255 255 0 0
8250 0 768 0 0 255 255 0 0
8360 0 768 0 0 255 255 0 0
8400 0 768 0 0 255 255 0 0
8405 0 768 0 0 255 255 0 0
8450 0 768 0 0 255 255 0 0
8500 0 768 0 0 255 255 0 0
8550 0 16 0 0 255 255 0 0
8600 0 16 0 0 255 255 0 0
8650 0 16 0 0 255 255 0 0
8760
8800
8805
8850
8900
8950
9000
9050
9100
9210
9250
9255
9300
9350
9650
0 768
0 768
0 768
0 768
0 768
0 768
0 768
0 768
0 768
0 768
0 768
0 768
0 768
0 768
0 768
0 768
0 768
0 768
0 768
0 768
0 768
0 768
0 768
0 768
0 768
0 768
0 768
0 1 6
0 16
0 16
0 16
0 16
0 16
0 16
0 16
0 16
0 23
0 23
0 23
0 23
0 23
0 23
0 23
0 23
0 23
0 23
0 23
0 23
0 23
0 23
0 23
0 23
0 23
0 23
0 23
0 23
0 23
0 23
0 23
0 768
0 768
0 768
0 768
0 768
0
9400 0 23 0 0 255 255 0 0
9450 0 23 0 0 255 255 0 0
9500 0 23 0 0 255 255 0 0
96lS 0 23 0 0 255 255 0 0
0
9655 0 23 0
conn 0 23 0 0 Zbb Z55 u u
9Zr?"
H n 0 255 255 0 0
0 255 255
0 255 255
0 255 255
0 255 255
0 255 255
0 255 255
0 255 255
0 255 255
0 255 255
0 255 255
0 255 255
0 255 255
0 255 255
0 255 255
0 255 255
0 255 255
0 255 255
0 255 255
0 255 255
0 255 255
0 255 255
0 255 255
0 255 255
0 255 255
0 255 255
0 255 255
0 255 255
0 255 255
0 255 255
0 255 255
0 255 255
0 255 255
0 255 255
0 255 255
0 255 255
0 255 255
0 255 255
0 255 255
0 255 255
0 255 255
0 255 255
0 255 255
0 255 255
0 255 255
0 255 255
0 255 255
0 255 255
0 255 255
0 255 255
0 255 255
0 255 255
0 255 255
0 255 255
0 255 255
0 255 255
0 255 255
0 255 255
0 255 255
0 255 255
0 255 255
0 255 255
0 255 255
0 255 255
0 255 255
0 0 255 255 0 0
0 0 255 255 0 0
0 0 255 255 0 0
0 0 255 255 0 0
0 0 255 255 0 0
0 0 255 255 0 0
0 0 255 255 0 0
0 0 255 255 0 0
0 0 255 255 0 0
0 0 255 255 0 0
0 0 255 255 0 0
0 0 255 255 0 0
0 0 255 255 0 0
0 0
0 0
0 0
0 0
0 09750 0 23 0
QRnn 0 23 0 0 2bb zn v u
!=n n 23 0 0 255 255 0 0
llln n 23 0 0 255 255 0 0
"Jnn n 23 0 0 255 255 0 0
10000 0 23 0
255 Q Q
10005 0 23 0
255 o Q
10050 0 23 0
255 Q Q
1012n n ill 0 0 255 255 0 0
10^n n 768 0 0 255 255 0 0
10o:n n 768 0 0 255 255 0 0
10~n n ill 0 0 255 255 0 0
1360 0 768 u u
10400 0 768 0 0 25j ..:>, U
TIME "registers (0) "registers (3) "registers (6) "registers (6)1
"reqisters(l)"registers (3) "registers (5)
registers (7)"
-D3-
10405 0 768 0
10450 0 768 0
10500 0 768 0
10550 0 768 0
10600 0 768 0
10710 0 768 0
10750 0 768 0
10755 0 768 0
10800 0 768 0
10850 0 768 0
10900 0 768 0
10950 0 768 0 u -o w, n
H000 0 768 0 0 HI HI n
H110 0 768 0
1H50 0 768 0 0 255 HI n
11155 0 768 0
11200 0 768 0
11250 0 768 0
11300 0 768 0
11350 0 768 0
11460 0 768 0
11500,
0 768 0
11505 0 768 0
11550 0 768 0
11600 0 768 0
11650 0 768 0
11700 0 768 0
11750 0 '768 0
11800 0 768 0
11910 0 768 0 0 255 255 0 011950 0 768 0 0 255 255 0 0
0 768
0 768
0 768
0 768
0 768
0 768
0 768
0 768
0 768
0 768
0 768
0 768
0 768
0 768
0 768
0 768
0 768
0 768
0 768
0 768
0 768
0 768
0 768
0 768
0 768
0 768
0 768
0 '768
0 7 68
0 768
0 768
0 768
0 768
0 768
0 768
0 768
0 768
0 768
0 768
0 768
0 768
0 768
0 768
0 768
0 768
0 768
0 768
0 768
0 768
0 768
0 768
0 800
0 800
0 800
0 800
0 800
0 800
0 800
0 800
0 800
0 800
0 800
0 800
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
11955 0 768 0 0 255 255 0 012000 0 768 0 0 255 255 0 0
12050 0 768 0 0 255 255 0 0
12100 0 768 0 0 255 255 0 0
12150 0 768 0 0 255 255 510 0
12200 0 768 0 0 255 255 510 0
12250 0 768 0 0 255 255 510 0
12360 0 768 0 0 255 255 510 0
12400 0 768 0 0 255 255 510 0
12405 0 768 0 0 255 255 510 0
12450 0 768 0 0 255 255 510 0
12500 0 768 0 0 255 255 510 0
12550 0 768 0 0 255 255 510 0
12600 0 768 0 0 255 255 510 0
12650 0 768 0 0 255 255 510 0
12760 0 768 0 0 255 255 510 0
12800 0 768 0 0 255 255 510 0
12805 0 768 0 0 255 255 510 0
12850 0 768 0 0 255 255 510 0
12900 0 768 0 0 255 255 510 0
12950 0 800 0 0 255 255 510 0
13000 0 800 0 0 255 255 510 0
13050 0 800 0 0 255 255 510 0
13160 0 800 0 0 255 255 510 0
13200 0 800 0 0 255 255 510 0
13205 0 800 0 0 255 255 510 0
13250 0 800 0 0 255 255 510 0
13300 0 800 0 0 255 255 510 0
13350 0 800 0 0 255 255 510 0
13400 0 800 0 0 255 255 510 0
13550 0 800 0 0 255 255 510 0
13600 0 800 0 0 255 255 510 0
TIME "registers (0) "registers (3) "registers (6) "registers (6)"registers (1) "registers (3) "registers (5)
registers (7)"
-d4-
0 255 255 0
0 255 255 00 255 255 0
0 255 255 0
0 255 255 00 255 255 00 255 255 0
0 255 255 0
0 255 255 00 255 255 00 255 255 0
0 255 255 0
0 255 255 0
0 255 255 0
0 255 255 0
0 255 255 0
0 255 255 0
0 255 255 0
0 255 255 0
0 255 255 0
0 255 255 0
0 255 255 0
0 255 255 0
0 255 255 0
0 255 255 0
0 255 255 0
0 255 255 0
0 255 255 0
0 255 255 0
0 255 255 0
0 255 255 0
0 255 255 0
0 255 255 0
0 255 255 0
0 255 255 0
0 255 255 510
0 255 255 510
0 255 255 510
0 255 255 510
0 255 255 510
0 255 255 510
0 255 255 510
0 255 255 510
0 255 255 510
0 255 255 510
0 255 255 510
0 255 255 510
0 255 255 510
0 255 255 510
0 255 255 510
0 255 255 510
0 255 255 510
0 255 255 510
0 255 255 510
0 255 255 510
0 255 255 510
0 255 255 510
0 255 255 510
0 255 255 510
0 255 255 510
0 255 255 510
0 255 255 510
0 255 255 510
0
13650
13700
13810
13850
13855
13900
13950
14000
14050
14100
14210
14250
14255
14300
14350
14400
14450
14500
14610
14650
14655
14700
14750
14800
14850
14900
14950
15060
15100
15105
15150
15200
15250
15300
15350
15500
15550
15600
15710
15750
15755
15800
15850
15900
15950
16060
16100
16105
16150
16200
16250
16300
16350
16460
16500
16505
16550
16600
16650
16700
16750
16860
0 800 0 0 255 255 510
0 800 0 0 255 255 510
0 800 0 0 255 255 510
0 800 0 0 255 255 510
0 800 0 0 255 255 510
0 800 0 0 255 255 510
0 800 0 0 255 255 510
0 800 1024 0 255 255 510
0 800 1024 0 255 255 5100 800 1024 0 255 255 510
0 800 1024 0 255 255 510
0 800 1024 0 255 255 510
0 800 1024 0 255 255 510
0 800 1024 0 255 255 510
0 800 1024 0 255 255 510
0 800 1200 0 255 255 510
0 800 1200 0 255 255 510
0 800 1200 0 255 255 510
0 800 1200 0 255 255 510
0 800 1200 0 255 255 510
0 800 1200 0 255 255 510
0 800 1200 0 255 255 510
0 800 1200 0 255 255 510
0 800 1200 0 255 255 510
0 800 1200 0 255 255 513
0 800 1200 0 255 255 513
0 800 1200 0 255 255 513
0 800 1200 0 255 255 513
0 800 1200 0 255 255 513
0 800 1200 0 255 255 513
0 800 1200 0 255 255 513
0 800 1200 0 255 255 513
0 800 1200 0 255 255 513
0 800 1200 0 255 255 513
0 800 1200 0 255 255 513
0 800 1200 0 255 255 513
0 800 1200 0 255 255 513
0 800 1200 0 255 255 513
0 800 1200 0 255 255 513
0 800 1200 0 255 255 513
0 800 1200 0 255 255 513
0 800 1200 0 255 255 513
0 800 1200 0 255 255 513
0 800 1200 0 255 255 513
0 800 1200 0 255 255 513
0 800 1200 0 255 255 513
0 800 1200 0 255 255 513
0 800 1200 0 255 255 513
0 800 1200 0 255 255 513
0 800 1200 0 255 255 513
0 800 1200 0 513 255 513
0 800 1200 0 513 255 513
0 800 1200 0 513 255 513
0 800 1200 0 513 255 513
0 800 1200 0 513 255 513
0 800 1200 0 513 255 513
0 800 1200 0 513 255 513
0 800 1200 0 513 255 513
0 800 1200 1566 513 255 513
0 800 1200 1566 513 255 513
0 800 1200 1566 513 255 513
0 800 1200 1566 513 255 513
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
TIME 'registers (0) "registers (3) "registers (6) "registers (6)
"registers (1) "registers (3) "registers (5)
registers (7)"
-D5-
16900 0 800 1200 1566 513 255 513 0
16905 0 800 1200 1566 513 255 513 0
16950 0 800 1200 1566 513 255 513 0
17000 0 800 1200 1566 513 255 513 0
17050 0 800 1200 1566 513 255 513 0
17100 0 800 1200 1566 513 255 513 017150 0 800 1200 1566 513 255 513 017200
17250 0 800 1200 1566 513 255 513 017400 0 800 1200 1566 513 255 513 017450
19150
19310
19350
19355
19400
19450
19500
19550
19600
19650
19700
19850
19900
19950
20060
20100
20105
0 800 1200 1566 513 255 513
0 800 1200 1566 513 255 513
0 800 1200 1566 513 255 513
0 800 1200 1566 513 255 513
0 800 1200 1566 513 255 513
0 800 1200 1566 513 255 513
0 800 1200 1566 513 255 5130 800 1200 1566 513 255 513
0 800 1200 1566 513 255 513
0 800 1200 1566 513 255 513
0 800 1200 1566 513 255 513
0 800 1200 1566 513 255 513
0 800 1200 1566 513 255 513
0 800 1200 1566 513 255 513
0 800 1200 1566 513 255 513
0 800 1200 1566 513 255 513
0 800 1200 1566 513 255 513
0 800 1200 1566 513 255 513
0 800 1200 1566 513 255 513
0 800 1200 1566 513 255 513
0 800 1200 1566 513 255 513
0 800 1200 1566 513 255 513
0 800 1200 1566 513 255 513
0 800 1200 1566 513 255 513
0 800 1200 1566 513 255 513
0 800 1566 1566 513 255 513
0 800 1566 1566 513 255 513
0 800 1566 1566 513 255 513
0 800 1566 1566 513 255 513
0 800 1566 1566 513 255 513
0 800 1566 1566 513 255 513
0 800 1566 1566 513 255 513
0 800 1566 1566 513 255 513
0 800 1566 1566 513 255 513
0 800 6264 1566 513 255 513
0 800 6264 1566 513 255 513
0 800 6264 1566 513 255 513
0 800 6264 1566 513 255 513
0 800 6264 1566 513 255 513
0 800 6264 1566 513 255 513
0 800 6264 1566 513 255 513
0 800 6264 1566 513 255 513
0 800 6264 1566 513 255 513
0 800 783 1566 513 255 513
0 800 783 1566 513 255 513
0 800 783 1566 513 255 513
0 800 783 1566 513 255 513
0 800 783 1566 513 255 513
0 800 783 1566 513 255 513
0 800 783 1566 513 255 513
0 800 783 1566 513 255 513
0 800 783 1566 513 255 513
0 800 783 1566 513 255 513
0 800 783 1566 513 255 513
0 800 783 1566 513 255 513
0 800 783 1566 513 255 513
0 800 783 1566 513 255 513
0 800 783 1566 513 255 513
0 800 783 1566 513 255 513
0 800 783 1566 513 255 513
0 800 783 1566 513 255 513
0 800 783 1566 513 255 513
0
0
17500 0 800 1200 1566 513 255 513 0
17610 0 800 1200 1566 513 255 513 0
17650 0 800 1200 1566 513 255 513 0
17655 0 800 1200 1566 513 255 513 0
17700 0 800 1200 1566 513 255 513 0
17750 0 800 1200 1566 513 255 513 0
17800 0 800 1200 1566 513 255 513 0
17850 0 800 1200 1566 513 255 513 0
17900 0 800 1200 1566 513 255 513 0
18010 0 800 1200 1566 513 255 513 0
18050 0 800 1200 1566 513 255 513 0
18055 0 800 1200 1566 513 255 513 0
18100 0 800 1200 1566 513 255 513 0
18150 0 800 1200 1566 513 255 513 0
18200 0 800 1566 1566 513 255 513 0
18250 0 800 1566 1566 513 255 513 0
18300 0 800 1566 1566 513 255 513 0
18410 0 800 1566 1566 513 255 513 0
18450 0 800 1566 1566 513 255 513 0
18455 0 800 1566 1566 513 255 513 0
18500 0 800 1566 1566 513 255 513 0
18550 0 800 1566 1566 513 255 513 0
18600 0 800 1566 1566 513 255 513 0
18650 0 800 6264 1566 513 255 513 0
18700 0 800 6264 1566 513 255 513 0
18750 0 800 6264 1566 513 255 513 0
18860 0 800 6264 1566 513 255 513 0
18900 0 800 6264 1566 513 255 513 0
18905 0 800 6264 1566 513 255 513 0
18950 0 800 6264 1566 513 255 513 0
19000 0 800 6264 1566 513 255 513 0
19050 0 800 6264 1566 513 255 513 0
19100 0 800 783 1566 513 255 513 0
0
19200 0 800 783 1566 513 255 513 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
TIME "registers (0) "registers (3) "registers (6) "registers (6)
"registers (1) "registers (3) "registers (5)
registers (7)"
-D6-
20150 0 800 783 1566 513 255 513 0
20200 0 800 783 1566 513 255 513 0
20250 0 800 783 1566 513 255 513 0
20300 0 800 783 1566 513 255 513 0
20350 0 800 783 1566 513 255 513 0
20460 0 800 783 1566 513 255 513 0
20500 0 800 783 1566 513 255 513 0
20505 0 800 783 1566 513 255 513 0
20550 0 800 783 1566 513 255 513 0
20600 0 800 783 1566 513 255 513 0
20650 0 800 783 3 513 255 513 0
20700 0 800 783 3 513 255 513 0
20750 0 800 783 3 513 255 513 0
20860 0 800 783 3 513 255 513 0
20900 0 800 783 3 513 255 513 0
20905 0 800 783 3 513 255 513 0
20950 0 800 783 3 513 255 513 0
21000 0 800 783 3 513 255 513 0
21050 0 800 783 3 513 255 513 0
21100 0 800 783 768 513 255 513 0
21150 0 800 783 768 513 255 513 0
21200 0 800 783 768 513 255 513 0
21310 0 800 783 768 513 255 513 0
21350 0 800 783 768 513 255 513 0
21355 0 800 783 768 513 255 513 0
21400 0 800 783 768 513 255 513 0
21450 0 800 783 768 513 255 513 0
21500 0 800 783 768 513 255 513 0
21550 0 800 783 768 513 255 513 0
21660 0 800 783 768 513 255 513 0
21700 0 800 783 768 513 255 513 0
21705 0 800 783 768 513 255 513 0
21750 0 800 783 768 513 255 513 0
21800 0 800 783 768 513 255 513 0
21850 0 800 783 768 513 255 513 0
21900 0 800 783 768 513 255 513 0
21950 0 800 783 768 513 255 513 0
22000 0 800 783 768 513 255 513 0
22110 0 800 783 768 513 255 513 0
22150 0 800 783 768 513 255 513 0
22155 0 800 783 768 513 255 513 0
22200 0 800 783 768 513 255 513 0
22250 0 800 783 768 513 255 513 0
TIME "registers (0) "registers (3) "registers (6) "registers (6)
"registers (1) "registers (3) "registers (5)registers (7)
"
-D7-
