particles of powder have an average diameter of 50 nm. The devel-oped powder with 80% by weight mixed in epoxy resin.

3. RESULTS AND ANALYSIS

In experiments, the ferrites were placed at the center of waveguide;the width w of the ferrites is 22 mm, the thickness t are 1.5, 3.0,and 4.5 mm individually, and the length d are 0.25L, 0.5L, 0.75L,and 1.0L where L � 37.5 mm. The effect of d and t is investigated.Figure 2 shows the measured frequency responses for a rectangularwaveguide filled with various sizes of ferrite.

From the experimental results, the verification of the occur-rence of backward waves in the partial filled waveguide with TE10

mode is presented. Thus, the transversal width of such awaveguide can be relatively longer. In practice, the increase of thethickness t of ferrite causes deviation of 0.33, 0.66, and 0.92 GHzrespectively, when d � 1.0L. The results show that the waveguidestructure has tunable left-handed material property by changing thesize of ferrite, and the significant transmission property is belowthe cutoff frequency of waveguide. The insertion loss is withvariation of 4–23 dB. The related �3dB fractional bandwidth ofthe backward waves is among the range of 0.6–0.9%.

Both the frequency responses of measured and simulated re-sults with a smaller size d � 0.25L and t � 1.5 mm, and a largersize d � 1.0L and t � 4.5 mm respectively are presented in Figure3. The measured results are in agreement with the simulated resultsby HFSS simulator.

4. CONCLUSIONS

The measured results revealed backward waves below the cut-offfrequency of the dominant TE mode presented. Transversal widthof such a waveguide can be relatively longer. In practice, theincrease of the physical length causes the size reduction about10–26%. The insertion loss of 4–23 dB is presented. The appli-cations of the effect can be applied in the design of waveguidesminiaturization, tunable filters, etc.

ACKNOWLEDGMENT

The authors thank the assistance by Professor Dau-Chyrh Chang ofDa Yeh University.

REFERENCES

1. N. Marcuvitz, Waveguide handbook, McGraw-Hill, New York, 1951,pp. 404–405.

2. M.N.M. Kehn and P.S. Kildal, Miniaturization rectangular hardwaveguides for use in multifrequency phased arrays, IEEE Trans An-tennas Propag 53 (2005), 100–109.

3. S. Hrabar, J. Bartolic, and Z. Sipus, Waveguide miniaturization usinguniaxial negative permeability metamaterial, IEEE Trans AntennasPropaga 53 (2005), 110–119.

4. I.A. Eshrah, A.A. Kishk, A.B. Yakovlev, and A.W. Glisson, Rectangu-lar waveguide with dielectric-filled corrugations supporting backwardwaves, IEEE Trans Microwave Theory Tech 53 (2005), 3298–3303.

5. A. Dechant and M. Okoniewski, Broadband double negative metama-terial from ferrite-loaded metallic waveguides, Electron Lett 42 (2006),4–5.

6. Y.S. Hong, C.M. Ho, H.Y. Hsu, and C.T. Liu, Synthesis of nanocrys-talline Ba(MnTi)xFe12–2xO19 powders by the sol-gel combustion methodin citrate acid-metal nitrates system (x � 0, 0.5, 1.0, 1.5, 2.0), J MagnMagn Mater 279 (2004), 401–410.

© 2006 Wiley Periodicals, Inc.

DESIGN AND SIGNAL INTEGRITYSIMULATION OF HIGH SPEED DIGITALSYSTEM

Yuanqing Wang, Wei Hong, Haiming Wang, Nianzu Zhang,Guangqi Yang, Leilei Liu, Hui Zhang, and Jin ChangState Key Laboratory of Millimeter Waves,Department of Radio Engineering,Southeast University,Nanjing 210096, People’s Republic of China

Received 29 May 2006

ABSTRACT: In this article, the design and implementation of a high-speed digital system including two daughter boards and a backplane aredescribed, where the emphasis is focused on the systematic analysis ofthe signal integrity performance using full wave electromagnetic meth-ods combined with circuit simulation. Shielded differential vias is pre-sented for high-speed digital design. The proposed digital systemachieves a data rate exceeding 3 Gbps (bit per second)/pair. Deembedprocess is presented to improve the accuracy of simulation. The simu-lated and measured results in time domain are in agreement. © 2006Wiley Periodicals, Inc. Microwave Opt Technol Lett 49: 203–210, 2007;Published online in Wiley InterScience (www.interscience.wiley.com).DOI 10.1002/mop.22076

Key words: signal integrity; interconnects; high speed digital system;cascade network; full-wave electromagnetic simulation; deembed

1. INTRODUCTION

With the continuous increment of clock frequency and data trans-mission rate of digital communication systems, serial data rate of3.125 Gbps even 10 Gbps can be achieved now [1–3]. The risingedge and falling edge of digital signals become sharper because ofthe continuous increasing speed of data transmission. Therefore,the spectrum of digital signals has already expanded to microwave,even millimeter, wave band. Compared with the previous workconcerned with logical problem, the issue of signal integrity (SI) iscoming to be necessary to high-speed digital designers. SI is acondition in which digital signals can properly be resolved at theirintended level by receiver [1, 2].

Serial data transmission is of critical importance to the high-speed digital communication. Serial transceiver converts paralleldata at lower speed to serial data at higher speed. As its goodcapability of common mode rejection, differential signal has beenwidely used in high-speed digital communication systems. Lowvoltage differential signaling is such a standard in wide application

Figure 1 Structure of high speed digital communication system. [Colorfigure can be viewed in the online issue, which is available at www.interscience.wiley.com]

DOI 10.1002/mop MICROWAVE AND OPTICAL TECHNOLOGY LETTERS / Vol. 49, No. 1, January 2007 203

[4], which provides the physical foundation for Gbps data trans-mission system.

In this article, the design and implementation of a high-speeddigital system are introduced. The proposed digital systemachieves a data rate exceeding 3 Gbps/pair. The good perfor-mances of the interconnect system were verified by measured eyediagram and bit error rate (BER) results.

Accurate simulation is the important guarantee for the perfor-mances of a high-speed digital system. Previously, work wasmainly focused on the simulation of interconnection based onquasistatic field or TEM field assumption [5, 6]. However, asexpanding spectrum of digital signals, such methods cannot ensurethe accuracy. There are also some reports for the SI analysis of thecircuit using full wave methods, some of which are concerned tocomponents rather than system [7]. Full-wave electromagnetic(EM) simulation of the whole system is also adopted to obtain theresponse of interconnection [8]. But for a complex high-speeddigital system consists daughter boards, backplane, and connec-tors, huge computing time and memory requirement will be a bigproblem if entire full-wave EM simulation is adopted. Further-more, the SI performance of the system is not only affected byinterconnection but also by the driver and receiver. The publica-tions mentioned above are all focused on the analysis of intercon-nects. Since the integrated circuits (IC, here mean Chips) modelsare not involved, signal jitter cannot be estimated from the EMsimulation. In this article, we investigated the modeling of acomplex high-speed digital system, and the interconnection wasdivided into several parts. Each part was firstly simulated by usingfull-wave EM solver to get the accurate frequency responses, then

deembed process is introduced to further improve the accuracy,and finally it was transformed to SPICE model. Therefore, thesimulation of the whole high-speed digital system can be per-formed with Cadence software, based on the SPICE models of theinterconnection, connectors, and transmitter/receiver ICs in timedomain. The waveform and eye diagram are then obtained withsystem level simulation and measurement.

2. DESIGN OF HIGH-SPEED DIGITAL SYSTEM

A structure of high-speed digital system including daughterboards, backplane, and connectors is shown in Figure 1. ICs on thedaughter boards play the role of transmitting or receiving data. Thetransmission path of signal in the system is called interconnectsystem. It includes the transmission lines on the daughter boards,backplane, and connectors. The interconnect system should bedesigned properly to guarantee the performance of high-speeddigital system.

Because differential signal is introduced in high-speed digitalsystem, coupled microstrip lines (CMSL) and striplines (CSTL)are widely used for transmission of differential signal. Noiseinduced on the differential lines is likely to appear as commonmode, which can be canceled by the differential signal receiver.

Figure 2 Cross-sections of CMSLs and CSTLs

Figure 3 (a) Differential vias and (b) shielded differential vias. [Colorfigure can be viewed in the online issue, which is available at www.interscience.wiley.com]

Figure 4 Simulated differential mode S21 parameters of the designeddifferential vias and perfect CMSLs

Figure 5 Photograph of the high-speed digital demo system. [Colorfigure can be viewed in the online issue, which is available at www.interscience.wiley.com]

204 MICROWAVE AND OPTICAL TECHNOLOGY LETTERS / Vol. 49, No. 1, January 2007 DOI 10.1002/mop

The cross-sections of CMSLs and CSTLs (edge coupled) areshown in Figure 2.

The characteristic impedance Z0 and the differential character-istic impedance Zdiff of the CMSLs and CSTLs can be calculatedusing following equations respectively [9]:

Zdiff � 2 � Z0�1 � 0.48e�0.96Sh� for CMSL (1)

Zdiff � 2 � Z0�1 � 0.347e�2.9Sh� for CSTL (2)

where

Z0 �60

�0.475�r � 0.67ln � 4h

0.67�0.8W � t�� for CMSL (3)

Z0 �60

��r

ln � 4h

0.67��0.8W � t�� for CSTL (4)

Because of the complexity of the high-speed digital system, thediscontinuities like vias and bends are inevitable. Some paperswere focused on the equivalent circuit model of the discontinuities[10–14], which are useful for high-speed digital system design andsimulation. With the frequency spectrum of a high-speed digitalsignal expanding, full-wave simulation is required to optimize thestructures of vias, bends in the interconnect system to mitigate thereflection and radiation caused by the discontinuities. Because ofwide application of differential signal, differential vias become theimportant discontinuity that high-speed circuit designers must de-sign properly to mitigate impedance mismatching.

Figure 3(a) shows an example of structure of differential vias ina six-layer FR4 PCB with 0.38-mm layer thickness. The relativedielectric constant is 4.5. The structure is made up of a pair ofdifferential via holes, which is connected with a pair of microstriplines. The differential via holes can be approximately modeled asbifilar transmission lines [13]. The differential inductance L, ca-pacitance C and impedance Z can be calculated by followingapproximation equations:

L ��

�ln�D � d

d � (5)

C ���

ln�D � d

d � (6)

Figure 6 Photographs of the (a) daughter board and (b) backplane.[Color figure can be viewed in the online issue, which is available atwww.interscience.wiley.com]

Figure 7 Cascading equivalent network of high speed digital system

Figure 8 Layout of a layer in the daughter board. [Color figure can beviewed in the online issue, which is available at www.interscience.wiley.com]

DOI 10.1002/mop MICROWAVE AND OPTICAL TECHNOLOGY LETTERS / Vol. 49, No. 1, January 2007 205

Z � �L

c(7)

where D is the space between the centers of differential vias and dis the radius of the via holes. For impedance matching, the differ-ential impedance of the differential vias should be equal to thedifferential lines. Once Z was determined, D and d can be calcu-lated using the above formulae.

Since differential vias is an open structure, the distribution ofelectric field will be easily influenced by the surrounding groundplanes [15]. It would cause impedance discontinuity, so we presentthe shielded differential vias shown in Figure 3(b). The shieldeddifferential vias is a closed structure. The differential mode capac-itance and inductance can be easily obtained by using 2D quasis-tatic field-based software such as Ansoft SI2D. In this structure,the width of microstrip lines and the space between microstriplines are 0.49 and 0.38 mm, respectively. The radius of vias, pads,and antipads are 0.127, 0.254, and 1 mm, respectively. The spacebetween the center of differential vias and shielding grounded viasis 0.87 mm. The simulated differential mode S21 parameters of thisstructure and a pair of perfect CMSL are shown in Figure 4.Through the comparison, we can find that the loss caused bydifferential mode impedance mismatching is much lower than 0.1dB. The design process is efficient.

Because the differential signal is always transferred in thehigh-speed digital system, the differential-mode transmission lossis the most important thing that high-speed circuit designers careabout. As shown in Figure 4, the differential-mode S21 parameterof the structure with discontinuities is close to the structure withoutdiscontinuity below 8 GHz. From the comparison, the properlydesigned differential vias mitigate the differential impedance mis-matching. Compared with full-wave EM simulation, the 2D qua-sistatic field analysis combined with approximation equationsshows advantages of time saving and acceptable efficiency.

A high-speed digital demo system is designed and imple-mented. Two daughter boards and the backplane constitute thewhole system. In the system, the core devices in the daughterboards are two pieces of XILINX’s FPGA chips: XC2VP20 whereserial transceivers are embedded. The FPGA can transmit high-speed data through differential lines using serial transceivers.Daughter boards are connected with the backplane by HIROSE’sHX2 connectors. Each daughter board can transmit and receivedata simultaneously. The data transmitted between daughterboards is communicated through the backplane. A photograph ofthe high-speed digital circuit demo system is shown in Figure 5.

Photographs of the daughter board and backplane of the systemare shown in Figure 6. The daughter boards are designed with FR4

PCB of eight layers with 0.26-mm layer thickness, where therelative dielectric constant is 4.5. The backplane is designed withFR4 PCB of six layers with 0.36-mm layer thickness, where therelative dielectric constant is also 4.5. Serial signals (14 pair) andLVDS signals (18 pair) transfer through backplane between thetwo daughter boards.

It is known that the spectrum of digital signal is decided by riseand fall time of signal. From the data sheet of XC2VP20, it isfound that the rise time of high-speed serial signal is 120 ps [16].The Fknee of digital signal can be calculated using approximationequation [2]:

Fknee �0.5

Tr(8)

where Tr is the rise time of digital signal. Beyond Fknee, spectrumwill roll off much faster. Thus the major spectrum of high-speedserial signal generated by XC2VP20 is below 8 GHz. Therefore,the layout of daughter boards and backplane can be designed basedon the procedure above.

3. MODELING AND SIMULATION OF HIGH-SPEED DIGITALSYSTEM

Accurate models of drivers, receivers, and interconnect system arethe key for a successful simulation of high-speed system. Driversand receivers are active devices, while the interconnect system ispurely a passive system.

The accuracy of signal integrity analysis depends on the accu-racy of the semiconductor circuit models of drivers and receivers.IBIS (I/O buffer information specification) is an emerging standardfor electronic behavioral specifications of digital integrated circuitinput/output analog characteristics while revealing no proprietaryinformation about the design or process technology. SPICE modelis a transistor-level model providing more accuracy. But it mayreveal vendor’s proprietary device information. Now, encryptedHSPICE model can maintain the confidentiality owed to propri-etary information. In simulation of the system shown in Figure 5,the encrypted HSPICE model provided by Xilinx is adopted.

Because of its passivity, the whole interconnect system can betreated as linear time invariant system. In theory, it is the mostaccurate to analyze the whole interconnect system by full-waveEM field solver. With increasing data rate, the connectors aredesigned and produced precisely for high-speed data transmission.Vendors of connectors would like to provide circuit model ratherthan detailed structure of high-speed connectors because of pro-prietary information. So it is hard to model the whole systemprecisely using full-wave EM field solver. Furthermore, it is not

Figure 9 Topology of system level simulation. [Color figure can be viewed in the online issue, which is available at www.interscience.wiley.com]

206 MICROWAVE AND OPTICAL TECHNOLOGY LETTERS / Vol. 49, No. 1, January 2007 DOI 10.1002/mop

proper for full-wave EM field solver to analyze such an electricallylarge problem as the whole digital communication system. Be-cause differential signal is chosen, we divide the whole system intoseveral multiport networks. In this article, we present the methodof cascaded network to model the digital system as shown inFigure 7.

The interconnect system is divided into four networks: connec-tors, backplane, and two daughter boards. The SPICE model ofconnectors provided by vendors is adopted in the simulation of thesystem. The daughter boards and backplane must be analyzed bydesigners. Ansoft high-frequency structure simulator (HFSS) isused for the frequency domain simulation of each part, which is a

Figure 10 Measured (a) waveform and (b) eye diagram at data speed at 3 Gbps. [Color figure can be viewed in the online issue, which is available atwww.interscience.wiley.com]

DOI 10.1002/mop MICROWAVE AND OPTICAL TECHNOLOGY LETTERS / Vol. 49, No. 1, January 2007 207

3D full-wave EM simulation software. After the interconnectsystem be divided into several parts, the structure of each part isimported into HFSS to simulate. The deembed procedure is pre-sented to improve the accuracy. As an example, layout of a layerof the daughter board is shown in Figure 8. It shows the differentiallines and connector pads. Daughter board and connector can be

divided into two parts at the differential bend. When the differen-tial lines on the daughter board are modeled in HFSS, the discon-tinuities are near the ports. So the high-order mode produced bydiscontinuities should not be fully attenuated at the ports in full-wave EM simulation. In this modeling, two uniform transmissionlines are added after differential bend to cancel the effect ofhigh-order mode. Using following equation, for an n-port networkS-parameter matrix S0 of the original structure can be calculatedfrom S-parameter matrix of the modified structure Sm.

S0 � �erl��1 � Sm � �erl��1 (9)

where

erl � �er1l1 0 0 0 0. . . . . . . . . . . . . . .0 0 erili 0 0

. . . . . . . . . . . . . . .0 0 0 0 ernln

� (10)

TABLE 1 Measured BER Results at Different Data Rate andPreemphasis Level

PreemphasisLevel (%) Bit Error Rate

0 2.5 e �13 at 2.8 Gbps, �1 e �14 at 2.7 Gbps10 2 e �10 at 3.3 Gbps, 1.5 e �12 at 3.25 Gbps,

�1 e �14 at 3.2 Gbps20 3.6 e �13 at 3.4 Gbps, 8.8 e �14 at 3.35 Gbps,

�1 e �14 at 3.3 Gbps30 4 e �11 at 3.6 Gbps, 6.7 e �12 at 3.5 Gbps ,

�1 e �14 at 3.4 Gbps

Figure 11 Comparison between the simulated and measured waveform using periodical signal at 2 Gbps: (a) simulated result and (b) measured result.[Color figure can be viewed in the online issue, which is available at www.interscience.wiley.com]

208 MICROWAVE AND OPTICAL TECHNOLOGY LETTERS / Vol. 49, No. 1, January 2007 DOI 10.1002/mop

ri is the complex propagation constant at ith port, li is length of theuniform transmission line that has been added to ith port of theoriginal structure.

The SPICE model of each part can be extracted from thefrequency domain characteristics by using HFSS, therefore thedigital system shown in Figure 5 can be modeled as severalcascade SPICE models. Then the models are imported into Ca-dence SigXplorer to simulate using HSPICE-based simulator. Thetopology of system-level simulation is shown in Figure 9. Themodels of driver, IC package, transmitting daughter board, twoconnectors, backplane, receiving daughter board, IC package, re-ceiver are connected in turn. Through the HSPICE-based simula-tion, the transient voltage and current waveform at any node can beobtained, and then the eye diagram can be obtained based on thetransient waveform. After the system was designed, the perfor-mance of system can be estimated through simulation.

4. EXPERIMENT AND SIMULATION RESULTS

An Agilent 54855A Infiniium oscilloscope with E2675A differen-tial probe and 6 GHz bandwidth was used to measure the differ-ential voltage waveforms at receiver pads on the daughter board ofthe system shown in Figure 5. Figure 10 shows the measuredwaveform and eye diagram of the example system at the data rate

of 3 Gbps. From the measured waveform, it is obvious thatsignificant component of signal is attenuated heavily. Figure 10shows the eye width of 152 ps and eye height of 172 mV. It canbe concluded that signal can be resolved by receiver properly.

Compared with eye diagram, BER is a more accurate pa-rameter to measure the SI performance of a digital system. Inthis digital system, a BER test function is implemented. Thedata to be transmitted is constructed using pseudorandom bitsequence patterns. The receiver compares the incoming datawith the expected data to count the BER. Because of thedispersive property of interconnect system, it appears low passproperty. The preemphasis function provided by FPGA boostinitial differential voltage swing to create a stronger rising orfalling waveform to improve the quality of received signal.Table. 1 shows the BER measurement at different preemphasislevel and data rate. From the table, we can find that the BERdecreases with increasing preemphasis level. Through the ex-periment, it proves that preemphasis technology is useful forcompensate the dispersive loss of interconnect system. Accord-ing to datasheet, the max guaranteed transmission data rate ofthe FPGA used in this example system is 2 Gbps. Therefore themeasured results validate the efficient design of the high-speeddigital system.

Figure 12 Comparison between eye diagram results simulated and measured using PRBS at 2 Gbps: (a) simulated result and (b) measured result. [Colorfigure can be viewed in the online issue, which is available at www.interscience.wiley.com]

DOI 10.1002/mop MICROWAVE AND OPTICAL TECHNOLOGY LETTERS / Vol. 49, No. 1, January 2007 209

Figure 11 shows the simulated and measured waveform of thesystem with the data rate of 2 Gbps, a good agreement betweensimulated and measured waveforms can be seen. Figure 12 showsthe simulated and measured eye diagram of the system with thedata rate of 2 Gbps. The eye diagram is the result of overlaywaveforms over many cycles. It is useful for high-speed designersto predict the signal integrity performance of complex digitalsystem through simulation. Thereby the method described in thisarticle for the divided modeling and simulation of high-speedinterconnection system is validated.

5. CONCLUSION

In this article, design and implementation of a high-speed digitalsystem are described. Design of differential transmission lines isalso introduced. Discontinuities of transmission lines are the maintrouble, which causes the distortion of signal on PCB. The full-wave analysis combined with equivalent circuit is adopted foroptimization of the discontinuity structures. Measurement vali-dates the design of the high-speed system. The method of model-ing of complex high-speed system is presented. Circuit simulationcombined with full-wave simulation is used to simulate the timedomain performance of high-speed digital system. The simulatedand measured results are in agreement, it verifies the availability ofthe simulation method.

ACKNOWLEDGMENT

The authors are grateful to the colleagues in the State Key Labo-ratory of Millimeter Waves for their valuable support during thedevelopment. This work was supported in part by the NationalScience Foundation of China under grant 90307016, and in part bythe National High Tech Research Plan of China (863 Plan) undergrant 2002AA123031.

REFERENCES

1. R.Y. Chen, Engineering electromagnetic compatibility, 2nd ed.,Wiley, Hoboken, NJ, 2001, Ch. 14.

2. H.W. Johnson and M. Graham, High-speed digital design, PrenticeHall, Englewood Cliffs, NJ, 2001.

3. RocketIO Transceiver User Guide, Xilinx Inc., 2003.4. C. Bloomingdale and G. Hendrickson, LVDS data outputs for high

speed analog-to-digital converters, Analog Devices, Inc., 2001.5. R.H.G. Cuny, SPICE and IBIS modeling kits the basis for signal

integrity analyses, IEEE Int Symp Electromagn Compat 8 (1996),204–208.

6. G. Antonini, J.L. Drewniak, A. Orlandi, and V. Ricchiuti, Eye patternevaluation in high-speed digital systems analysis by using MTL mod-eling, IEEE Trans Microwave Theory Tech 50 (2002), 1807–1815.

7. L. Walling and S. Polstyanko, Solving a high-frequency signal-integ-rity problem, Microwaves RF 39 (2000), 63–66.

8. H. Zhang, W. Hong, and Y.Q. Wang, Design of backplane in high-speed digital system and its signal integrity analysis, Microwave OptTechnol Lett 45 (2004), 194–199.

9. LVDS Owner’s Manual, National Semiconductor, 2004.10. A.A. Oliner, Equivalent circuits for discontinuities in balanced strip

transmission line, IEEE Trans Microwave Theory Tech 3 (1955),134–143.

11. A. Sabban and K.C. Gupta, A planar-lumped model for coupledmicrostrip lines and discontinuities, IEEE Trans Microwave TheoryTech 40 (1992), 245–252.

12. P. Silvester and P. Renedek, Microstrip discontinuity capacitances forright-angle bends, T junction, and crossings, IEEE Trans MicrowaveTheory Tech 21 (1973), 341–346.

13. E. Laermans, J.D. Geest, D.D. Zutter, F. Olyslager, S. Sercu, and D.Morlion, Modeling differential via holes, IEEE Trans Adv Packag 24(2001), 357–363.

14. Q. Gu, Y.E. Yang, and M.A. Tassoudji, Modeling and analysis of vias

in multilayered integrated circuits, IEEE Trans Microwave TheoryTech 41 (1993), 206–214.

15. Y.Q. Wang and W. Hong, Design of differential vias in high speeddigital circuit, In: Proceedings of the Asia-Pacific Microwave Confer-ence, Suzhou, Vol. 5, 2005, pp. 3241–3244.

16. Virtex-II Pro Platform FPGA Handbook, Xilinx, Inc., 1989.

© 2006 Wiley Periodicals, Inc.

DESIGN AND IMPLEMENTATION OF ADUALBAND MICROWAVE FILTERUSING NONUNIFORM LINES

Jhin-Fang Huang and Zong-Min LyuDepartment of Electronic EngineeringNational Taiwan University of Science and Technology43 KeeLung Rd. Sec 4Taipei 106, Taiwan

Received 30 May 2006

ABSTRACT: In this article, we propose a mapping method in whichthe system function of filter in z-domain is founded by discrete-time do-main techniques as well as by chain-scatte ring matrices of varioustransmission-lines is derived to fulfill a dualbandpass microwave filterbased on equal-length nonuniform coupled lines. A dualband filter withthe desired bandwidth and low insertion loss is recognized by cascadingbandpass and bandstop filters. The five-order Butterworth bandstop fil-ter, which uses a coupled-serial-shunted lines structure, causes the im-plantation and correct placement of the bandstop filter. The wide-bandbandpass filter is implemented by the five-order Chebyshev Type IIband-pass filter, which uses serial lines and shunted stubs lines configu-ration. The design process is finished by using optimization algorithmsto tune the values of characteristic impedances of each transmission-linesection. Experimental results significantly agree with the theoretical val-ues. Measurement shows that the 3 dB passband widths are about 20%for the frequency of 2.45 GHz and 10% for the frequency of 5.25 GHz.The insertion loss is about 0.831 dB at the frequency of 2.38 GHz and1.873 dB at the frequency of 5.216 GHz. © 2006 Wiley Periodicals, Inc.Microwave Opt Technol Lett 49: 210–215, 2007; Published online inWiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.22075

Key words: equal-length line; Z transforms; bandpass; bandstop; dual-band filter

1. INTRODUCTION

Microwave filters are two-port components used in an electronicsystem capable of allowing transmission of signals within thepassband and simultaneously rejecting unwanted harmonics overthe stopband [1]. Different kinds of approximations, like Butter-worth, Chebyshev, and elliptic functions have been developed andused frequently as models for microwave filter synthesis. Micro-wave filters with various frequency responses have been thor-oughly studied and previously implemented. Conventional proce-dures to design and implement microwave filters usually beginwith the prototypes developed for lumped-element circuits.Lumped-element circuits with the assistantce of Richard’s trans-formation [2] and Kuroda’s identities are then transformed to thecorresponding distributed element circuits [3]. However, it is dif-ficult to implement microwave filters based on lumped-elementmodels because it is difficult to ignore the effects of componentlengths in microwave frequencies. The replacement of lumped-elements by distributed components has become a popular methodto overcome this inconsistency.

210 MICROWAVE AND OPTICAL TECHNOLOGY LETTERS / Vol. 49, No. 1, January 2007 DOI 10.1002/mop