Design and Implementation of Reconfigurable VLSI Architecture for Optimized Performance Cognitive Radio Wideband Spectrum Sensing

8/15/2019 Design and Implementation of Reconfigurable VLSI Architecture for Optimized Performance Cognitive Radio Wideb…

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Design and Implementationof Recongurable VLSI Architecture

for Optimized Performance CognitiveRadio Wideband Spectrum Sensing

S. Gayathri and K.S. Sujatha

Abstract Spectrum sensing performs major function in cognitive radio to ef -

ciently use the underutilized spectrum. It has to detect the presence of primary user

signal in a channel and has to utilize in primary user ’s absence. In widebandspectrum sensing, a wide frequency has to be sensed. In this paper, a recongurable

VLSI architecture is designed to perform cooperative spectrum sensing for wide-

band, this needs a local detection, which is fundamental for cooperative sensing.

Each and every individual secondary user has to perform energy detection. In this

paper, energy detection technique used is based on the Neyman Pearson criterion.

Then the cooperative decision is taken which increases the sensing performance.

The designed architecture is then implemented in Xilinx Virtex-4 Field pro-

grammable Gate array.

Keywords Neyman pearson criterion Xilinx Virtex-4 eld programmable gatearray MATLAB Cognitive radio network

1 Introduction

Radio spectrum is a natural resource which is essential for wireless systems.Progress in wireless communication system has increased the demand of radio

spectrum. Cognitive radio has become a reassuring approach to mitigate the

spectrum scarcity and to increase the ef ciency of the spectrum utilization. In

cognitive radio systems, the secondary user (unlicensed user) is allowed by primary

user to follow the dynamic spectrum access policy. Spectrum sensing is the basic

function of cognitive radio. In order to make use of the radio spectrum, CR has to

S. Gayathri (&) K.S. SujathaDepartment of ECE, Easwari Engineering College, Chennai, India

e-mail: [email protected]

K.S. Sujatha

e-mail: [email protected]

© Springer India 2016

L.P. Suresh and B.K. Panigrahi (eds.), Proceedings of the International

Conference on Soft Computing Systems, Advances in Intelligent Systems

and Computing 397, DOI 10.1007/978-81-322-2671-0_67

711


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continuously monitor the spectrum to identify whether spectrum is idle or busy.

This mechanism is known as spectrum sensing. Spectrum sensing symbolizes a

major role in cognitive radio systems because the other functions of CR depend on

spectrum sensing. Spectrum sensing has to execute two functions as follows; rst, it

has to detect the white space or unoccupied bands; and second, it has to continu-ously monitor the spectrum to sense the arrival of primary user during transmission.

Many spectrum sensing schemes were introduced which are as follows: energy

detection technique, coherent detection method, and cyclostationary feature

detection. These approaches are performed for local sensing. From the above

approaches, energy detection technique is known to be the easiest approach in

existence. The channel degradation caused by the shadowing and multipath effects

will arise the hidden terminal problem in local sensing. Henceforth, multinode

sensing (or) cooperative sensing helps us to manipulate this problem. It is of two

types namely centralized and distributed. In centralized cooperative sensingapproach, multiple secondary users will send either the one bit hard decision control

channel or energy statistics to the fusion centre which in turn decides whether the

band is occupied or not. In distributed approach, the cognitive radios will take their

own decision based on the sensing report from the neighbouring cognitive radios.

Both the hidden terminal problem and designing a hardware to perform wide band

sensing are the major design challenges in cognitive radio. Therefore, a recong-

urable architecture is proposed in this work to perform collaborative wideband

sensing to overcome this problem.

2 Related Works

The existing literature for wideband spectrum sensing for CR system is scarce or

little. A wavelet transform based spectrum sensing was introduced [1] which uses

wavelet transform to estimate power spectral density; however, it is not feasible in

real-time sensing. Thomson multitaper spectral estimation was proposed in [2] to

estimate PSD. Whereas, its dependency of eigenvalue decomposition, hardwarerealization of this method is impractical. In [3], spectral estimator based on FFT is

proposed where lter banks are used to convert the wideband into narrowband and

then PSD is estimated for each narrowband. This method turns out to be impractical

because of improper ltering.

In [4], a sensing processor for wideband is designed using multitaper windowed

frequency domain power detector. It has a drawback of partial realization in FPGA.

In [5], a cooperative spectrum sensing design is implemented in FPGA but it is

restricted for narrowband sensing. In this paper, a wideband has to be sensed

henceforth a recongurable architecture with multiple direct down converter

channelized cognitive radios for multinode detection is designed. The proposed

architecture is then implemented in FPGA and its area requirements are reported.

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3 System Architecture

This section proposes an architecture for cooperative spectrum sensing cognitive

radio for wideband sensing. As shown in Fig. 1, the cooperative sensing archi-tecture of a cognitive radio consists of two units. The two units are as follows:

Local detection unit and hard decision logic unit. Local detection unit performs

local sensing using energy detection method. Whereas in the hard decision logic

unit along with the local decision of the cognitive radio, local decision form

multiple cognitive radios is compared with the threshold and gives out the nal

sensing output.

3.1 Local Detection Unit

The proposed work is for wideband cooperative sensing; therefore, multiple CR

undergoes local sensing and computes a one bit decision control output. The local

detection unit in the proposed architecture consists of IF sampling wideband

receiver architecture with digital IQ baseband processing unit. The receiver archi-

tecture consists of RF front end and ADC block and IQ Digital down

converter-based channelizer. In the RF front end, bandpass sampling is done in

digital domain by a digital bandpass lter (antialising lter) and mixed with an LO

to produce the IF signal which is given to the ADC. The ADC performs samplingand gives out time domain samples, x k (nT s). Consider the received wideband signal

x (t ), is given as a input to RF front end and ADC block, where bandpass sampling is

done on the received signal. The bandpass sampled output is given as input to IO

digital down converted channelizer block [6], which gives out K subbands with

discrete time domain samples X k ¼ x k 1ð Þ; x k 2ð Þ; . . . x k N ð Þ where k ¼ 1; 2; . . .; k .The time domain samples are given as input to the local detection unit as shown in

Fig. 2. ADC cannot be realizable in FPGA and the time domain samples are

Final sensing output

Received signal

Local detection

unit

Hard decision

logic unit

Local detection

from CR1

Local detection

from CR2

Local detection

from CR3

Fig. 1 Proposed architecture

of cooperative spectrum

sensing cognitive radio

Design and Implementation of Recongurable VLSI Architecture … 713


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demultiplexed to K subbands. Further operation takes place as narrowband chan-

nelization process. The samples are given to K IQ digital down converters where

samples are divided into inphase components, I k (n) and quadrature components,

Qk (n) using a demultiplexer and followed by multiplying it with monobit multiplier

[7]. The computed samples undergo digital lowpass FIR ltering and digital

downsampling to decimate the sampling rate. The ltered samples are then squared

using a multipler. The squared inphase and quadrature samples are then added by

sum block and computes x k nð Þj j2

. Finally, the average of N samples is taken usingthe average FIR lter to take the mean of the sample which gives out the energy

statics of the signal in K subband,P N

n¼1 x k nð Þj j2. The test static, T k ( x k ) is comparedwith the derived threshold value, r k for p f = 0.1. The threshold r k for local detection

is obtained from the formula [8] as follows:

r k ¼ Q1 p f r

2v

ffiffiffiffiffiffi2 N

p N r2v

!

where P f is probability of false detection and N is number of samples. If the T k ( x k )exceeds the threshold then it sends binary value ‘1’ as a binary decision input to the

hard decision logic unit and binary value ‘0’ if T k ( x k ) is less than threshold (Fig. 3).

3.2 Hard Decision Logic Unit

In the hard decision logic, multiple CR with distributed approach is performed.

i.e., nal decision of the presence of primary user is taken after collaborativelyexchanging the local detection decision with each other. Multiple CR gives out

RF

front

end

&

ADC

Squaredevice

AddI&Q

K

subband

binarydecision

To

decision

logic

I2 k(n) &Q2k(n)x(nTs)x(t)

I(n) & Q(n) of

K subbands

IQ DDC

channelizer

Average

N samples

Fig. 2 Local detection unit

for a cognitive radio



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K subband local detection sensing results in the form of vector which is represented

as Y k ¼ T k ;1 1ð Þ; T k ;2 2ð Þ; . . .T k ;m N ð Þ. The 1 bit binary decision output for K subandsfrom local detection of M number of CRs are weighted and AND operation is

performed, i.e., Z k ¼Q M

i¼1 W T k ;iY k ;i. Z k is then compared with threshold, r

k . The

threshold, r k value is ‘1’ because of using hard decision AND logic. Finally, the

hard decision logic gives out ‘1’ if the primary user is present and if ‘0’ is obtained

then the band is identi

ed as free, i.e., the primary user is absent at the particular band. The binary decision for K subband from M CRs should be ‘0’ for further data

transmission by cognitive radio.

4 Results and Discussions

The RF front end of the receiver architecture is simulated in MATLAB. A 10 GHz

Wideband signal is modeled and bandpass ltering is done. The ltered signal is

then modulated with a carrier wave and given to ADC. The ADC computes time

domain samples. The discrete time domain samples computed from ADC sampling

is given as the input to the VHDL module of cooperative spectrum sensing.

The VHDL module has four local detection submodules meant for four Cognitive

radios, which gives it binary decision output after comparing it with the average

submodule output with the threshold. The threshold value used is based on P f = 0.1.

The binary decision is given to hard decision unit where the cooperative decision is

taken and a nal binary decision out is obtained. The simulation result of the

module of cooperative spectrum sensing is given in Fig. 4.

LPF

LPF

LPF

LPF

M

M

M

ADC

Mult

+1/-1

Mult

+1/-1

Mult+1/-1

Mult

+1/-1

M

Fig. 3 IQ digital down

converted channelization



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4.1 Implementation Results in Virtex Board

The proposed architecture is implemented in virtex-4 FPGA after simulating and

synthesizing it with Xilinx Isim 13.2 suite. The net list can then be generated and

downloaded in Virtex-4 FPGA kit. The design summary report of the implemen-

tation are given in Fig. 5 shows number of multipliers, look up table and slices has

been used. This summary report clearly points out that the proposed architecture

outperforms the other implementations by consuming less area and completely

realizable in FPGA.

5 Conclusion and Future Work

In this paper, a cooperative spectrum sensing scheme has been proposed for

wideband sensing cognitive radio. Thus the cooperative sensing method improves

the spectrum sensing performance over wide frequency range. Simultaneously, it

Fig. 4 Simulation result of wideband cooperative spectrum sensing cognitive radio

Fig. 5 Design summary report



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solves the hidden terminal problem in the cognitive radio network and it can be

easily implemented in FPGA.

In future, the work will be focused on optimizing the power consumed by the

architecture by applying low power techniques like clock gating, etc. and further-

more, replacing lters with multiplierless lters.

Acknowledgments The authors would like to thank Dr. K. Kathiravan for his valuable sug-

gestions to improve the quality of work.

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Design and Implementation of Reconfigurable VLSI Architecture for Optimized Performance Cognitive Radio Wideband Spectrum Sensing