Department of Electrical and Systems Engineering ESE 570

Department of Electrical and Systems EngineeringESE 570 Midterm Exam - SOLUTIONS

March 05, 2015

To maximize opportunity for partial credit, please show all work and provide units for all requestedparameters. Please note that there are a total of 3 problems. For full credit solve Problem 1 and eitherProblem 2 or Problem 3. Problem 1 is worth 60 points and Problems 2 and 3 are each worth 40 points.

Please be clear that I will only grade 2 exercises, Problem 1 and either Problem 2 or 3. If you elect to workall 3 problems, please clearly specify which 2 solutions you want graded. Otherwise I will grade Problem 1and the first of the two remaining solutions that appear in your exam book. Please use approximationswhere appropriate.

1. Consider the CMOS logic gate layout in Fig. P1 where the output F = f(A, B, C) and A, B, C are inputs. This

gate has been implemented in a 1mm n-well CMOS technology that is represented by the SPICE parameters in

Table 4 (page 5) of the “Formulas and Data” handout. The gate load capacitance CLOAD is comprised of only

internal (intrinsic) parasitic capacitances. The layouts in Fig. P1 show all the relevant dimensions. All nMOS

and pMOS transistors have the same dimensions, shown respectively in Figs. P1b and P1c.

Fig. P1

a). Sketch the schematic for the logic gate in Fig. P1. Determine the Boolean expression “F” for the gate, i.e.

F=f(A, B, C). Determine the values for VOH and VOL. (15pts)

b). Assume that all extrinsic parasitic capacitances associated with the layouts Fig. P1 are zero. List the intrinsic

parasitic capacitances that dominate the make-up of CLOAD

. Label the capacitors using subscripts that

indicate their source, e.g. for source-to-bulk nMOS use “sbn”. Draw them in the schematic sketched in part

a). (15pts)

c). Using the SPICE parameters in Table 4 (page 5) of the “Formulas and Data” handout. and the layout in Fig.

P1, estimate the values for the intrinsic parasitic capacitances identified in part b). In your estimates let the

voltage equivalence factors Keq = Keq(sw) = 0.5. (15pts).

d). Let the nMOS transistors be sized as shown in Fig. P1, redesign the pMOS transistors (if needed) to achieve a

switching threshold voltage Vth = 1.5 V. (15pts)

Department of Electrical and Systems EngineeringESE 570 Midterm Exam - SOLUTIONS

March 05, 2015

To maximize opportunity for partial credit, please show all work and provide units for all requestedparameters. Please note that there are a total of 3 problems. For full credit solve Problem 1 and eitherProblem 2 or Problem 3. Problem 1 is worth 60 points and Problems 2 and 3 are each worth 40 points.

Please be clear that I will only grade 2 exercises, Problem 1 and either Problem 2 or 3. If you elect to workall 3 problems, please clearly specify which 2 solutions you want graded. Otherwise I will grade Problem 1and the first of the two remaining solutions that appear in your exam book. Please use approximationswhere appropriate.

1. Consider the CMOS logic gate layout in Fig. P1 where the output F = f(A, B, C) and A, B, C are inputs. This

gate has been implemented in a 1mm n-well CMOS technology that is represented by the SPICE parameters in

Table 4 (page 5) of the “Formulas and Data” handout. The gate load capacitance CLOAD is comprised of only

internal (intrinsic) parasitic capacitances. The layouts in Fig. P1 show all the relevant dimensions. All nMOS

and pMOS transistors have the same dimensions, shown respectively in Figs. P1b and P1c.

Fig. P1

a). Sketch the schematic for the logic gate in Fig. P1. Determine the Boolean expression “F” for the gate, i.e.

F=f(A, B, C). Determine the values for VOH and VOL. (15pts)

b). Assume that all extrinsic parasitic capacitances associated with the layouts Fig. P1 are zero. List the intrinsic

parasitic capacitances that dominate the make-up of CLOAD

. Label the capacitors using subscripts that

indicate their source, e.g. for source-to-bulk nMOS use “sbn”. Draw them in the schematic sketched in part

a). (15pts)

c). Using the SPICE parameters in Table 4 (page 5) of the “Formulas and Data” handout. and the layout in Fig.

P1, estimate the values for the intrinsic parasitic capacitances identified in part b). In your estimates let the

voltage equivalence factors Keq = Keq(sw) = 0.5. (15pts).

d). Let the nMOS transistors be sized as shown in Fig. P1, redesign the pMOS transistors (if needed) to achieve a

switching threshold voltage Vth = 1.5 V. (15pts)

2

SOLUTION:

3

4

2. Fig. P2 shows a two-transistor MOS “circuit” fabricated on a VLSI test-site where the SPICE parameters for

the transistors are given in Table 4 (pages 5 and 6) of the “Formulas and Data” handout with the exception that

LAMBDA = 0. The transistors are externally biased with the voltages VG1 and VD2 shown in Fig. P3 and and VD1

and ID are measured voltage and current, respectively.

a). Determine the mode of operation of M1 and calculate the value of (W/L)1 that sets the drain current ID

= 0.3

mA with VD1

= V2

= 2 V. (15pts)

b). Determine the transistor threshold voltage and mode of operation for M2. (15pts)

c). Determine the value for the bias voltage V3 of M2. (10pts)

SOLUTION:

a). V DS1=V 2=2V and VGS1=V 1=3V ⇒VGS1−VT0=3.0V−0.5V=2.5V

Since V DS1=2VVGS1−V T0=2.5V ⇒M1linear

I D=0.3mA=KP

2W

L1

[2 V GS1−VT0V DS1−V DS1

2 ]=8.5 x 10

−5A/V 2

2W

L

1

[2 2.5V 2V−4V2]

Solving for W

L1

=2 0.3 x10

−3

8.5 x10−5

1

6=1.18

b). Since V DS2=VGS2 by connection V DS2VGS2−V T2⇒M2 saturation4

Since V SB2=V 2−0V=2V ≠0V ⇒V T2≠V T0

i.e. VT2=VT0GAMMA∣−PHIV SB2∣−∣PHI∣

where PHI=−0.74V and GAMMA=0.48V

5

V T2=0.5V0.48V ∣−−0.74V 2V∣−∣−0.74V∣=0.88V

c). Since M2 is in saturation and VGS2=V DS2

I D=0.3mA=KP

2W

L2

V GS2−V T22=KP

2W

L

2

V DS2−V T22

Solving for V DS2

V DS2=VT22 I D

KP W

L

2

=0.88V 2 0.3 x10−3A

8.5 x10−5A/V 23

=0.88V1.43V=2.41V

Note V S2=V D1=2V

V DS2=V D2−V S2=V 3−V 2 ⇒V 3=V DS2V 2=2.41V2V=4.41V

3. An MOS transistor has been fabricated in a CMOS technology similar to that represented by the SPICE

parameters in Table 4 (page 5) of the “Formulas and Data” handout with the exception of VT0 and

LAMBDA which will be determined in part (b). The terminal voltages and currents are shown in Figure P3

and Table P3.

Fig. P3 Table P3

a) Is the MOS transistor in Figure P3 an nMOS or pMOS? Please explain your answer. (10pts)

b) Let the nMOS transistor be biased by the terminal voltages shown in Figure P3 and Table P3. Using these

current-voltage conditions and the SPICE parameters in Table 4 (page 5) of the “Formulas and Data” handout,

determine the values (with units) for VT0 and LAMBDA. (10pts)

c) Determine the transistor's mode of operation (cutoff, linear or saturation) for each of the three sets of I-V data

in Table P3. (10pts)

d) Determine the (W/L) for the transistor in Figure P3. (10pts)

SOLUTION:

a)

6

Let’s initially assume the MOS transistor is pMOS; then V1 is at the source and V3 is at the drain.

For Row 1 V GSp 1=V 4−V 1=−1V => which implies the pMOS can be conducting with ID=109.4 A

For Row 2 V GSp 2=V 4−V 1=0V => which implies the pMOS is cutoff ID=0 ≠ 437.8 A

ID=0 ≠ 437.8 A => MOS transistor is NOT pMOS.

Assume the MOS transistor is nMOS; then V3 is at the source and V1 is at the drain.

For Row 1 V GSn 1=V 4−V 3=2V => which implies the nMOS is likely conducting with ID=109.4 A



=> MOS transistor is nMOS.

b)

kn

2(VGSn1−VT 0n)

2(1+LAMBDA⋅V DSn1)

k n

2(V

GSn2−VT 0

n)2(1+LAMBDA⋅V

DSn2)

=(V GSn1−VT 0n)

2

(V GSn2−VT 0n)2=109.4

437.8⇒

2V−VT 0n

3V −VT 0n=√

109.4

437.8=0.6

2V−VT 0n

3V−VT 0n=0.6⇒2V−VT 0n=1.8V−0.6VT 0n⇒0.2V=0.4VT 0n⇒VT 0n=0.5V

For Rows 1 and 3 VGSn1=VGSn3 and V DSn1≠V DSn3

k n

2(VGSn1−VT 0n)

2(1+ LAMBDA⋅V DSn1)

k n

2(V

GSn3−VT 0

n)2(1+ LAMBDA⋅V

DSn3)

=1+LAMBDA⋅VDSn 1

1+LAMBDA⋅VDSn 3

=109.4

110.5=0.99

1LAMBDA⋅3V

1LAMBDA⋅4V=0.99⇒ 1LAMBDA⋅3V=0.99LAMBDA⋅3.96V ⇒LAMBDA⋅0.96V=0.01

⇒LAMBDA=0.01

0.96V=0.0101V

−1

c) Note that LAMBDA≠0

For Row 1 VGDn=V4−V1=−1VVT0n⇒ saturation ; also V DSn=V1−V3=3V

For Row 2 VGDn=V4−V1=0VVT0n⇒ saturation ; also V DSn=V1−V3=3V

For Row 3 VGDn=V4−V1=−1VVT0n⇒ saturation ; also V DSn=V1−V3=4V

d) Determine the (W/L) for the transistor in Figure P3.

7

Select any of the three rows, say Row 1: kn

2V GSn1−VT0n

21LAMBDA⋅V DSn1=109. 4 A

k n=2109.4 A

V GS1n−VT0n 2 1LAMBDAnV DS1n

=2 109.4 A

1V 210.01V−1

3V =212.43

A

V2 =>

W /Ln=212.43 AKPn

=212.43 A/V 2

8.5E−5 A/V 2= 2.5

Department of Electrical and Systems EngineeringESE 570 Midterm Exam

March 06, 2014

To maximize opportunity for partial credit, please show all work and provide units for all requested parameters. Please note that there are a total of 3 problems. For full credit solve Problem 1 and either Problem 2 or Problem 3. Problem 1 is worth 60 points and Problems 2 and 3 are each worth 40 points.

Please be clear that I will only grade 2 exercises, Problem 1 and either Problem 2 or 3. If you elect to work all 3 problems, please clearly specify which 2 solutions you want graded. Otherwise I will grade Problem 1 and the first of the two remaining solutions that appear in your exam book.

1. Consider the inverter layout in Fig. P1, where L n = Lp = Lmin = 1 µm by design rules. Let the SPICE parameters be those in Table 4 (pages 5 and 6) of the “Formulas and Data” handout, with the exception that GAMMA = LAMBDA = 0. The inverter load capacitance CLOAD is comprised of internal (intrinsic) and external (extrinsic) parasitic capacitances. The layout in Fig. P1 includes all the relevant dimensions, except for Wn and Wp which are to be determined in part b.

a. Derive the design relationship that enables the designer to determine the ratio W p/Wn to realize a specified

VOL; i.e derive that W p

W n=2.0VOL−0.4VOL

2 , where VOL < VT0n. (20 pts)

b. Let the load capacitance CLOAD = 10 fF. Design the inverter to realize a propagation delay t PHL = 0.02 ns and VOL = 0.4 V (when Vin = VDD), i.e. determine values for Wp and Wn. You may assume that the nMOS driver transistor is dominant and in saturation during the Vout fall from VDD to VDD/2. (20 pts)

c. Using the SPICE parameters in Table 4 (page 5) of the “Formulas and Data” handout and the layout in Fig. 1 with Wn = 2.8 µm and Wp = 1.6 µm, estimate the values for the drain-to-bulk parasitic capacitances associated with CLOAD. In your estimates let the voltage equivalence factors Keq = Keq(sw) = 0.5 . (20 pts)

2. The circuit in Fig. P1 is a pMOS circuit where both transistors are enhancement mode pMOS with SPICE parameters given in Table 4 (pages 5 and 6) of the “Formulas and Data” handout, with the exception LAMBDA = 0. The current IX = 0.25mA and both transistors are biased with the voltages (all with respect to ground) shown in the schematic.

a. Determine the transistor threshold voltages for transistors M1 and M2. Assume V Y < 4V. (10 pts)

b. Determine the mode of operation of M2 and calculate the value of (W/L) 2 that sets IX = 0.25mA. (10 pts)

c. With 0V ≤ VY < 4V, determine the range for VY such that M1 is operating in the saturation mode. (10 pts)

d. With VY = 1V, determine the value of (W/L)1 for IX = 0.25mA. (10 pts)

3. Consider the inverter in Fig. P3. Let the SPICE parameters be those in Table 4 (pages 5 and 6) of the “Formulas and Data” handout, with the exception that LAMBDA = 0.

Fig. P3

a. Design the inverter circuit, i.e. determine the value of k nRL to achieve a noise margin NMH = 1 V. You may

use the following equation V out V in=V IH = 23V DD

kn RL. (30 pts)

b. Complete the design of the inverter circuit started in (a) to also realize a static power dissipation of 100 µW, i.e. determine the values for (W/L)n and RL (assume that the output voltage Vout = “1” during 50% of the operation time and Vout = “0” during the remaining 50%). Assume VOL = 0.1V. (10 pts)

1


March 06, 2014SOLUTIONS



1. Consider the inverter layout in Fig. P1, where L n = Lp = Lmin = 1 µm by design rules. Let the SPICE parameters be those in Table 4 (pages 5 and 6) of the “Formulas and Data” handout, with the exception that GAMMA = LAMBDA = 0. The inverter load capacitance CLOAD is comprised of internal (intrinsic) and external (extrinsic) parasitic capacitances. The layout in Fig. P1 includes all the relevant dimensions, except for Wn and Wp which are to be determined in part b.



W n=2.0VOL−0.4VOL



c. Using the SPICE parameters in Table 4 (page 5) of the “Formulas and Data” handout and the layout in Fig. 1 with Wn = 2.8 µm and Wp = 1.6 µm, estimate the values for the drain-to-bulk parasitic capacitances associated with CLOAD. In your estimates let the voltage equivalence factors Keq = Keq(sw) = 0.5 . (20 pts)

2

SOLUTION:



W n=2.0VOL−0.4VOL


The schematic for the layout in Fig. P1 is

VGSn = Vin = 3V >VT0n and VDSn = Vout = VOL < VGSn – VT0n = 3V – 0.5 V = 2.5V => nMOS is linear.

VGSp = - VDD = - 3V < VT0p and VDSp = VOL – VDD = 0.4V – 3V = - 2.6V < VGSp – VT0p = - 3V - (- 0.5V) = - 2.5V => pMOS is saturation.

KPp2

-W p

Lp.-−V DD−VT0p .

2=KPn

2-W n

Ln.[2-V DD−VT0n.VOL−VOL

2 ]

where Ln = Lp = 1 um, VT0n = - VT0p = 0.5V, KPn = 8.5 x 10-5 V/A2 and KPp = 3.4 x 10-5 V/A2

3.4 x10−5V / A2

2-W p

Lp. -−3V−-−0.5V ..2=

8.5 x 10−5V / A2

2-W n

Ln. [2 -3V−0.5V .V OL−VOL

2 ]

or 3.4 x10−5V / A2

2-W p

Lp. -−2.5V.2= 8.5 x10−5V / A2

2-W n

Ln.[2 -2.5V .V OL−V OL

2 ]

Solving for the ratio Wp/Wn

W p

W n=8.5

3.41

-−2.5V .2[5.0VOL−V OL

2 ]=2.0VOL−0.4VOL2


3

C LOADd V out

d t≈−i Dn⇒dt=C LOAD-

−d V out

i Dn. where iDn=

KPn2

-W n

Ln.-V DD−VT0n .

2

1PHL=∫t=t0t=t1

'

dt≈−CLOAD

KPn2

-W n

Ln. -V DD−V T0n.

2∫V out=V DD

V out=0.5V DD

dVout=2CLOAD -0.5V DD.

KPn-W n

Ln.-V DD−V T0n.

2

-Wn

Ln.=

2CLOAD -0.5V DD.

1PHL KPn -V DD−V T0n.2=

2 -1 x 10−14F .-0.5 x 3.V 2

0.02 x 10−9 s-8.5 x 10−5A/V 2. -3−0.5.2V 2 = 2.82 => Wn = 2.82 µm

Using W p

W n=

8.53.4

1-−2.5V .2

[5.0VOL−V OL2 ]=2.0VOL−0.4VOL

2 with VOL = 0.3V

W p

W n=2.0VOL−0.4VOL

2 =0.600−0.036=0.564

From part (a) W p

W n=0.564⇒W p=0.564W n=1.580m

c. Using the SPICE parameters in Table 4 (page 5) of the “Formulas and Data” handout and the layout in Fig. P1

with Wn = 2.8 µm and Wp = 1.6 µm, estimate the values for the drain-to-bulk parasitic capacitances associated with CLOAD. In your estimates let the voltage equivalence factors Keq = Keq(sw) = 0.5 . (20 pts)

MOS: W n=2.820m , XJ=0.20m , Y=1.50m pMOS: W p=1.580m , XJ=0.20m , Y=1.50m

ADn=W⋅XJ+W⋅Y=-2.82E−6 .⋅-2.0E−7 .+-2.82E−6.⋅-1.5 E−6 . .=0.564 E−12+4.23E−12=4.794E−12m2

PDn=W+2Y=2.82 E−6+2⋅1.5 E−6=5.82E−6m

Cdbn=ADn⋅CJn⋅Keqn+PDnn⋅CJSW n⋅Keqn-sw . .=-4.794 E−12m2.⋅-3.0E−4F /m2 .⋅0.5+-5.82 E−6m .⋅-4.0E−10F /m .⋅0.5=0.719 fF+1.16 fF=1.879 fF

Cdbp=ADp⋅CJ p⋅K eqp+PDp⋅CJSW p⋅K eqp -sw .

AD p=W⋅XJ+W⋅Y=-1.58E−6.⋅-0.2E−6.+-1.58 E−6.⋅-1.5 E−6. .=0.316 E−12+2.370 E−12=2.686 E−12m2

PDp=W+2Y=1.58E−6+2⋅1.5E−6=4.58E−6m

Cdbp=AD p⋅CJ p⋅K eqn+PDp⋅CJSW p⋅Keqn-sw . .=-2.686 E−12m2.⋅-3.0E−4F /m2 .⋅0.5+-4.58E−6m.⋅-4.0 E−10F /m .⋅0.5=0.403 fF+0.916 fF=1.319 fF

4

2. The circuit in Fig. P2 is a pMOS circuit where both transistors are enhancement mode pMOS with SPICE parameters given in Table 4 (pages 5 and 6) of the “Formulas and Data” handout, with the exception LAMBDA = 0. The current IX = 0.25mA and both transistors are biased with the voltages (all with respect to ground) shown in the schematic.

a. Determine the transistor threshold voltages for transistors M1 and M2. Assume V Y < 4V. (10 pts)

b. Determine the mode of operation of M2 and calculate the value of (W/L) 2 that sets IX = 0.25mA. (10 pts)

c. With 0V ≤ VY < 4V, determine the range for VY such that M1 is operating in the saturation mode. (10 pts)

d. With VY = 1V, determine the value of (W/L)1 for IX = 0.25mA. (10 pts)

SOLUTION:

a. M2: Since VSB2 = 0V, VT = VT0p = -0.5 V

M1: Since VSB1 = 4V – 5V = -1V ≠ 0V VT1=VT0p+GAMMA-,∣−PHI+V SB1∣−,∣−PHI∣.

where PHI=0.77V and GAMMA=−0.69,V

V T1=−0.5V−0.69,V -,∣−-0.77V .+-−1V .∣−,∣0.77V∣.=−0.812V b. Since VGS2 = 0V – 5V = - 5V < VT0p = - 0.5 and VDS2 = 4 V – 5V = -1 V > VGS2 – VT0p = -4.5 V,

M2 is in the Linear Mode.

I X=0.25mA= KP2

-WL.

2[2 -VGS2−VT0p.V DS2−V DS2

2 ]

With KP = 3.4 x 10-5 A/V2 and VT0p = - 0.5V

.=3.4 x10−5 A/V 2

2-WL.

2[2-−4.5V . -−1V .−-−1V .2]= 3.4 x10−5A/V 2

2-WL.

2[8V ]=0.25 x10−3A

Solving for -WL.

2=

2 -0.25 x10−3 .3.4 x 10−5

18=1.84

5

c. With 0V ≤ VY < 4V, determine the range for VY such that M1 is operating in the saturation mode.

VGS1 = 1V – VX = 1V – 4V = -3V and VDS1 = VY – VX = VY – 4V.

For Saturation Mode: VDS1 < VGS1 – VT1

VDS1 = VY – 4V < VGS1 – VT1 = - 3V - (- 0.812V) = - 2.188 V => VY – 4V < - 2.188 V

or 0 ≤ VY < - 2.188V + 4V = 1.812 V

d. With VY = 1 V, determine the value of (W/L)1 that sets IX = 0.25 mA.

I X=0.25mA= KP2

-WL.

1-V GS1−V T1.

2=3.4 x 10−5A/V 2

2-WL.1-−3V−-−0.812V ..2

Solving for -WL.

1= 2 -0.25 x 10−3.

3.4 x 10−51

4.79=3.07

3. Consider the inverter in Fig. P3. Let the SPICE parameters be those in Table 4 (pages 5 and 6) of the “Formulas and Data” handout, with the exception that LAMBDA = 0.

6

Fig. P3

a. Design the inverter circuit, i.e. determine the value of knRL to achieve a noise margin NMH = 1 V.

You may use the following equation V out -V in=V IH .=, 23V DD

kn RL. (30 pts)

b. Complete the design of the inverter circuit started in (a) to also realize a static power dissipation of 100 µW, i.e. determine the values for kn and RL (assume that the output voltage Vout = “1” during 50% of the operation time and Vout = “0” during the remaining 50%). Assume VOL = 0.1V.

(10 pts)

SOLUTION: a. VDD = 3V and the transistor parameters are KP = 34 mA/V2 and VT0 = 0.5 V, determine the (W/L) n RL in

Fig. P3 to achieve a NMH = 1 V with V out -V in=V IH .=, 23V DD

kn RL.

MNH = VOH – VIH = 3V – VIH = 1V => VIH = 2 V

VIH: d V out

d V in=−1@V in=V IH and the nMOS is in linear mode

V DD−V out

RL=k n2[ -2V in−VT0n.Vout−V out

2 ]

Differentiate wrt to Vin and set d V out

d V in=−1 and V in=V IH :

−1RL

d V out

d V in=k n2[2-V in−VT0n.

d V out

d V in+2V out−2V out

d V out

d V in]

1RL

=k n2[−2 -V IH−VT0n.+2V out+2V out ]

Solving for VIH:

V IH=VT0n+2V out−1k n RL

where V out -V in=V IH .=, 23V DD

kn RL

7

V IH=VT0n+2, 23V DD

k n RL− 1k n RL =>

1.5V=, 8kn RL

− 1kn RL

letting x=1k nRL

=> 1.5V=,8 x−x or -1.5V+x .2=8x => x 2−5x+2.25=0

factoring: -x−0.5V . -x−4.5V .=0

Solving for x: x= 1kn RL

=0.5V , 4.5V

To determine the correct value of x we need to evaluate Vout for both values of x, i.e.

using V out -V in=V IH .=, 23V DD

kn RLand x= 1

k n RL=0.5V , 4.5V

x = 0.5 V: V out -V in=V IH .=, 23-3V⋅0.5V.=1V

x = 4.5 V: = V out -V in=V IH .=, 23-3V⋅4.5V.=3V=VDD > x= 1

kn RL=0.5V or k n RL=2V−1

(b) Use static power dissipation of 100 µW spec to separate kn = KPn (W/L)n from RL, i.e.

1000W=V DD

2V DD−VOL

RL=1.5V 2.9V

RL⇒RL=-1.5.-2.9. V 2

1x10−4=43.5 k/

x= 1k nRL

=0.5V => k n=2V−1

RL= 2

0.43x105 V−1 IV=46.50 A/V 2


March 14, 2013

To maximize opportunity for partial credit, please show all work and provide units for all requested parameters. Please note that there are a total of 3 exercises. For full credit solve Exercise 1 and either Exercise 2 or Exercise 3. Each exercise is worth 50 points.

Please be clear that I will only grade 2 exercises, Exercise 1 and either Exercise 2 or 3. If you elect to work all 3 exercises, please clearly specify which 2 solutions you want graded. Otherwise I will grade Exercise 1 and the first of the two remaining solutions that appear in your exam book.

1. Consider the CMOS logic gate layout in Fig. P1 where the output F = f(A, B, C, D) and A, B, C, D are inputs. This gate has been implemented in a 1µm n-well CMOS technology that is represented by the SPICE parameters in Table 4 (page 5) of the “Formulas and Data” handout. The logic gate load capacitance C LOAD is comprised of only internal (intrinsic) parasitic capacitances. The layout in Fig. P1 includes all the relevant dimensions. All nMOS and pMOS transistors have the same dimensions shown respectively in Fig. P1b and c.

a. Sketch the schematic for the logic gate. Determine the Boolean expression for the gate, i.e. F = f(A, B, C, D).

(10pts)

b. Let all inputs (A, C, C, D) switch instantaneously from 0 V→ DD or VDD → 0. Draw the equivalent inverter for the gate and determine the WnEQV and WpEQV in terms of the Wn and Wp for the gate's individual transistors (Figs P2b and c). Assume that LAMBDA = 0 and GAMMA = 0 for all transistors. (10pts)

c. With all the inputs switching simultaneously, as described in part b above, determine the value for W p that realizes a switching threshold voltage Vth = 1.5 V for the gate; where Wn ≥ 1.5 µm and Wp ≥ 1.5 µm. Assume that LAMBDA = 0 and GAMMA = 0 for all transistors. (10pts)

d. Let all overlap and interconnect capacitances be zero and let the output of the logic gate in Fig. 1 have a fan-out = 0. Using the SPICE parameters in Table 4 (page 5) of the “Formulas and Data” handout. and the layout in Fig. 1, estimate the values for the drain-to-bulk C db parasitic capacitances associated with C LOAD. In your estimates let the voltage equivalence factors Keq = Keq(sw) = 0.5 . (15pts)

e. Determine the input condition (i.e. which inputs are set high or low or switching) for worst-case pull-up (or τPLH). State your reason(s) for your answer. (15pts)

Fig. P1

2

2. Consider the CMOS gate in Fig. P2, where LAMBDA = 0 for all transistors.

a. Sketch the schematic for the logic gate. Determine the Boolean expression for the gate, i.e. F = f(A, B, C,). (10pts)

b. Draw the equivalent inverters for the gate and determine the W nEQV and WpEQV in terms of the Wn and Wp for the gate's individual transistors (Figs P2b and c) for the input patterns (i) {A, B, C} = {1, 1, 1} and (ii) {A, B, C} = {0, 1, 1}. Assume that LAMBDA = 0 and GAMMA = 0 for all transistors. (10pts)

c. Letting Ln = Lp = 1 µm, determine the values for the Wn, Wp to realize VOL ≤0.25V for all input conditions; where Wn ≥ 1.5 µm and Wp ≥ 1.5 µm. Use the SPICE parameters in Table 4 (page 5) of the “Formulas and Data” handout. Assume that LAMBDA = 0 and GAMMA = 0 for all transistors. (20pts)

3. Fig. P3 shows a two-transistor MOS “circuit” fabricated on a VLSI test-site where the SPICE parameters for the transistors are given in Table 4 (pages 5 and 6) of the “Formulas and Data” handout with the exception that LAMBDA = 0. The transistors are externally biased with the voltages V G1 and VD2 shown in Fig. P3 and and VD1 and ID are measured voltage and current, respectively.

a. Determine the mode of operation of M1 and calculate the value of (W/L) 1 that sets the drain current ID = 0.26 mA with VD1 = 2 V. (15pts)

b. Determine the transistor threshold voltage and mode of operation for M2. (10pts)

c. Determine the value for the bias voltage VD2 of M2. (15pts)

Fig. P2


March 14, 2013Solutions



1. Consider the CMOS logic gate layout in Fig. P1 where the output F = f(A, B, C, D) and A, B, C, D are inputs. This gate has been implemented in a 1µm n-well CMOS technology that is represented by the SPICE parameters in Table 4 (page 5) of the “Formulas and Data” handout. The logic gate load capacitance C LOAD is comprised of only internal (intrinsic) parasitic capacitances. The layout in Fig. P1 includes all the relevant dimensions. All nMOS and pMOS transistors have the same dimensions shown respectively in Fig. P1b & c.

Solution:

a. Sketch the schematic for the logic gate. Determine the Boolean expression for the gate, i.e. F = f(A, B, C, D). (10pts)

b. Let all inputs (A, C, C, D) switch instantaneously from 0 V→ DD or VDD → 0. Draw the equivalent inverter for the gate and determine the WnEQV and WpEQV in terms of the Wn and Wp for the gate's individual transistors (Figs P2b and c). Assume that LAMBDA = 0 and GAMMA = 0 for all transistors. (10pts)

c. With all the inputs switching simultaneously, as described in part b above, determine the value for W p that realizes a switching threshold voltage Vth = 1.5 V for the gate; where Wn ≥ 1.5 µm and Wp ≥ 1.5 µm. Assume that LAMBDA = 0 and GAMMA = 0 for all transistors. (10pts)

d. Let all overlap and interconnect capacitances be zero and let the output of the logic gate in Fig. P1 have a fan-out = 0. Using the SPICE parameters in Table 4 (page 5) of the “Formulas and Data” handout. and the layout in Fig. P1, estimate the values for the drain-to-bulk C db parasitic capacitances associated with CLOAD. In your estimates let the voltage equivalence factors Keq = Keq(sw) = 0.5 . (15pts)

e. Determine the input condition (i.e. which inputs are set high or low or switching) for worst-case pull-up (or τPLH). State your reason(s) for your answer. (15pts)

Fig. 1

2Solution:a.

F=ABC ⋅D

b.

k nEQV=3kn∥kn=34kn⇒W nEQV=

34Wn

k pEQV=k p∥k p∥k pk p3k p=

43k p⇒W pEQV=

43W p

c. The gate is symmetric, i.e. VT0n = |VT0p| and V th = VDD/2. Hence, using the equivalent inverter, this

symmetry implies that k REQV=1⇒k pEQV=k pEQV⇒W pEQV=KPnKPp

W nEQV=8.53.4W nEQV=2.5W nEQV

Since, 43W p=

2.5⋅34W n⇒W p=

2.5⋅916

W n

Hence, with W n=1.5m then W p=1.406W n=2.11m1.5m

d. nMOS: W n=1.5m , XJ=0.2m , Y=1.5m pMOS: W p=2.11m , XJ=0.2m , Y=1.5m

ADn=W⋅XJW⋅Y=1.5E−6⋅2.0E−71.5E−6⋅1.5E−6 .=0.3 E−122.25E−12=2.55 E−12m2

PDn=W2Y=1.5E−62⋅1.5E−6=4.5E−6m

F

V DD

D

C

A

B

C

BA

D

s

s

s s

s

s s s

d

d

d

d

d

d d d

k pEQV

k nEQV

W pEQV

L p

W nEQV

Ln

3

Cdbn=ADn⋅CJn⋅KeqnPDnn⋅CJSW n⋅Keqn sw .=2.55 E−12m2 ⋅3.0E−4F /m2⋅0.54.5E−6m ⋅4.0E−10 F /m⋅0.5=0.38 fF0.9 fF=1.28 fF

Cdbp=ADp⋅CJ p⋅K eqpPDp⋅CJSW p⋅K eqpsw

AD p=W⋅XJW⋅Y=2.11 E−6⋅0.2E−62.11E−6⋅1.5 E−6 .=0.422 E−123.165 E−12=3.59E−12m2

PDp=W2Y=2.11 E−62⋅1.5E−6=5.11E−6m

Cdbp=AD p⋅CJ p⋅K eqnPDp⋅CJSW p⋅Keqnsw .=3.59E−12m2⋅3.0 E−4F /m2⋅0.55.11E−6m⋅4.0E−10F /m⋅0.5=0.54 fF1.02 fF=1.56 fF

e. The worst case input condition for τPLH is the condition that maximizes the effective pull-up resistance and maximizes the effective CLOAD. This arrises when inputs A = B = 0, D = 1 and C switching from VDD → 0.

This selection combines the three pMOS (A, B, C) in series such that the estimated effective on resistance is R EFF

= 3Rp.

This selection forces parasitic capacitances at the drains pMOS (A, B, C, D) and parasitic capacitances at the drains nMOS (A, B, C, D) to the output – maximizing C LOAD.

2. Consider the CMOS gate in Fig. P2, where LAMBDA = 0 for all transistors.

a. Draw the schematic for the logic gate. Determine the Boolean expression for the gate, i.e. F = f(A, B, C,). (10pts)

Fig. P2

4

b. Draw the equivalent inverters for the gate and determine the W nEQV and WpEQV in terms of the Wn and Wp for the gate's individual transistors (Figs P2b and c) for the input patterns (i) {A, B, C} = {1, 1, 1} and (ii) {A, B, C} = {0, 1, 1}. Assume that LAMBDA = 0 and GAMMA = 0 for all transistors. (10pts)

c. Letting Ln = Lp = 1 µm, determine the values for the Wn, Wp to realize VOL ≤0.25V for all input conditions; where Wn ≥ 1.5 µm and Wp ≥ 1.5 µm. Use the SPICE parameters in Table 4 (page 5) of the “Formulas and Data” handout. Assume that LAMBDA = 0 and GAMMA = 0 for all transistors. (20pts)

Solution:a.

F=AB ⋅C

b.

i. {A, B, C} = {1, 1, 1}: k pEQV=k p⇒W pEQV=W p and k nEQV=23k p⇒W nEQV=

23Wn

ii. {A, B, C} = {0, 1, 1}: k pEQV=k p⇒W pEQV=W p and k nEQV=12k p⇒W nEQV=

12Wn

c. Use the equivalent inverter with the worst-case input pattern, i.e. {A, B, C} = {0, 1, 1} where

k pEQV=k p⇒W pEQV=W p and k nEQV=12k p⇒WnEQV=

12Wn ; also Ln=L p=1.0m

For Vin = VDD = 3V and VOL ≤ 0.25V

VGSn = Vin = 3V >VT0n and VDSn = Vout = VOL = 0.25V < VGSn – VT0n = 3V – 0.5 V = 2.5V => nMOS is linear.

VGSp = - VDD = - 3V < VT0p and VDSp = VOL – VDD = 0.25V – 3V = - 2.75V < VGSp – VT0p = - 3V - (- 0.5V) = - 2.5V => pMOS is saturation.

KPp2

W pEQV

L p −V DD−VT0p

2=KPn2

W nEQV

Ln[2V DD−VT0nV OL−V OL

2 ]

5

where Ln = Lp = 1 um, VT0n = - VT0p = 0.5V, KPn = 8.5 x 10-5 V/A2 and KPp = 3.4 x 10-5 V/A2

3.4 x10−5V /A2

2W pEQV

L p −3V−−0.5V 2=

8.5 x10−5V /A2

2W nEQV

Ln [2 3V−0.5VVOL−VOL

2 ]

or

3.4 x10−5V /A2

2W pEQV

L p −2.5V2=

8.5 x10−5V /A2

2W nEQV

Ln[22.5VVOL−VOL

2 ]

Solving for the ratio WpEQV/WnEQV

W pEQV

W nEQV=

8.53.4

1−2.5V 2

[5.0V OL−V OL2 ]=2.0V OL−0.4V OL

2

VOL = 0.25 V => W pEQV

W nEQV=W p

W nEQV=2.0VOL−0.4V OL

2 =0.475

W p=0.475W nEQV=0.475 12W n=0.238W n1.5m

Let W p=1.5m => Wn=W p

0.238=

1.5m0.238

=6.302m

3. Fig. P3 shows a two-transistor MOS “circuit” fabricated on a VLSI test-site where the SPICE parameters for the transistors are given in Table 4 (pages 5 and 6) of the “Formulas and Data” handout with the exception that LAMBDA = 0. The transistors are externally biased with the voltages V G1 and VD2 shown in Fig. P3 and and VD1 and ID are measured voltage and current, respectively.

a. Determine the mode of operation of M1 and calculate the value of (W/L) 1 that sets the drain current ID = 0.26 mA with VD1 = 2 V. (15pts)

b. Determine the transistor threshold voltage and mode of operation for M2. (10pts)

c. Determine the value for the bias voltage VD2 of M2. (15pts)

6Solution:

a. V DS1=V D1=2V and VGS1=VG1=3V ⇒VGS1−VT0=3.0V−0.5V=2.5V

Since V DS1=2VVGS1−V T0=2.5V ⇒M1linear

I D=0.26mA= KP2

WL1[2 VGS1−VT0 V DS1−V DS1

2 ]=8.5 x 10−5 A/V 2

2WL1[2 2.5V 2V−4V 2]

Solving for WL1=2 0.26 x10−3

8.5 x10−516=1.02

b. Since V DS2=VGS2 by connection V DS2VGS2−V T2⇒M2 saturation

Since V SB2=V D1−0V=2V ≠0V⇒V T2≠V T0

i.e. VT2=VT0GAMMA∣−PHIV SB2∣−∣PHI∣

where PHI=−0.74V and GAMMA=0.48V

V T2=0.5V0.48V ∣−−0.74V 2V∣−∣−0.74V∣=0.88V

c. Since M2 is in saturation and VGS2=V DS2

I D=0.26mA= KP2

WL

2VGS2−V T2

2=KP2

WL2V DS2−V T2

2

Solving for V DS2

V DS2=VT2 2 I D

KP WL 2

=0.88V 20.26 x 10−3 A8.5 x10−5 A/V 2 3

=0.88V1.43V=2.31V

Note V S2=V D1=2VV DS2=V D2−V S2⇒V D2=V DS2V S2=2.31V2V=4.31V

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Department of Electrical and Systems Engineering ESE 570