Lecture Outline ESE 570: Digital Integrated Circuits and VLSI ...ese570/spring2019/handouts/...Q=CV= ∫I(t)dt € E=CV dd 2 Capacitor charging energy Penn ESE 570 Spring 2019 - Khanna

1

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

Lec 10: February 19, 2019 MOS Inverter: Dynamic Characteristics

Penn ESE 570 Spring 2019 – Khanna

Lecture Outline

!  Inverter Power !  Dynamic Characteristics

"  Delay

2 Penn ESE 570 Spring 2019 – Khanna

Inverter Power


Power

!  P = I×V

!  Tricky part: "  Understanding I "  (pairing with correct V)


Static Current

!  P = Istatic×VDD

!  Static current determined by subthreshold current


Switching Currents

!  Dynamic current flow:

!  If both transistor on: "  Current path from Vdd

to Gnd "  Short circuit current


2

Switching

Dynamic Power

7 Penn ESE 570 Spring 2019 - Khanna

Switching Currents

!  Itotal(t) = Istatic(t)+Iswitch(t)

!  Iswitch(t) = Isc(t) + Idyn(t)

8

Isc

Istatic

Idyn

Penn ESE 570 Spring 2019 - Khanna

Charging

!  Idyn(t) – why is it changing? "  Ids = f(Vds,Vgs) "  and Vgs, Vds changing

9

€

IDS = µnCOXWL

"

# $

%

& ' VGS −VT( )VDS −

VDS2

2)

* +

,

- .

€

IDS ≈νsatCOXW VGS −VT −VDSAT

2%

& '

(

) *


Switching Energy – focus on Idyn(t)


Isc

Istatic

Idyn

Switching Energy – focus on Idyn(t)

E = P(t)dt∫= I(t)Vdd dt∫=Vdd I(t)dt∫

11

Idyn


Switching Energy

12

!  Do we know what this is?

Idyn

Idyn (t)dt∫



3

Switching Energy

13


Idyn

Q = Idyn (t)dt∫



Switching Energy

14


!  What is Q? Idyn

Q = Idyn (t)dt∫



Switching Energy

15



Q = Idyn (t)dt∫


€

Q = CV = I(t)dt∫


Switching Energy

16



Q = Idyn (t)dt∫


€

Q = CV = I(t)dt∫

€

E = CVdd2

Capacitor charging energy


Switching Power

!  Every time output switches 0#1 pay: "  E = CV2

!  Pdyn = (# 0#1 trans) × CV2 / time


Switching Power

!  Every time output switches 0#1 pay: "  E = CV2

!  Pdyn = (# 0#1 trans) × CV2 / time

!  # 0#1 trans = ½ # of transitions

!  Pdyn = (# trans) × ½CV2 / time


4

Switching


Short Circuit Power

Short Circuit Power

!  Between VTN and Vdd - VTP

"  Both N and P devices conducting


Short Circuit Power

!  Between VTN and Vdd - VTP

"  Both N and P devices conducting

!  Roughly:

21

Isc


Vin

time

Vout

Isdp

time

time

time

Vthn

Vdd

Vdd

Vdd-Vthp

Isc

tsc tsc

Peak Current

!  Ipeak around Vdd/2 "  If |VTN|=|VTP| and sized equal rise/fall

22

€


2%

& '

(

) *


Vin

time

Vout

Isdp

time

time

time

Vthn

Vdd

Vdd

Vdd-Vthp

Isc

tsc tsc

Peak Current


23

€


2%

& '

(

) *

€

I(t)dt∫ ≈ Ipeak × tsc ×12%

& ' (

) *


Vin

time

Vout

Isdp

time

time

time

Vthn

Vdd

Vdd

Vdd-Vthp

Isc

tsc tsc

Vin

time

Vout

Isdp

time

time

time

Vthn

Vdd

Vdd

Vdd-Vthp

Isc

tsc tsc

Peak Current


24

€


2%

& '

(

) *

€

I(t)dt∫ ≈ Ipeak × tsc ×12%

& ' (

) *

€

E =Vdd × Ipeak × tsc ×12#

$ % &

' (


5

Dynamic Characteristics


Inverter Delay

!  Caused by charging and discharging the capacitive load "  What is the load?


Inverter Delay


Inverter Delay


Inverter Delay

29

Cgb = Cgbn+ Cgbp


Inverter Delay

30

Cload = C#dbn + C#

dbp + C#gdn + C#

gdp + Cint + Cgb

Cgb = Cgbn+ Cgbp


6

Inverter Delay

31

Cload ≈ C#dbn + C#

dbp + Cint + Cgb

Usually Cdb >> Cgd Csb >> Cgs


32

Cload ≈ Cdbn + Cdbp + Cint + nCgb

n = fan-out ≥ 1

Inverter Delay


Propagation Delay Definitions

33

VDD

0 t

VDD

0

V50% = VDD/2 Penn ESE 570 Spring 2019 – Khanna


34

t




Rise/Fall Times


7

MOS Inverter Dynamic Performance

!  ANALYSIS (OR SIMULATION): For a given MOS inverter schematic and Cload, estimate (or measure) the propagation delays

!  DESIGN: For given specs for the propagation delays and Cload*,

determine the MOS inverter schematic

37

Assume Vin ideal






38

3 METHODS: 1. Average Current Model

Assume Vin ideal

τPHL ≈CloadΔVHLIavg ,HL

τPLH ≈CloadΔVLHIavg ,LH






39

3 METHODS: 2. Differential Equation Model

Assume Vin ideal

iC =CloaddVoutdt

⇒ dt∫ =CloaddVoutiC

∫dt ≈ τ PHL or τ PLH






40

3 METHODS: 3. 1st Order RC delay Model

Assume Vin ideal

τ PHL ≈ 0.69 ⋅Cload ⋅Rnτ PLH ≈ 0.69 ⋅Cload ⋅Rp


Method 1

Average Current Model


Calculation of Propagation Delays

42

τ PHL ≈ CloadΔVHLIavg,HL

=CloadVOH −V50%Iavg,HL

τ PLH ≈ CloadΔVLHIavg,LH

=CloadV50% −VOLIavg,LH


8


43







44






Calculation of Rise/Fall Times

45

τ fall ≈ CloadΔV90%−10%Iavg,90%−10%

=CloadV90% −V10%Iavg,90%−10%

τ rise ≈ CloadΔV10%−90%Iavg,10%−90%

=CloadV90% −V10%Iavg,10%−90%





=CloadV90% −V10%Iavg,90%−10%


=CloadV90% −V10%Iavg,10%−90%




=CloadV90% −V10%Iavg,90%−10%


=CloadV90% −V10%Iavg,10%−90%

Method 2

Differential Equation Model


9

Calculating Propagation Delays

49

Two Cases 1. Vin abruptly rises => Vout falls => 2. Vin abruptly falls => Vout rises =>

Assume Vin is an ideal pulse-input

iDP - iDn

τ PHLτ PLH


Case 1: Vin Abruptly Rises - τPHL





52

≈

≈



53

≈

≈



54

V out= V DD− V T0n

≈

≈


10


55


≈

CloaddVoutdt

≈ −iDn

dt =Cload−dVoutiDn

τ PHL = dtt=t0

t=t50%∫ =Cload−1iDn

$

%&

'

()

Vout=VDD

Vout=VDD /2∫ dVout

τ PHL =Cload−1iDn

$

%&

'

()

VDD

VDD−VT 0n∫ dVout +Cload−1iDn

$

%&

'

()

VDD−VT 0n

VDD /2∫ dVout



56


≈

CloaddVoutdt

≈ −iDn

dt =Cload−dVoutiDn

τ PHL = dtt=t0

t=t50%∫ =Cload−1iDn

$

%&

'

()

Vout=VDD

Vout=VDD /2∫ dVout


$

%&

'

()

VDD


$

%&

'

()

VDD−VT 0n

VDD /2∫ dVout

t0#t1 t1#t50% Penn ESE 570 Spring 2019 – Khanna


57



"

#$

%

&'

VDD


"

#$

%

&'

VDD−VT 0n

VDD /2∫ dVout

t0#t1 t1#t50%

saturation linear



58



"

#$

%

&'

VDD


"

#$

%

&'

VDD−VT 0n

VDD /2∫ dVout

t0#t1 t1#t50%

saturation linear

saturation: iDn =kn2(Vin −VT 0n )

2

τ PHL,sat =Cload−1

kn2(VDD −VT 0n )

2

"

#

$$$

%

&

'''

VDD

VDD−VT 0n∫ dVout

τ PHL,sat =−Cload

kn2(VDD −VT 0n )

2dVoutVDD

VDD−VT 0n∫

τ PHL,sat =2CloadVT 0n

kn (VDD −VT 0n )2



59



"

#$

%

&'

VDD


"

#$

%

&'

VDD−VT 0n

VDD /2∫ dVout

t0#t1 t1#t50%

saturation linear

linear: iDn =kn2(Vin −VT 0n )Vout −V

2out( )

τ PHL,lin =Cload−1

kn22(VDD −VT 0n )Vout −V

2out( )

"

#

$$$

%

&

'''

VDD−VT 0n

VDD /2∫ dVout

τ PHL,lin =2Cload

kn

−12(VDD −VT 0n )Vout −V

2out( )

"

#$$

%

&''VDD−VT 0n

VDD /2∫ dVout

τ PHL,lin =2Cload

kn⋅

−12(VDD −VT 0n )

ln Vout2(VDD −VT 0n )−Vout( )

"

#$$

%

&''Vout=VDD−VT 0n

Vout=VDD /2



60

τ PHL,lin =2Cload

kn⋅

−12(VDD −VT 0n )

ln Vout2(VDD −VT 0n )−Vout( )

#

$%%

&

'((Vout=VDD−VT 0n

Vout=VDD /2

τ PHL,lin =Cload

kn (VDD −VT 0n )ln 2(VDD −VT 0n )−VDD 2

VDD 2#

$%

&

'(


11


61



"

#$

%

&'

VDD


"

#$

%

&'

VDD−VT 0n

VDD /2∫ dVout

t0#t1 t1#t50%

saturation linear


kn (VDD −VT 0n )2 τ PHL,lin =

Cload


VDD 2"

#$

%

&'

τ PHL = 2CloadVT 0n

kn (VDD −VT 0n )2 +Cload


VDD 2"

#$

%

&'



62



"

#$

%

&'

VDD


"

#$

%

&'

VDD−VT 0n

VDD /2∫ dVout

t0#t1 t1#t50%

saturation linear


kn (VDD −VT 0n )2




VDD 2"

#$

%

&'

τ PHL,lin =Cload


VDD 2"

#$

%

&'

τ PHL =Cload ⋅1

kn (VDD −VT 0n )2VT 0n

(VDD −VT 0n )+ ln 2(VDD −VT 0n )

VDD 2−1

#

$%

&

'(

)

*+

,

-.



63



"

#$

%

&'

VDD


"

#$

%

&'

VDD−VT 0n

VDD /2∫ dVout

t0#t1 t1#t50%

saturation linear


kn (VDD −VT 0n )2




VDD 2"

#$

%

&'

τ PHL,lin =Cload


VDD 2"

#$

%

&'

τ PHL =Cload ⋅1



VDD 2−1

#

$%

&

'(

)

*+

,

-.

Rn


64

Recall from static CMOS Inverter:

(1) Vth → kR; (2) τPHL → kn; (3) kR & kn → kp DESIGN:

τ PHL =Cload ⋅1



VDD 2−1

#

$%

&

'(

)

*+

,

-.

Vth =VT 0n +

1kR

VDD +VT 0 p( )

1+ 1kR

kR =VDD +VT 0 p −VthVth −VT 0n

"

#$

%

&'

2



65

Recall from static CMOS Inverter:

(1) Vth → kR; (2) τPHL → kn; (3) kR & kn → kp DESIGN:

τ PHL =Cload ⋅1



VDD 2−1

#

$%

&

'(

)

*+

,

-.

Vth =VT 0n +

1kR

VDD +VT 0 p( )

1+ 1kR

kR =VDD +VT 0 p −VthVth −VT 0n

"

#$

%

&'

2



(1) Vth → kR; (2) τPLH → kp; (3) kR & kp → kn

66

τ PHL =Cload ⋅1



VDD 2−1

#

$%

&

'(

)

*+

,

-.

Differential Model Approximation


"

#$

%

&'

VDD


"

#$

%

&'

VDD−VT 0n

VDD /2∫ dVout

t0#t1 t1#t50%

saturation linear

Approximate by assuming in saturation:


12

67 Δ is less than 10%

τ PHL =Cload ⋅1



VDD 2−1

#

$%

&

'(

)

*+

,

-.



"

#$

%

&'

VDD


"

#$

%

&'

VDD−VT 0n

VDD /2∫ dVout

t0#t1 t1#t50%

saturation linear

τ PHL ≈ Cload−1iDn,sat

#

$%%

&

'((VDD

VDD /2∫ dVout =−Cload

kn2(VDD −VT 0n )

2

#

$

%%%

&

'

(((

VDD

VDD /2∫ dVout

τ PHL ≈CloadVDD

kn (VDD −VT 0n )2 ∝RnCload



68

Δ is less than 10%

τ PHL =Cload ⋅1



VDD 2−1

#

$%

&

'(

)

*+

,

-.



"

#$

%

&'

VDD


"

#$

%

&'

VDD−VT 0n

VDD /2∫ dVout

t0#t1 t1#t50%

saturation linear

τ PHL ≈ Cload−1iDn,vsat

#

$%%

&

'((VDD

VDD /2∫ dVout

=−Cload

vsatCOXW VDD −VT 0n −Vdsat2

*

+,-

./

#

$

%%%%

&

'

((((

VDD

VDD /2∫ dVout

τ PHL ≈CloadVDD

2vsatCOXW VDD −VT 0n −Vdsat2

#

$%

&

'(∝RnCload

Approximate by assuming in velocity saturation:

Vdsat ≈Lvsatµn


Example 1:

!  Consider a CMOS inverter with Cload=1pF and VDD=5V. The nMOS transistor has VT0n=1V and kn=625uA/V2.

!  Assume Vin is an ideal step pulse with instant rise/fall times. Calculate the delay time necessary for the inverter output to fall from its initial value of 5V to 2.5V.


Example 1:



70

τ PHL =Cload ⋅1



VDD 2−1

#

$%

&

'(

)

*+

,

-.


Example 1:



71

τ PHL =Cload ⋅1



VDD 2−1

#

$%

&

'(

)

*+

,

-.

τ PHL =1×10−12 ⋅

1(625×10−6 )(5−1)

2(5−1)

+ ln 2(5−1)2.5

−1#

$%

&

'(

)

*+

,

-.

τ PHL = 0.52ns


Example 1:

72

τ PHL =Cload ⋅1



VDD 2−1

#

$%

&

'(

)

*+

,

-.

τ PHL =1×10−12 ⋅

1(625×10−6 )(5−1)

2(5−1)

+ ln 2(5−1)2.5

−1#

$%

&

'(

)

*+

,

-.

τ PHL = 0.52ns

τ PHL ≈CloadVDD




13

Example 1:

73

τ PHL =Cload ⋅1



VDD 2−1

#

$%

&

'(

)

*+

,

-.

τ PHL =1×10−12 ⋅

1(625×10−6 )(5−1)

2(5−1)

+ ln 2(5−1)2.5

−1#

$%

&

'(

)

*+

,

-.

τ PHL = 0.52ns

τ PHL ≈CloadVDD


τ PHL ≈1×10−12 (5)

625×10−6 (5−1)2= 0.5ns


Δ < 3%


Example 2:

!  Consider a CMOS inverter with Cload=1pF and VDD=5V. The nMOS transistor has VT0n=1V, k’n=20uA/V2, and W/L=10.

!  Use the average current method to calculate the fall time. Assume VOH=VDD, and VOL=0V.

74

Usefull equations:


=CloadV90% −V10%Iavg,90%−10%

ID,sat =k 'n2WLVGS −VT 0n( )2

ID,lin =k 'n2WL2 VGS −VT 0n( )VDS −V 2

DS( )


Example 2:



75

Iavg, fall =12ic (Vin =VOH ,Vout =V90%)+ ic (Vin =VOH ,Vout =V10%)[ ]

Iavg, fall =12ic (Vin = 5V,Vout = 4.5V )+ ic (Vin = 5V,Vout = 0.5V )[ ]

Iavg, fall =12k 'n2WLVin −VT 0n( )2 + k 'n

2WL2 Vin −VT 0n( )Vout −V 2

out( )"

#$%

&'

Iavg, fall =1220×10−6

2(10) 5−1( )2 + 20×10

−6

2(10) 2 5−1( )(0.5)− (0.5)2( )

"

#$

%

&'

Iavg, fall = 0.988mAPenn ESE 570 Spring 2019 – Khanna

Example 2:



76

Iavg, fall =12ic (Vin =VOH ,Vout =V90%)+ ic (Vin =VOH ,Vout =V10%)[ ]

Iavg, fall =12ic (Vin = 5V,Vout = 4.5V )+ ic (Vin = 5V,Vout = 0.5V )[ ]

Iavg, fall =12k 'n2WLVin −VT 0n( )2 + k 'n

2WL2 Vin −VT 0n( )Vout −V 2

out( )"

#$%

&'

Iavg, fall =1220×10−6

2(10) 5−1( )2 + 20×10

−6

2(10) 2 5−1( )(0.5)− (0.5)2( )

"

#$

%

&'

Iavg, fall = 0.988mAPenn ESE 570 Spring 2019 – Khanna

Example 2:



77

Iavg, fall = 0.988mA


=CloadV90% −V10%Iavg,90%−10%

τ fall ≈1×10−12 4.5− 0.50.988×10−3

= 4ns


Example 2:


!  Use the differential equation method to calculate the fall time. Assume VOH=VDD, and VOL=0V.

78

Usefull equations:

iC =CloaddVoutdt


∫


id ,sat =12k 'nWLVGS −VT 0n( )

2

id ,lin =12k 'nWL2(VGS −VT 0n )VDS −V

2DS( )

14

Example 2:



79

iC =CloaddVoutdt

= −12k 'nWLVin −VT 0n( )

2

dt = −2Cload

k 'n W L( ) VDD −VT 0n( )2dVout

dt = − 2∗1×10−12

20×10−6 10( ) 5−1( )2dVout = −6.25×10

−10dVout

dtt=t90%

t=tsat

∫ = −6.25×10−10 dVoutVout=4.5

Vout=4.0

∫ = 0.313ns


Example 2:

!  Consider a CMOS inverter with Cload=1pF and VDD=5V. The nMOS transistor has VT0n=1V, kn=20uA/V2, and W/L=10.


80

t90% → tsat = 0.313nsiC =Cload

dVoutdt

= −12k 'n

WL2(Vin −VT 0n )Vout −V

2out( )

dt = − 2Cload

k 'n W L( ) 2(VDD −VT 0n )Vout −V 2out( )

dVout

dtt=tsat

t=t10%

∫ = −2Cload

k 'n W L( )1

2(VDD −VT 0n )Vout −V2out( )

dVoutVout=4

Vout=0.5

∫

dtt=tsat

t=t10%

∫ =Cload

k 'n W L( )⋅

1Vin −VT 0n

ln 2(Vin −VT 0n )−V10%V10%

$

%&

'

()

dtt=tsat

t=t10%

∫ =1×10−12

20×10−6 10( )⋅15−1

ln 2(5−1)− 0.50.5

$

%&

'

()= 3.39ns

Example 2:

!  Consider a CMOS inverter with Cload=1pF and VDD=5V. The nMOS transistor has VT0n=1V, kn=20uA/V2, and W/L=10.


81

t90% → tsat = 0.313nsiC =Cload

dVoutdt

= −12k 'n

WL2(Vin −VT 0n )Vout −V

2out( )

dt = − 2Cload

k 'n W L( ) 2(VDD −VT 0n )Vout −V 2out( )

dVout

dtt=tsat

t=t10%

∫ = −2Cload

k 'n W L( )1

2(VDD −VT 0n )Vout −V2out( )

dVoutVout=4

Vout=0.5

∫

dtt=tsat

t=t10%

∫ =Cload

k 'n W L( )⋅

1Vin −VT 0n

ln 2(Vin −VT 0n )−V10%V10%

$

%&

'

()

dtt=tsat

t=t10%

∫ =1×10−12

20×10−6 10( )⋅15−1

ln 2(5−1)− 0.50.5

$

%&

'

()= 3.39ns

t90% → t10% = 3.7ns

Avg method: 4ns

Case 2: Vin Abruptly Falls - τPLH

82

τ PLH =Cload1iDp

!

"##

$

%&&0

−VT 0 p∫ dVout +Cload1iDp

!

"##

$

%&&−VT 0 p

V50%∫ dVout

t0#t1 t1#t50%

saturation linear


τ PLH =Cload ⋅1

kp(VDD− |VT 0 p |)2 |VT 0 p |

(VDD− |VT 0 p |)+ ln

2(VDD− |VT 0 p |)VDD 2

−1#

$%

&

'(

)

*++

,

-..

Case 2: Vin Abruptly Falls - τPLH

83

τ PLH =Cload1iDp

!

"##

$

%&&0

−VT 0 p∫ dVout +Cload1iDp

!

"##

$

%&&−VT 0 p

V50%∫ dVout

t0#t1 t1#t50%

saturation linear


Rp

τ PLH ≈CloadVDD

kp(VDD− |VT 0 p |)2

τ PLH =Cload ⋅1

kp(VDD− |VT 0 p |)2 |VT 0 p |



−1#

$%

&

'(

)

*++

,

-..

RpCload

Differential Equation Model

84

CONDITIONS for Balanced CMOS Propagation Delays, i.e.

τ PLH =Cload ⋅1

kp(VDD− |VT 0 p |)2 |VT 0 p |



−1#

$%

&

'(

)

*++

,

-..

τ PHL =Cload ⋅1



VDD 2−1

#

$%

&

'(

)

*+

,

-.

WL

!

"#

$

%&p

= µn

µp

WL

!

"#

$

%&n

#


15

Delay Observations

85

τ PLH =Cload ⋅1

kp(VDD− |VT 0 p |)2 |VT 0 p |



−1#

$%

&

'(

)

*++

,

-..

τ PHL =Cload ⋅1



VDD 2−1

#

$%

&

'(

)

*+

,

-.


86

τ PLH =Cload ⋅1

kp(VDD− |VT 0 p |)2 |VT 0 p |



−1#

$%

&

'(

)

*++

,

-..

τ PHL =Cload ⋅1



VDD 2−1

#

$%

&

'(

)

*+

,

-.

Delay Design Equations


87

Delay Design Equations w/ Saturation Approximation

τ PHL ≈CloadVDD

kn (VDD −VT 0n )2

τ PLH ≈CloadVDD

kp(VDD− |VT 0 p |)2

WL

!

"#

$

%&n

≈CloadVDD

τ PHLµnCox (VDD −VT 0n )2

WL

!

"#

$

%&p

≈CloadVDD

τ PLHµpCox (VDD− |VT 0 p |)2


Design for Delays with More Realistic Model for Cload

88

Cload Cdbn + Cdbp + Cint + Cgb i≈ i

i≈ iCload Cdbn(Wn) + Cdbp(Wp) + Cint + Cgb


89

Cdbn (Wn) = [Wn (Y + xj)] Cj0n Keqn + (Wn + 2Y) Cjswn Keqn(sw)

Cdbp (Wp) = [Wp (Y + xj)] Cj0p Keqp + (Wp + 2Y) Cjswp Keqp(sw)


90

Cload = α0 + αnWn + αpWp

α0 = 2YCjswnKeqn + 2YCjswpKeqp + Cint + Cgb

αn = (Y + xj)Cj0nKeqn + CjswnKeqn

αp = (Y + xj)Cj0pKeqp + CjswpKeqp

Cdbn (Wn) = [Wn (Y + xj)] Cj0n Keqn + (Wn + 2Y) Cjswn Keqn(sw)

Cdbp (Wp) = [Wp (Y + xj)] Cj0p Keqp + (Wp + 2Y) Cjswp Keqp(sw)


16

91

and


τ PLH =Cload ⋅1

kp(VDD− |VT 0 p |)2 |VT 0 p |



−1#

$%

&

'(

)

*++

,

-..

τ PHL =Cload ⋅1



VDD 2−1

#

$%

&

'(

)

*+

,

-.

τPHL = ΓnCload (Wn )Wn

τPLH = ΓpCload (Wp )Wp


92

and


τ PLH =Cload ⋅1

kp(VDD− |VT 0 p |)2 |VT 0 p |



−1#

$%

&

'(

)

*++

,

-..

τ PHL =Cload ⋅1



VDD 2−1

#

$%

&

'(

)

*+

,

-.

const.

Γn and ΓP are set largely by process parameters and VDD









94

Cload = α0 + αnWn + αpWp





95

Cload = α0 + αnWn + αpWp Cload = α0 + αnWn + (αpWp/Wn)Wn Cload = α0 + [αn + αpR]Wn


where R = Wp/Wn = constant




96


where R = Wp/Wn = constant (Recall: when Lp=Ln) Vth = 1kR=µpWp

µnWn




17


97


Cload = α0 + αnWn + αpWp Cload = α0 + (αnWn/Wp)Wp + αpWp Cload = α0 + [αn/R + αp]Wp

where R = Wp/Wn = constant (Recall: when Lp=Ln) Vth = 1kR=µpWp

µnWn





98


Cload = α0 + αnWn + αpWp Cload = α0 + (αnWn/Wp)Wp + αpWp Cload = α0 + [αn/R + αp]Wp

where R = Wp/Wn = constant

α0 + [αn + αpR]Wn

Wn

τPHL = Γn τPLH = Γp

α0 + [αn/R + αp]Wp

Wp

(Recall: when Lp=Ln) Vth = 1kR=µpWp

µnWn





99

where R (constant) = aspect ratio = Wp/Wn


Wn



Wp



100

where R (constant) = aspect ratio = Wp/Wn

= limit τPHL = Γn [αn + αp R] Wn → large absolute

minimum delays = limit τPLH = Γp [αn/R + αp]

Wp → large

Hence increasing Wn and Wp will have diminishing influence on τPHL and τPLH as they become large, i.e.


Wn



Wp

τPHL

τPLH


101


Penn ESE 570 Spring 2019 – Khanna 102



18

Taking Into Account Non-Ideal Input Waveform

103

ideal Vin non-ideal Vin Vout to ideal Vin Vout to non-ideal Vin






104

METHODS: 1.  Average Current Model

2.  Differential Equation Model

3.  1st Order RC delay Model

Assume Vin ideal




iC =CloaddVoutdt


∫dt ≈ τ PHL or τ PLH

τ PHL ≈ 0.69 ⋅Cload ⋅Rn

Idea

!  Ptot = Pstatic + Pdyn+ Psc

"  Can’t ignore Static Power (aka. Leakage power)

!  Propogation Delay "  Average Current Model "  Differential Equation Model "  1st Order Model

"  More next time…


Admin

!  HW 5 out "  Due 3/1

!  Quiz next lecture Thursday 2/21 "  First 15 minutes of class "  Starts at 1:30pm exactly "  Closed book "  Covers lecture 1-9


Documents

Lecture Outline ESE 570: Digital Integrated Circuits and VLSI ...ese570/spring2019/handouts/...Q=CV= ∫I(t)dt € E=CV dd 2 Capacitor charging energy Penn ESE 570 Spring 2019 - Khanna