Degradation Caused by Negative Bias Temperature Instability Depending onBody Bias on NMOS or PMOS in 65 nm Bulk and Thin-BOX FDSOI Processes

Ryo Kishida and Kazutoshi KobayashiDepartment of Electronics, Graduate School of Science and Technology, Kyoto Institute of Technology

AbstractReverse Body Bias (RBB) control on Fully Depleted

Silicon On Insulator (FDSOI) with thin Buried OXide(BOX) layer mitigates power consumption on the stand-by mode. However, Degradation caused by Negative BiasTemperature Instability (NBTI) is changed by RBB. Wemeasure aging degradation of ring oscillators by applyingRBB to NMOS or PMOS. In bulk, RBB to PMOSsuppresses NBTI-induced degradation because increasingthreshold voltage reduces carriers in channel. However,RBB to NMOS does not suppress NBTI-induced degra-dation because Positive BTI (PBTI) is not dominant inNMOS. In FDSOI, RBB to not only PMOS but alsoNMOS suppresses NBTI-induced degradation becauseBOX layer intercepts carriers to flow to substrate.

I. IntroductionIn recent years, low power consumption is mandatory

to reduce power density and to prolong battery life. ThinBuried OXide (BOX) Fully-Depleted Silicon On Insulator(FDSOI) is one possible candidate to operate in the lowvoltage of 0.4 V [1]. Reverse Body Bias (RBB) canreduce power consumption further more. However, degra-dation caused by Negativec Bias Temperature Instability(NBTI) is changed by RBB [2], [3]. NBTI causes agingdegradation and become significant concern in nano-scaleddevices [4]. The same amount of RBB is generally appliedto NMOS and PMOS. However, it requires additionalvoltage source for RBB to NMOS. Our purpose is tooptimize RBB voltage in NMOS and PMOS to suppressNBTI-induced degradation. We measure aging degradationof Ring Oscillators (ROs) by periodically counting thenumber of oscillation during stress conditions.

II. BTI-induced Degradation by RBBFig. 1 shows how to control body bias. N-well in PMOS

and P-well in NMOS are connected to source terminalson the standard mode as shown in Fig. 1 (a). Fig. 1 (b)shows the RBB conditions. N-well and P-well are biasedto positive and negative for source terminals of PMOSand NMOS respectively. Fig. 2 shows an example howto use RBB. RBB suppresses power consumption on thestand-by mode because threshold voltage (Vth) increasesand leakage current decreases. Body bias cannot be con-trolled in SOI with conventional thick BOX. However,thin-BOX FDSOI can control the body bias as shownin Fig. 3 [1]. We evaluate BTI-induced degradation bychanging RBB in bulk and thin-BOX FDSOI with 10 nmBOX layers. RBB suppresses aging degradations and Vthincreases with time as voltage and temperature increase[4]. The atomistic trap-based BTI (ATB) model [5] isone of proposed theories of BTI as shown in Fig. 4. BTIoccurs and Vth increases since defects in a gate oxide trapcarriers as shown in Fig. 4 (a). The number of carriers inchannel decreases by applying RBB as shown in Fig. 4 (b).Probability to trap carriers decreases because the numberof carriers induced in the channel decreases. Therefore,it becomes harder to trap carriers to the defects as RBBincreases. There are Negative BTI (NBTI) and PositiveBTI (PBTI). NBTI occurs on PMOS when gate-sourcevoltage is negative. Likewise, PBTI is observed in NMOSespecially in technologies with high-k gate dielectrics [6].

III. Measurement SetupWe fabricated a chip including 11-stage ROs composed

of NOR gates to dominate NBTI as shown in Fig. 5.PMOS of NORs are stressed by NBTI when ENB ishigh to stop oscillation. Fig. 6 shows our measurementflow. During frequency measurement, ENB becomes lowonly for 28 µs and RBB is restored to 0 V to oscillatein the same condition. RBB is applied while ROs stoposcillation for 50 s. ROs suffer from NBTI in the low-power mode. NBTI measurement condition is at 1.6 Vpower supply voltage and 120 ◦C temperature to accelerateNBTI-induced degradation. Fig. 7 shows the test chipfabricated in 65 nm bulk and thin-BOX FDSOI processes.Layout patterns are same in both processes.

IV. Measurement ResultsFig. 8 shows measurement results by the body bias. X-

axis is stress time and Y-axis is degradation rate basedon initial frequencies. Dots represent average of measure-ment data and curves are drawn by the fitting functionalong SNBTI log(t + 1). SNBTI is the fitting parameterindicating degradations caused by NBTI. This functioncomes from the ATB model since defects have a timeconstant distributed uniformly on the log scale from 10−9 sto 109 s [7]. Fig. 8 (a) and (b) show the measurementresults in bulk when RBB is applied to NMOS or PMOS.VBN and VBP are defined body bias of NMOS and PMOSrespectively. Difference of degradation rate at 0 and 1 V ofVBN is only less than 0.05%. While in PMOS, degradationrate decreases by 38% when VBP of 1 V is applied. NBTI-induced degradation is suppressed by applying VBP inbulk because NBTI is more dominant than PBTI in 65 nmprocess. Fig. 8 (c) and (d) show the measurement resultsin FDSOI when VBN or VBP are applied. Degradation ratedecreases as RBB increases in RBB of both MOSFETs.We assume oscillation frequencies increase because carri-ers are captured in channel by RBB. BOX layer interceptscarriers to flow to substrate. We also evaluate degradationfactor SNBTI from fitting functions. Fig. 9 (a) and (b) showSNBTI in bulk by applying VBN or VBP. Fig. 9 (c) and (d)show those in FDSOI. SNBTI are almost constant in anyVBN of bulk, which means NBTI is not suppressed by VBNin bulk. Likewise, SNBTI decreases by 40% at VBP of 1 V.SNBTI in FDSOI is about twice as large as that in bulkbecause Vth of FDSOI is lower than that of bulk. Electricfield in the gate oxide is higher in lower Vth and agingdegradation is accelerated. In FDSOI, SNBTI decreaseas RBB on both MOSFETs and are almost equivalent.Applying RBB on PMOS is enough to suppress NBTI-induced degradation without RBB on NMOS and negativevoltage sources are not required.

V. ConclusionWe fabricated ring oscillators in 65 nm bulk and thin-

BOX FDSOI processes and measured aging degradationapplied RBB to NMOS or PMOS. RBB on NMOS cannotsuppress degradation in bulk, while RBB on PMOS,the degradation is suppressed. The degradation factordecreases by 40% from 0 to 1 V of RBB on PMOS. InFDSOI, the degradation factor decreases by RBB on bothNMOS and PMOS. Applying RBB to PMOS is enoughto suppress NBTI-induced degradation.

G

S D

Gate

Oxide

VDD

PMOS

G

S D

Gate

Oxide

NMOS

GND

N-well P-well

(a)G

S D

Gate

Oxide

G

S D

Gate

Oxide

RBB RBB

PMOS NMOS

N-well P-well

|Vth |

(b)Fig. 1: Body bias (BB) control. (a) no BBand (b) reverse BB (RBB).

CPU

CPU

BB=0

RBB

Standard operation

Low stand-by power

Suppress aging degradationLonger lifetime

Fig. 2: RBB to suppress power con-sumption and aging degradation forchips on cars.

G

S

Gate

Oxide

RBB

BOX 10 nm

|Vth|

~~

PNP SOI 12 nm ~~

Fig. 3: Cross section of thin-BOX FDSOI on PMOS. It cancontrol BB through 10 nm thin-BOX layers.

G

S D

Gate

Oxide

Vg

Carrieres

Oxide Trap Interface Trap

Si

Defect

(a)

G

S D

Gate

Oxide

Vg

Si

RBB

Carriers|Vth|Si

Defect

(b)

Fig. 4: BTI mechanism. (a) Atomistic trap-based BTImodel. Vth increases when carriers are trapped. (b) Sup-pression of NBTI by RBB. Vth increases and the numberof carries decrease.

ENB

OUT000 00

1

Fig. 5: 11-stage RO composed NORgates.

Oscillation

28 µs

NBTI stress = 50 s

OUT

VB RBB

Oscillation

28 µs

Fig. 6: Measurement flow.

2.0 mm

6.2 mm

65 nm process 576 ROs

Fig. 7: Test chip.

0.00

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(a) NMOS RBB in bulk.

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(b) PMOS RBB in bulk.

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(c) NMOS RBB in FDSOI.

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(d) PMOS RBB in FDSOI.Fig. 8: Measurement results of NBTI.

0

2

4

6

8

10

0 0.2 0.4 0.6 0.8 1

SN

BT

I [x 1

0-2

]

VBN (Reverse body bias of NMOS) [V]

3.523.21

2.763.00 2.98

(a) NMOS RBB in bulk.

0

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0 0.2 0.4 0.6 0.8 1

SN

BT

I [x 1

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3.52

2.52 2.472.11

(b) PMOS RBB in bulk.

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BT

I [x 1

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(c) NMOS RBB in FDSOI.

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BT

I [x 1

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8.35

7.25

5.79

4.46

(d) PMOS RBB in FDSOI.Fig. 9: Degradation factor SNBTI.

AcknowledgmentsWe thank Prof. Kumashiro for valuable comments. The

chip for this work was fabricated by Renesas Electronicsand designed by utilizing the EDA system supported by theVLSI Design and Education Center (VDEC), the Universityof Tokyo in collaboration with Synopsys Inc., CadenceDesign System and Mentor Graphics Inc.

References[1] R. Tsuchiya et al., IEDM, pp. 631-634, 2004.[2] R. Kishida et al., SSDM, pp. 711-712, 2016.[3] J. Franco et al., IEDM, pp 18.5.1-18.5.4, 2011.[4] V. Huard et al., IRPS, pp. 289-300, 2008.[5] H. Kukner et al., IEEE Trans. on Dev. & Mat. Rel.,

pp. 182-193, 2014.[6] S. Zafar et al., VLSI Tech., pp. 23-25, 2006.[7] B. Kaczer et al., IRPS, pp XT.3.1-XT.3.5, 2011.