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7/30/2019 DEC - Module - II - Part2
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Introduction to FPGAs
FPGA (Field Programmable Gate Array) ASIC chips provide the highest performance, but
can only perform the function they were designed
for.
FPGAs can be reprogrammed using HDLs or
other design methods to implement a incredible
variety of functions
Allow for efficient and cost-effectiveprototyping
Cost of FPGA chips is very low compared to
ASICs because they are not specialized for a
specific task
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FPGA: Configurable Logic Blocks
Essential FPGAcomponent
Each CLB can bereprogrammed toimplement a basicsequential orcombinational circuit
Create array of CLBs
At intersection of wiresare switches
Form switching matrix
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FPGA: Configurable Logic Blocks
Two 16x1 RAM blocks 8x1 RAM block
2 Edge-triggered D
flip-flops
Multiplexers used to
configure
interconnects
Newer FPGAsprovide other
additional hardware
features
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FPGA: Configurable Logic Blocks
RAM blocks act asLook Up Tables
Used to implement
combinationalfunctions
By using all 3 LUTs,
can implement anyBoolean function of 5
variables
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FPGA: Switching Network PSM: programmable
switching matrix configuredto connect vertical andhorizontal wires
Singles: connect adjacentPSMs
Doubles: connect every otherPSM (traverses 2 CLBs)
Quad: traverses 4 CLBs
Global: run entire length ofchip. Use tristate buffers andcan be used as buses shared
by several CLBs Purpose: allows signals to be
routed through fewerswitching points
Global nets: low-skew signal
network for high fan-outsignals (clocks and reset
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FPGA Design Flow
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Whats VHDL? Basic
Concept
VHDL
Very Hard Difficult Language
Very High Speed Integrated Circuit Hardware
Description Language
Front end/Back end Design
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Why VHDL? (Using an HDL)
Can be used for
Describing,
Modeling, and
Designing digital systems
For the goals of
Requirement specification
Documentation
Testing using simulation
Verification
Synthesizing digital circuits
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VHDL Development
US DoD initiated in 80s
Very High Speed ASIC Description
Language Initial objective was modeling only and
thus only a simulator was envisaged
Subsequently tools for VHDL synthesiswere developed
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History of VHDL
Launched in 1980 by Defense Advanced
Research Projects Agency (DARPA)
July 1983Intermetrics, IBM and Texas
Instruments were awarded a contract to
develop VHDL
August 1985 release of final version of
the language under government contract,
VHDL Version 7.2
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December 1987IEEE Standard 1076-
1987
1988VHDL became an American
National
Standards Institute (ANSI ) standard
In 1990 Cadence opened the
language to the public
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For RTL design VITAL added
VITAL(VHDL Initiative Towards ASICLibrary)
IEEE revised VHDL & VITAL in 1993
September Final review of standard in 2001
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VHDL vs. Verilog
Complex grammar
Complicated
compiler
Large memory forsimulation
Hard to learn
A lot of data types
High level data types,
Pointers
Alias
Easy language Simple & fast
compiler
Efficient memory
usage and faster
Easy to learn for
beginner
A few data types
Hardware related
Wires
Registers
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VHDL vs. Verilog
User defined types
Strong type
checking
(ie it checks the
typing more
rigorously)
User defined
Library &
package
Open Language
All primitive types
Some castings are
allowed
No user defined
packages
Cadences
language at first
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Verilog modeled after C, VHDL is modeled
after Ada
Verilog is case sensitive while VHDL is not
VHDL is more flexible
Verilog used extensively in the US while
VHDL is used internationally
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Data Types
bit values: '0', '1'
boolean values: TRUE, FALSE
integer values: -(231) to +(231 - 1)
std_logic values: 'U','X','1','0','Z','W','H','L','-'
U' = uninitialized'X' = unknown
'W' = weak 'X
'Z' = floating
'H'/'L' = weak '1'/'0
'-' = don't care
Std_logic_vector (n downto 0);
Std_logic_vector (0 upto n);
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Additional standardized packagesprovide definitions
of data types and expressions of
timing data
IEEE 1164 (data types)
IEEE 1076.3 (numeric)
IEEE 1076.4 (timing)
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Hardware description languages descr ibe a
system Systems can be described from many
different points of view
Behavior: what does it do?
Structure: what is it composed of? Functional properties: how do I interface to
it?
Physical properties: how fast is it?
Usage (Using an HDL)
Descriptions can used for Simulation
Verification, performance evaluation
Synthesis
First step in hardware design
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Synthesis
Synthesis:
Conversion of behavioral level description to
structural level netlist
Structural level netlist
Implementation of behavioral description
Describes interconnection of gates
Synthesis tool we shall use:
Leonardo Spectrum/ISE inbuilt synthesizer
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Simulation Simulation is modeling the
output response of a circuit
to given input stimuli
For our example circuit:
Given the values of A, Band S
Determine the values of Xand Y
Many types of simulators
used Event driven simulator is
used popularly
Simulation tool we shall
use: ModelSim/inbuilt
my_ckt
A
B
S
X
Y
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Module/Unit
Logic module
A
B
C
Out put
In putsFull
Adder
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Defining Modules in VHDL
1.Define block by giving name
2.Specify i/p ,o/p lines (ports).
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VHDL language elements
VHDL is composed of language building
blocksthat consist of more than 75 reservedwordsand about 200 descriptive wordsor
wordcombinations
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Reserved VHDL keywords
VARIABLE
WAIT
WHEN
WHILE
WITH
XNOR
XOR
RETURN
SELECT
SEVERITY
SIGNAL
SHARED
SLA
SLL
SRA
SRL
SUBTYPE
THEN
TO
TRANSPORT
TYPE
UNAFFECTED
UNITS
UNTIL
USE
OF
ON
OPEN
OR
OTHERS
OUT
PACKAGE
PORT
POSTPONED
PROCEDURE
PROCESS
PURE
RANGE
RECORD
REGISTER
REM
REPORT
ROL
ROR
IN
INERTIAL
INOUT
IS
LABEL
LIBRARY
LINKAGE
LITERAL
LOOP
MAP
MOD
NAND
NEW
NEXTNOR
NOT
NULL
DISCONNECT
DOWNTO
ELSE
ELSIF
END
ENTITY
EXIT
FILE
FOR
FUNCTION
GENERATE
GENERIC
GROUP
GUARDED
IF
IMPURE
ABS
ACCESS
AFTER
ALIAS
ALL
AND
ARCHITECTURE
ARRAY
ASSERT
ATTRIBUTE
BEGIN
BLOCK
BODY
BUFFER
BUS
CASE
COMPONENT
CONFIGURATION
CONSTANT
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Levels of Abstraction Digital system can be represented at different
levels of abstraction
Behavioralrelationship between input and
output signals, usually boolean expressions
Structuraldescription of the collection of
gates and connections, more like a schematic
Physical (Layout)
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VHDL Programming
Dataflow
Behavioral
Structural
Mixed Structural and Behavioral
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VHDL structure
Library
Definitions, constants
EntityInterface
Architecture
Implementation, function
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Libraries
Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_arith.all;
Use ieee.std_logic_signed.all;
Use ieee.std_logic_unsigned.all;
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Entity
Define inputs andoutputs
Example:
Entity test is
Port( A,B,C,D: in
std_logic;E: out std_logic);
End test;
Inputs and Outputs
Chip
A
B
C
D
E
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Entity
Describes the interface of a module
entity Reg4 is
port ( d0, d1, d2, d3, en, clk : in
std_logic;
q0, q1, q2, q3 : out std_logic);
end Reg4;
enti ty name port names port mode (direction)
port type
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Basic Identifiers
Can Only Use
alphabetic letters ( A-Z, a-z ), or
Decimal digits ( 0-9 ), or
Underline character ( _ )
Must Start With Alphabetic Letter
May NOT end with underline ( MyVal_ )
May NOT contain sequential underlines
(My__Val)
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Not case sensiti ve, but recommended to use
alwaysthe sameway.
I t is also recommended touse capitals for
language components
Examples
B3,b3,ram1,ram_1,ram_1_c, MyVal.
The followings are not used
_Basic_gate
Ram_2_Ram__2
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The mode of the port
= in, out, inout, buffer, linkagein: Component only read the signal
out: Component only write to the signal
inout: Component read or write to the signal(bidirectional signals)
buffer: Component write and read back the
signal (no bidirectional signals, the signal isgoing out from the component)
linkage: Used only in the documentation
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Concurrent operation
Q=a+ b .c
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Architecture
Define
functionality of the
chip
X
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Dataflow Model The flow of data through the entity is modeled
primarily using concurrent signal assignmentstatements. (uses statements that defines theactual flow of data.....)
The structure of the entity is not explicitlyspecified but it can be implicitly deduced.
Architecture MYARCH of MYENT is
beginSUM
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity half_adder is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
carry : out STD_LOGIC;sum : out STD_LOGIC);
end half_adder;
architecture Behavioral of half_adder is
begin
sum
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Logical operators defined in
VHDL NOT
AND
NAND
OR
NOR
XOR
XNOR
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Delay in Signal Assignment
There are two types of delay that can be
applied when assigning a time/value pair
into the driver of a signalInertial Delay
Transport Delay
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Inertial Delay
Inertial delay models the delays oftenfound in switching circuits. An inputvalue must remain stable for a specifiedtime (pulse rejection limit) before the
value is allowed to propagate to theoutput.
This is the delay due to the fact that
electronic gates require a short amountof time to respond to the movement ofenergy within the circuit.
The value appears at the output after the
specified inertial-delay.
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Transport Delay
This delay models pure propagation delay; ie,any change in the input (no matter how small)is transported to the output after the specifieddelay time period
To use a transport delay model, the keywordtransportmust be used in a signal assignmentstatement
Ideal delay modeling can be obtained by using
this delay model, where spikes would bepropagated through instead of being ignored
Output
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Example: 1-bit Full Adder(with delay)
entity FullAdderis
port (X, Y, Cin: in bit; -- Inputs
Cout, Sum: out bit); -- Outputs
end FullAdder;
XY
Cin
Sum
CoutFull Adder
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Example: 1-bit Full Adder
(contd.)Architecture Equations ofFullAdderis
begin -- Concurrent Assignment
Sum
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p g
In1
In2
s1
c_in
sum
c_out
HA HA
ORs2
s3
This example shows a model of a full adder constructed from2 half-adders and a 2 input OR gate.
The behavior of the 3 components is described using processes
that communicatethrough signals.
When there is an eventon either of the input signals, process HA1
executes (see code in next slide), which creates eventson internal
signalss1 and s2.
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library IEEE;
use IEEE.std_logic_1164.all;
entity full_adder is
port(in1, in2, c_in: in std_ulogic;sum, c_out: out std_ulogic);
end full_adder;
architecture dataflow of full_adder issignal s1, s2, s3 : std_ulogic;
constant gate_delay: Time:=5 ns;
begin
L1: s1
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Structural Model Digital circuits consist of components and
interconnection between them A component can in turn be composed of sub-
components and their interconnections
A component interacts with other componentsthrough pins
Component is modeled as entity
Component pins are modeled as ports
Interconnections between components are
modeled as signals
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VHDL Structural Elements
Entity: Interface
Architecture: Implementation, behavior,
function Process: Concurrency, event controlled
Configuration: Model chaining, structure,
hierarchy Package: Modular design, standard solution,
data types, constants
Library: Compilation, object code
ChipA
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--Structural Description
entity AOI_Network is
port(A,B.C,D:in std_logic;
E:out std_logic);
end AOI_Network
architecture structural of AOI_Network is
component AND2
port(x,y:in std_logic;
z:out std_logic);
end component;
pA
B
C
D
EX
Y
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component or2
port(x,y:in std_logic;
z:out std_logic);
end component;
signal X,Y:std_logic;Begin
G1:AND2 port map (A,B,X);
G2:AND2 port map (C,D,Y);G3:OR2 port map (X,Y,E);
End structural;
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Before this the module should be previously
defined
use library.entity AND2 is
port (u,v:in std_logic;
q:out std_logic);end AND2;
architecture of AND2 is
beginq
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Example: 4-bit Adder
entity Adder4 is
port (A, B: in bit_vector(3 downto 0);
Ci: in bit; -- Inputs
S: outbit_vector(3 downto 0);
Co: out bit); -- Outputs
end Adder4;
E l 4 bit Add ( td )
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Example: 4-bit Adder (contd.)
Architecture Structure of Adder4 isComponent FullAdder
port (X, Y, Cin: in bit; Cout, Sum: out bit);
signal C: bit_vector (3 downto 1);
begin -- Instantiations
FA0: FullAdder port map (A(0), B(0), Ci, C(1), S(0));
FA1: FullAdder port map (A(1), B(1), C(1), C(2), S(1));
FA2: FullAdder port map (A(2), B(2), C(2), C(3), S(2));
FA3: FullAdder port map (A(3), B(3), C(3), Co, S(3));
end Structure;
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The concept of component can be
understood using the concept of a design
library, which is a collection of differentmodules, each defined by entity and
architecture statement.
Once cells are used in library we can usecopies by component command
This is called instancing the cell, and
component itself is called an instance of theoriginal.
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Modeling the Behavior way
Architecture body describes an implementation of an entity
may be several per entity
Behavioralarchitecture
describes the algorithm performed by the
module
contains
process statements, each containing
sequential statements, including
signal assignment statementsand
wait statements
F ll Add i P
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Full Adder using Processes
library ieee;
use ieee.std_logic_1164.all;entity FULL_ADDER is
port (A, B, Cin : in std_logic;
Sum, Cout : out std_logic);
end FULL_ADDER;
Process P2 that defines
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architecture BEHAV_FAof FULL_ADDER is
signal int1, int2, int3:
std_logic;begin
-- Process P1 that definesthe first half adder
P1: process (A, B)begin
int1
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Multiplexers
A B
4-to-1
MUX
I0
I1
I2
I3
Z
A
B
I3
A
B
I2
AB
I1
A
B
I0
Z
Data inputs
versus controlinputs
Use of
muxes in
control and
data path
A B Z0 0 I00 1 I11 0 I21 1 I3
+
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Concurrent Conditional
Assignment: 4 to 1 Multiplexery
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CASE Statement:
4 to 1 Multiplexer
Case sel is
when 0 => y y y y
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2 to 4 decoder with enable,
DeMUX
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Example: DFF (contd.)
Architecture Beh ofDFF is
begin process (CLK)
beginif(CLK = 1 then
Q
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Internal Structure of aPLA
Inputs
A
A
B
B
C
C
AND ARRAY
OR ARRAY
F0 F1 F2 F3
Outputs
AB
AC
B
BC
AC