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DDRIII BASED GENERAL PURPOSE FIFO

ON VIRTEX-6 FPGA ML605 BOARDPART A PRESENTATION

STUDENTS:

OLEG KORENEV

EUGENE REZNIK

SUPERVISOR:

ROLF HILGENDORF

Semester: spring 2012

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CONTENT1. Project overview 2. Specifications 3. Part A goals4. Memory on ml605 5. AXI46. Part A overview7. Part B goals and Workflow8. Timeline

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PROJECT OVERVIEWDesign and implementation of General Purpose FIFO IP core which allows usage of external memory (DDR3) as FIFO storage on Xilinx FPGA device

• Design and implement generic IP core of FIFO

• Design and implement GUI generator of IP core on PC

• Create sample design with implemented IP core

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SPECIFICATIONSHardware

• Xilinx Virtex-6 ML605 FPGA Evaluation Kit • DDR III memory• Ethernet interface

• PC with Ethernet interface

Software• ISE Design Suite Logic Edition Version 14.3• Modelsim• Wireshark• Winpcap library

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OUR GOALS PART A•Gain experience in hardware development

(VHDL environment)•Explore and expertise FPGA work environment•Create design with configurable

• word size• FIFO depth

•Achieve best performance•Minimize usage of FPGA resources•Make our world a better place

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MEMORY ON ML605 DDR3 memory

• Capacity: 512MB

• Max theoretical bandwidth: 800MT/s*64bit = 6.4GB/sec

Xilinx provides us with DDR3 controller which has AXI Memory Mapped interface

• AXI bus data width up to 1024 bit

• 256 bit for max memory performance, assuming bus works with 200Mhz

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4AXIXilinx provides us with AXI4 Memory Mapped bus, which is a standard bus used in modern ARM SoC.

Features• Separate Address/Control and Data Phases• burst-based transactions with only start address issued• separate read and write data channels

CONTROLLER

Native Fifo Interface

MEMORY TO FIFO

FIFO

FIFO TO MEMORY

FIFO

GENERAL PURPOSE FIFOAXI4 Interface

GENERAL PURPOSE FIFOINTERFACE

GP

FIF

O

Native FIFOAXI4

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PART A OVERVIEW GENERAL PURPOSE FIFO

Interface• GP FIFO has native FIFO interface• Word size can be 32, 64, 128, 256, 512, 1024 bit• Utilizes DDR3 memory through AXI interconnect• Depth is limited only by available RAM memory on DDR3

Internal architecture• Internal FIFO-To-Memory controller• Internal Memory-To-FIFO controller• Internal Bypass controller

Arbitration between GP FIFOs is managed by AXI interconnect

MAC Module

EXAMPLE DESIGN BLOCK DIAGRAM

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DDR3HOST STORAGE LOGIC STORAGE USER STORAGE

MEMORY CONTROLLER

AXI4 BUS (INTERCONNECT)

General Purpose Fifo

Example Design

MAC Controller

HOST

General Purpose Fifo

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Interface• Utilizes Ethernet MAC level of communication• Software has simple and intuitive interface • Software handles all the data transmission in between host

and GP FIFOInternal architecture

• MAC module• GP FIFO• Simple example of a logic which uses GP FIFO

MAC can potentially provide us with a considerably high speed of datatransmission, the bottleneck is software - driver performance

PART A OVERVIEW EXAMPLE DESIGN

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PART A OVERVIEWCONCLUSION

Our design meets the requirements of the project.• GP FIFO is fast

limited only by interconnect bus available bandwidth• GP FIFO has potentially configurable depth and word size• GP FIFO is simple, utilizes small amount of resources on

the board

GP FIFO gives you another easy way to pass big chunks of data from one module to another.

Our example design provides you with efficient communication in between a host and the board.

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OUR GOALS PART B

• Generalize our GP FIFO• Simulate and test all the possible configurations and their

exceptional case• Make possible optimizations• Close timing on each configuration• Develop software generator of GP FIFO IP core• Write detailed manual for IP core and for it’s generator

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TIMELINE16/6 9/6 2/6 26/5 19/5 12/5 5/5 28/4 21/4 14/4 7/4 Duration Task

2 weeks Generalize GP FIFO

2 weeks Optimizations

3 weeksSimulation and Testing

2 weeks Close Timing

3 weeks Develop IP core generator

2 weeks Write manual