XTP091 - ML605 Board & FMC XM104 Connectivity Card IBERT ... · – Create IBERT Design – FMC SMA/SATA ML605 & FMC XM104: Using IBERT ACE Files ML605 & FMC XM104: Generate IBERT

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ML605 Board & FMC XM104 Connectivity Card IBERT Design: SMA & SATA Interfaces

March 2012

XTP091

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Revision History

Date Version Description 03/16/12 13.4 Recompiled under 13.4.

10/26/11 13.3 Recompiled under 13.3.






ML605 IBERT Overview

Xilinx ML605 & FMC XM104 Boards – Xilinx Virtex-6 FPGA Connectivity Kit

Software Requirements ML605 & FMC XM104: IBERT Setup ML605 & FMC XM104: Running the IBERT Design ML605 & FMC XM104 IBERT Design Creation

– Create IBERT CORE Generator Project – Create IBERT Design – FMC SMA/SATA

ML605 & FMC XM104: Using IBERT ACE Files ML605 & FMC XM104: Generate IBERT ACE Files References

Note: This presentation applies to the ML605 and XM104 Boards

ML605 IBERT Overview

Description – The LogiCORE Integrated Bit Error Ratio (IBERT) core is used to create a

pattern generation and verification design to exercise the Virtex-6 GTX transceivers. A graphical user interface is provided through the IBERT console window of the ChipScope Pro Analyzer

Reference Design IP – LogiCORE IBERT Example Designs

• FMC_HPC (4 Transceivers)

– ChipScope Pro Analyzer • ChipScope Pro Software and Cores User Guide (UG029)

Note: Presentation applies to the ML605 and XM104 Boards

Xilinx Virtex-6 FPGA Connectivity Kit

FMC XM104 Board

ML605 Board


ISE Software Requirements

Xilinx ISE 13.4 software


ChipScope Pro Software Requirement

Xilinx ChipScope Pro 13.4 software


ML605 & FMC XM104: IBERT Setup


Unzip ug664.zip file to your C:\ drive – Available through http://www.xilinx.com/v6connkit



SATA Loopback Cable – Included in Connectivity Kit



SMA Cables – Included in Connectivity Kit – 4 cables used with IBERT



The Virtex-6 Connectivity Kit includes the attached FMC XM104 Board


Connect J4 and J10 with an SMA Cable









Connect J5 and J7 with an SMA cable

Connect J11 and J12 with the provided SATA loopback cable


Set S2 to 0101XX (X = Don’t care, 1 = on, Position 6 → Position 1) – This selects JTAG

Set S1 to 0XXX (Position 4 → Position 1) – This disables JTAG configuration from the Compact Flash



Connect a USB Type-A to Mini-B cable to the USB JTAG connector on the ML605 board – Connect this cable to your PC – Power on the ML605 Board


ML605 & FMC XM104: Running the IBERT Design


Open ChipScope Pro and click on the Open Cable Button (1) Click OK (2)

1

2



Select Device → DEV:1 MyDevice1 (XC6VLX240T) → Configure… Select <Design Path>\ready_for_download\ml605_fmc_xm104_ibert.bit



Select File → Open Project… Select <Design Path>\ready_for_download\ml605_fmc_xm104_ibert.cpj



Click Yes on this Dialog



The line rate is 3.125 Gbps for all four GTXs (1)

1

Note: GTX0_113, GTX1_113 = SATA; GTX2_113, GTX3_113 = SMA


TX Diff Output Swing = 590 mV TX Pre-Emphasis = 0.15 dB; TX Post-Emphasis = 0.18 dB



TX/RX Data Patterns are set to PRBS 7-bit and 15-bit (1) Click BERT Reset buttons (2)

1

2



View the RX Bit Error Count (1) Different GTX Transceivers used as TX & RX partners


2

ML605 & FMC XM104: IBERT Project Creation

Create IBERT CORE Generator Project

Open the CORE Generator Start → All Programs → Xilinx ISE Design Suite 13.4 → ISE Design Tools → Tools → CORE Generator

Create a new project; select File → New Project



Create a project directory: ml605_fmc_xm104_ibert



Name the project: ml605_fmc_xm104_ibert.cgp



Select Part Under the Project

options, set the Part (as seen here): – Family: Virtex6 – Device: xc6vlx240t – Package: ff1156 – Speed Grade: -1

Select Generation



Set the Design Entry to Verilog

Click OK


ML605 & FMC XM104: IBERT Design Creation


Right click on the IBERT Virtex6 GTX (ChipScope Pro - IBERT, Version 2.06a – Select Customize


Make the following settings: – Component name:

ml605_fmc_xm104_ibert Under the System Clock,

select the following settings: – Use External Clock

source – Frequency: 200 – Location: J9 – Standard: LVDS 25

Click Next

Create IBERT Design

Make the following settings – Select All GTs – Max Line rate: 3.125

Gbps – The Refclk Frequency:

156.25 MHz – GTX count: 8

Click Next

Create IBERT Design

Set the following GTX locations to the Custom 1 / 3.125 Gbps Protocol: – QUAD_112 (for

Clocking) – QUAD_113

Click Next

Create IBERT Design

Connect all GTXs to: – MGTREFCLK0 112 – This connects Bank 113 to

the Bank 112 156.25 MHz GTX Ref Clock

– GTX Ref Clock comes in from the XM104 board on Bank 112 signal FMC_HPC_GBTCLK1_M2C

Click Next

Create IBERT Design

Click Generate

Create IBERT Design


After the IBERT core finishes generating, click Close on the Readme File window


ML605 & FMC XM104: Generate IBERT ACE Files

ML605 & FMC XM104: Generate IBERT ACE File

Type these commands in an ISE Design Suite Command Prompt: cd C:\ml605_fmc_xm104_ibert\ready_for_download make_ace.bat


ML605 & FMC XM104: Using the IBERT ACE File

Use a CompactFlash reader to mount the ML605 CompactFlash as a disk drive

Copy the file, <Design Path>\ready_for_download\ ml605_fmc_xm104_ibert.ace to <CF Drive>\XILINX\cfg6


http://support.xilinx.com/xlnx/xil_ans_display.jsp?getPagePath=19668�

ML605 & FMC XM104: Using IBERT ACE Files


Set S2 to 0101XX (X = Don’t care, 1 = on, Position 6 → Position 1) – This selects JTAG

Set S1 to 1110 (Position 4 → Position 1) – This enables JTAG configuration from the Compact Flash, slot 6 – The ML605 CompactFlash has an ML605 FMC XM104 IBERT ACE file



Insert CompactFlash into the ML605 and cycle board power Start the ChipScope Pro Analyzer and open the

ml605_fmc_xm104_ibert.cpj project


References

References

ChipScope Pro – ChipScope Pro Software and Cores User Guide

http://www.xilinx.com/support/documentation/sw_manuals/ xilinx13_4/chipscope_pro_sw_cores_ug029.pdf

http://www.xilinx.com/support/documentation/sw_manuals/xilinx13_4/chipscope_pro_sw_cores_ug029.pdf�

http://www.xilinx.com/support/documentation/sw_manuals/xilinx13_4/chipscope_pro_sw_cores_ug029.pdf�

Documentation

Documentation

Virtex-6 – Virtex-6 FPGA Family

http://www.xilinx.com/products/silicon-devices/fpga/virtex-6/index.htm

FMC XM104 Documentation – FMC XM104 Connectivity Card

http://www.xilinx.com/products/boards-and-kits/HW-FMC-XM104-G.htm – FMC XM104 Connectivity Card User Guide

http://www.xilinx.com/support/documentation/boards_and_kits/ug536.pdf

http://www.xilinx.com/products/silicon-devices/fpga/virtex-6/index.htm�

http://www.xilinx.com/products/boards-and-kits/HW-FMC-XM104-G.htm�

http://www.xilinx.com/support/documentation/boards_and_kits/ug536.pdf�

Documentation

ML605 Documentation – Virtex-6 FPGA ML605 Evaluation Kit

http://www.xilinx.com/products/silicon-devices/fpga/virtex-6/index.htm – ML605 Getting Started Guide

http://www.xilinx.com/support/documentation/boards_and_kits/ug533.pdf – ML605 Hardware User Guide

http://www.xilinx.com/support/documentation/boards_and_kits/ug534.pdf – ML605 Reference Design User Guide

http://www.xilinx.com/support/documentation/boards_and_kits/ug535.pdf

http://www.xilinx.com/products/silicon-devices/fpga/virtex-6/index.htm�




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XTP091 - ML605 Board & FMC XM104 Connectivity Card IBERT ... · – Create IBERT Design – FMC SMA/SATA ML605 & FMC XM104: Using IBERT ACE Files ML605 & FMC XM104: Generate IBERT