DCS 2 LAB FILE

8/10/2019 DCS 2 LAB FILE

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DIGITAL CIRCUITS AND SYSTEMSII

EC407

Karan Saini

EC-II

68/EC/11


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INDEX

S.NO Experiment Signature

1 Characterization of Logic Family. Find out logicThreshold values and noise margins. Delay time

measurement of inverter using ring oscillator.

2 Design of combinational circuit, 2-4 Decoder, 4-2encoder, Binary to gray code converter using VHDL

3 Model flip-flop, register, latch in VHDL. ImplementAsynchronous and synchronous reset

4 Design of Traffic Light Controller system

5 Binary and BCD counter using VHDL.

6 Data demultiplexer. Data is required on a highspeed 4-bit input bus, output to one of the three 4-

bit output bus.

7 Serial in parallel out register using VHDL.

8 ALU using VHDL

9 FSM To check divisibility by 5


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EXPERIMENT 1

AIM: Characterization of Logic Family. Find out logic Threshold valuesand noise margins. Delay time measurement of inverter using ring

oscillator.

DIAGRAM:


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OBSERVATION TABLE:

(a) Delay time of an inverter:

S. NO. No of inverters

(N)

Frequency observed

(f)

Delay of inverter

(tpd)

1 3 30.3 MHz 5 ns

2 5 20MHz 5ns

3 7 13MHz 5ns

Using the formula

(b) Logic threshold values and Noise margins:

S. NO. Input Voltage (Vi) Output Voltage (Vo)


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GRAPH:

Result: For IC

74HCT04B1 the delay time of a single inverter comes

out to be 5ns and the logic threshold values and noise margins are


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EXPERIMENT 2

AIM: Design of combinational circuit, 2-4 Decoder, 4-2 encoder, Binary

to gray code converter using VHDL

CODE:

a)2 X 4 decoder:

library ieee;

use ieee.std_logic_1164.all;

entity Decoder2x4 isport(i :in std_logic_vector(1 downto 0);e :in

std_logic;ostd_logic_vector(3 down to 0));

end Decoder2x4;

architecture Behv of Decoder2x4 is

begin

process(i,e)

begin

if(e=1) then

o(0)


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end component;

signal i:std_logic_vector(1 downto 0);

signal e:std_logic;

signal o:std_logic_vector(3 downto 0);

begin

inst:Decoder2x4 port map(i,e,o);

process

begin

e


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end process;end architecture;

Test Bench

-- test bench

entity tb isend tb;

architecture tb_arch of tb iscomponent encoder4x2 is

port(i:instd_logic_vector(3 downto 0);o:outstd_logic_vector(1 downto 0);e:instd_logic);end component;signal i:std_logic_vector(3 downto 0);signal o:std_logic_vector(1 downto 0);signal e:std_logic;begin

inst:encoder4x2 port map(i,o,e);processbegin

e


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process(i,e)begin

if e=1 theno(0)


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EXPERIMENT 3

AIM: Model flip-flop, register, latch in VHDL. Implement Asynchronous

and synchronous reset

CODE:

a)Synchronous and Asynchronous register

--synchronous register

library ieee;

use ieee.std_logic_1164.all;entity syn_8_reg is

port(d:instd_logic_vector(7 downto 0);q:out std_logic_vector(7 downto 0);

clk:instd_logic;rst:instd_logic);end syn_8_reg;architecture behv_syn of syn_8_reg isbeginprocess(clk)begin

if clk=1 then

if rst=1 thenq


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process(clk,rst)begin

if rst=1 thenq


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b)Synchronous and Asynchronous D flip flop

--synchronous D flip-floplibrary ieee;use ieee.std_logic_1164.all;

entity syn_d_ff isport(d:instd_logic;q:outstd_logic;clk:instd_logic;

rst:instd_logic);end syn_d_ff;architecture behv_syn of syn_d_ff isbeginprocess(clk)begin

if clk=1 thenif rst=1 then

q


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Test Bench

--test bench

entity tb is

end tb;architecture tb_arch of tb is

component syn_d_ff isport(d:instd_logic;q:outstd_logic;clk:instd_logic;

rst:instd_logic);end component;component asyn_d_ff is

port(d:instd_logic;q:outstd_logic;clk:instd_logic;rst:instd_logic);end component;

signal d,qsyn,qasyn,rst,clk: std_logic;begininst1: syn_d_ff port map(d,qsyn,clk,rst);inst2: asyn_d_ff port map(d,qasyn,clk,rst);processbegin

d


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process(d,rst)begin

if rst=1 thenq


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greenif count=10 then

tlcstate:=SYELLOW;

count:=0;elsecount:=count+1;red


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EXPERIMENT 5

AIM: BCD and Binary counter using VHDL

CODE:

--binary counterlibrary ieee;use ieee.std_logic_1164.all;entitybincnt is

port(count:outstd_logic_vector(3 downto 0);clk:instd_logic;rst:instd_logic);end bincnt;

architecture bincnt_arch of bincnt isbeginprocess(clk,rst)begin

if rst=1 thencount


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EXPERIMENT 6

AIM: Design of 4-bit data demultiplexer

CODE:

--Demultiplexer 4 bit data on three 4 bit output bus

library ieee;use ieee.std_logic_1164.all;

entity demux is

port(din:instd_logic_vector(3 downto 0);sel:instd_logic_vector(1 downto 0);dout1, dout2,dout3:outstd_logic_vector(3 downto 0));end demux;

architecture demux_arch of demux isbeginprocess(din,sel)begin

case sel iswhen 00=> dout1


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architecture tb_arch of tb iscomponent demux is

port(din:instd_logic_vector(3 downto 0);sel:instd_logic_vector(1 downto 0);dout1, dout2,dout3:outstd_logic_vector(3 downto 0));

end component;signal din,dout1,dout2,dout3:std_logic_vector(3 downto 0);signal sel:std_logic_vector(1 downto 0);begininst:demux port map(din,sel,dout1,dout2,dout3);p1:processbegin

din


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EXPERIMENT 7

AIM: Serial-In-Parallel-Out register using VHDL

CODE:

--serial in parallel out register

library ieee;use ieee.std_logic_1164.all;

entity sipo isport(sin,clk,rst,enable:instd_logic;o:out

std_logic_vector(3 downto 0));end sipo;

architecture sipo_arch of sipo issignal temp:std_logic_vector(3 downto 0);beginprocess(clk)begin

if rst=1 thentemp=0000;

else

if clk=1 and enable=1 thentemp(3)


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EXPERIMENT 8

AIM: Design an ALU using VHDL

CODE:

--ALU

library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;

entity alu isport(a,b:instd_logic_vector(6 downto 0);

z:out std_logic_vector(7 downto 0);sel:instd_logic-vector(3 downto 0);

c:in std_logic);end alu;architecture alu_d_arch of alu isbeginprocess(a,b,sel)begin

case sel is

when 0000=>z(6 downto 0) z(6 downto 0)z(6 downto 0)z(6 downto 0) z z z z z(6 downto 1)

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DCS 2 LAB FILE