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DEMO MANUAL DC2071A
Description
LTC2373/LTC237216-Bit/18-Bit, 1Msps/500ksps
8-Channel, SAR ADCs with 100dB SNR
Demonstration circuit 2071A features the LTC®2373 family. The LTC2373/LTC2372 are low noise, high speed, 8-chan-nel, 16-/18-bit successive approximation register (SAR) ADCs. The following text refers to the LTC2373-18 but applies to all parts in the family, the only differences being the number of bits and the maximum sample rate. Operat-ing from a single 5V supply, the LTC2373-18 has a highly configurable, low crosstalk, 8-channel input multiplexer, supporting fully differential, pseudo-differential unipolar and pseudo-differential bipolar analog input ranges.
The DC2071 demonstrates the DC and AC performance of the LTC2373-18 in conjunction with the DC590 and DC890 data collection boards. Use the DC590 to demonstrate DC
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and QuikEval and PScope are trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners.
performance such as peak-to-peak noise and DC linearity. Use the DC890 if precise sampling rates are required or to demonstrate AC performance such as SNR, THD, SINAD and SFDR. The demonstration circuit 2071 is intended to demonstrate recommended grounding, component place-ment and selection, routing and bypassing for this ADC. Several suggested driver circuits for the analog inputs will be presented.
Design files for this circuit board are available at http://www.linear.com/demo/DC2071A
Assembly optionsTable 1. DC2071A Assembly OptionsAssembly Version U1 Part Number Max Conversion Rate Number of Bits Max CLK IN Frequency
DC2071A-A LTC2373CUH-18 1Msps 18 62MHz
DC2071A-B LTC2372CUH-18 0.5Msps 18 31MHz
DC2071A-D LTC2373CUH-16 1Msps 16 50MHz
DC2071A-E LTC2372CUH-16 0.5Msps 16 25MHz
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DEMO MANUAL DC2071A
boArD photo
Figure 1. DC2071A Connection Diagram
0V TO 4.096V
0V TO 4.096V
±8.192V
0V TO 4.096V
±4.096V
±4.096V
–16V GND +16V
CLK100MHz MAX3.3VPP
DC890
DC590ORDC2026
DEFAULT INPUT LEVELS
A
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DEMO MANUAL DC2071A
Dc890 Quick stArt proceDureCheck to make sure that all switches and jumpers are set as shown in the connection diagram of Figure 1. The default connections configure the ADC to use the onboard reference and regulators to generate the required common mode voltages. The analog input is DC coupled. Connect the DC2071A to a DC890 USB High Speed Data Collec-tion Board using connector P1. Then, connect the DC890 to a host PC with a standard USB A/B cable. Apply ±16V to the indicated terminals. Then apply a low jitter signal source to J2–J7. Observe the recommended input voltage range for each analog input. Connect a low jitter 2.5VPP sine wave or square wave to connector J1. See Table 1 for the appropriate clock frequency. Note that J1 has a 50Ω termination resistor to ground.
Run the PScope™ software (Pscope.exe version K76 or later) which can be downloaded from www.linear.com/designtools/software.
Complete software documentation is available from the Help menu. Updates can be downloaded from the Tools menu. Check for updates periodically as new features may be added.
The PScope software should recognize the DC2071A and configure itself automatically.
Click the Collect button (See Figure 7) to begin acquiring data. The Collect button then changes to Pause, which can be clicked to stop data acquisition.
Dc590 Quick stArt proceDureIMPORTANT! To avoid damage to the DC2071A, make sure that VCCIO (JP6) of the DC590 is set to 3.3V before connecting the DC590 to the DC2071A.
To use the DC590 with the DC2071A, it is necessary to apply ±16V and ground to the ±16V and GND terminals on the DC2071A. Connect the DC590 to a host PC with a standard USB A/B cable. Connect the DC2071A to a DC590 USB serial controller using the supplied 14-conductor
ribbon cable. Apply a signal source to J2-J7. No clock is required on J1 when using the DC590. The clock is provided by the DC590.
Run the QuikEval™ software (quikeval.exe version K103 or later) which is available from www.linear.com/design-tools/software. The correct control panel will be loaded automatically. Click the Collect button (Figure 10) to begin reading the ADC.
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DEMO MANUAL DC2071A
DC Power
The DC2071A requires ±16VDC and draws +100mA/ –40mA. Most of the supply current is consumed by the CPLD, op amps, regulators and discrete logic on the board. The +16VDC input voltage powers the ADC through LT1763 regulators which provide protection against accidental reverse bias. Additional regulators provide power for the CPLD and op amps. See Figure 1 for connection details.
Clock Source
You must provide a low jitter 2.5VPP sine or square wave to the clock input, J1. The clock input is AC coupled so the DC level of the clock signal is not important. A generator like the Rohde & Schwarz SMB100A high speed clock source is recommended. Even a good generator can start to produce noticeable jitter at low frequencies. Therefore it is recommended for lower sample rates to divide down a higher frequency clock to the desired sample rate. The ratio of clock frequency to conversion rate is 62:1 for 18-bit parts and 50:1 for 16-bit parts. If the clock input is to be driven with logic, it is recommended that the 49.9Ω terminator (R3) be removed. Slow rising edges may compromise the SNR of the converter in the presence of high-amplitude higher frequency input signals.
Data Output
Parallel data output from this board (0V to 2.5V default), if not connected to the DC890, can be acquired by a logic analyzer and subsequently imported into a spreadsheet or mathematical package depending on what form of digital signal processing is desired. Alternatively, the data can be fed directly into an application circuit. Use pin-50 of P1 to latch the data. The data should be latched using the positive edge of this signal. The data output signal levels at P1 can also be increased to 0V to 3.3V if the application circuit requires a higher voltage. This is accomplished by moving JP3 to the 3.3V position.
Reference
The default reference is the LTC2373-18 internal 4.096V reference. Alternatively, if an external reference voltage is
desired, the LTC6655-4.096 reference (U9) can be used by setting the REF jumper (JP1) to the EXT position and installing a 0Ω resistor in the R19 position.
Analog Inputs
The four default driver circuits for the analog inputs of the LTC2373-18 on the DC2071A are shown in Figures 2 to 5. The circuit of Figure 2 is a fully differential driver with 0V to 4.096V inputs. The output of this circuit is band limited to approximately 13MHz. The circuit of Figure 3 is a single-ended to differential driver with an input signal range of ±8.192V. This circuit is band limited to 1.6MHz at the output. The circuit of Figure 4 is a single-ended to differential driver with an input range of 0V to 4.096V. The output bandwidth of this circuit is 1.6MHz. The circuit of Figure 5 is a single-ended/fully differential input driver circuit with an input range of ±4.096V. The input band-width of this circuit is 4.8kHz. The output is band limited to 3MHz. The default for this circuit is single-ended drive. Drive the AIN4
– input to ±4.096V. Alternatively, by remov-ing R117 and changing R114 to 100Ω this circuit can be driven fully differentially.
The AIN1 and AIN3 driver circuits can be DC or AC coupled. The default setting is DC coupled. AC coupling the inputs may degrade the distortion performance of the ADC due to nonlinearity of the coupling capacitors. AC coupling can be implemented on the DC2071A by putting the coupling jumpers (JP6, JP8 for AIN1 and JP7 for AIN3) in the AC position, and adding two 1kΩ resistors at the optional resis-tor locations on the other side of each coupling capacitor (R91, R97, R106, R110 for AIN1 and R93, R100 for AIN3).
Another option available on the demo board is to drive each input single-ended and then convert the single-ended inputs to fully differential at the MUX outputs. This allows the user to have eight single-ended inputs but still have the SNR of a fully differential input. To accomplish this, remove C31, R8, R15 and R128 then add C15, C24, C27, C29, R7, R13, R16, R17, R18, R129, R130, R131 and U7. The values for the passive devices are shown in the schematic of Figure 6.
Dc2071A setup
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DEMO MANUAL DC2071A
Dc2071A setup
Figure 2. 0V to 4.096V Fully Differential AC/DC Coupled Driver
BNC
C7710µF6.3VR94
0Ω
C79OPT1206
C7410µF6.3V
CM2
R91OPT
R97OPT
JP6+IN1COUPLINGAC DC
3 2 1
AIN1+
0V TO4.096V
J2
BNC
C9110µF6.3VR109
0Ω
C92OPT1206
C8910µF6.3V
CM2
R106OPT
R110OPT
JP8–IN1COUPLINGAC DC
3 2 1
AIN1–
0V TO4.096V
J3
R9524.9Ω
R10124.9Ω
C84OPT
C8015pF
C9015pF
R108OPT
R10724.9Ω
V–
C86OPT
R10424.9Ω
R10510Ω
R9610Ω
R137OPT
R92OPT
V+
C820.1µF
–
+
CH0
CH1
–
+
C750.1µF
42
3
8
8
7
1
5
6
4
LT6237U24B
U24A
LT6237
Figure 3. ±8.192V Single-Ended to Differential DC Coupled Driver
BNC
R1120Ω
R11620K
R1204.99K
R13420Ω
R1130Ω
R1210Ω
C96OPT
AIN2±8.192V
J4
R1LT5400-41
2
3
4
8
7
6
5
R2
R3
R132, 20Ω
R133, 20Ω
R4
EP+
–
LT1469
U25B
U25A
CH2
VCM
CH3
C1050.01µFC0G
83
2
1
OP AMP–
OP AMP+
C9310µF25V0805
C9810µF25V0805
C9910µF6.3V
4
+
–
85
6
7 9
4
LT1469
R12520K R126
10K
C1020.01µFC0G
R13520Ω
C1060.01µFC0G
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DEMO MANUAL DC2071A
Figure 4. 0V to 4.096V Single-Ended to Differential AC/DC Coupled Driver
BNC
C7810µF6.3V
R9910Ω
C81OPT1206
C730.1µF
C721µF
C851µF
C8315pF
C7610µF6.3V
CM2
CM
R93OPTR98
0Ω
R102499Ω
R100OPT
JP7IN3COUPLINGAC DC
3 2 1
AIN30V TO
4.096V
J5
C880.1µF
C8710µF6.3V
V–
4
5
1
8
2
6
3 7
V+
R980Ω
R10310Ω
U27
+IN1
+IN2
CH5
CH4
V+
V–
OUT1
OUT2
SHDN
–IN1
LT6350
+–
+–
Figure 5. Single-Ended/Fully Differential Input to Fully Differential DC Coupled Driver
+
+
–
–SHDN
V+
V–VOCM
C940.1µF
C954.7µF10V
83
75
62
41
LTC6362
BNC
R1140Ω
R1151k
R117150Ω
C970.22µFC0G 1812
AIN4+
±4.096V
J6
C10110µF6.3V
VDD
CM
R1271k
R1111k
C1080.01µF
C1070.01µF
R11835.7Ω
R11935.7Ω
CH6
CH7
BNC
R112100Ω
R1231k
R124OPT
C1000.22µFC0G 1812
AIN4–
±4.096V
J7U28
Dc2071A setup
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DEMO MANUAL DC2071A
Figure 6. Eight Single-Ended Inputs Converted to Fully Differential
R181k
R171k
R130Ω
C10425pF
V–
C10325pF
V+C27
0.1µF
C241000pF
C290.1µF
–
+8
1
7
3
2
4
LT6237
85
6
4
LT6237
R1624.9ΩCM
BUFOUT
BUFOUT
REFBUF
REFBUF
E1
VDD VCCI0
–
+LT6237
U1
CH0CH1CH2CH3CH4CH5CH6CH7COM
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
CNVSCKSDI
SDOBUSY
RESET
RDL
V DD
VDDL
BYP
OVDD
REFB
UF
REFI
N
MUX
OUT+
ADCI
N+
MUX
OUT–
ADCI
N–
29 28 25 12 13
GND
GND
GND
GND
GND
OGND
GND
GND
27 17 15 14 11 26 23 33
313212789
1030
1621202219
24
18
+
–
C81200pF C9
OPT
C141200pF
C16OPT C17
OPT
C20OPT
C213300pF C22
3300pF
C233300pF
C251500pF C26
OPT
C281500pF
C151000pF
C1010µF25V0805
C110.1µF
C710µF25V0805
C60.1µF
C120.1µF
C1347µF10V1210X7R
R1300Ω
R1310Ω
R111k
R121k
R1291k
R724.9Ω
REF
JP1
EXT
INT
321
C194.7µF
LTC237X
U7A
U7B
Dc2071A setup
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DEMO MANUAL DC2071A
DC890 Data Collection
For SINAD, THD or SNR testing, a low noise, low distortion generator such as the B&K Type 1051 or Stanford Research SR1 should be used. A low jitter RF oscillator such as the Rohde & Schwarz SMB100A or DC1216A-A high speed clock source is used to drive the clock input. This demo board is tested in-house by attempting to duplicate the FFT plot shown in the Typical Performance Characteristics section of the LTC2373-18 data sheet. This involves using a 62MHz clock source, along with a sinusoidal generator
at a frequency of approximately 1kHz. The input signal level is approximately –1dBFS. A typical FFT obtained with DC2071A is shown in Figure 7. Note that to calculate the real SNR, the signal level (F1 amplitude= –1.058dB) has to be added back to the SNR that PScope displays. With the example shown in Figure 7 this means that the actual SNR would be 99.67dB instead of the 98.61dB that PScope displays. Taking the RMS sum of the recalculated SNR and the THD yields a SINAD of 99.5dB which is fairly close to the typical number for this ADC.
Figure 7. PScope Screen Shot
Dc2071A setup
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DEMO MANUAL DC2071A
To change the default settings for the LTC2373-18 se-quencer in PScope, click on the Set Demo Bd Options button in the PScope tool bar shown in Figure 8. This will open the Configure Sequencer menu of Figure 9. In this menu it is possible to set the number of sequences up to 16, the channel configuration, format and gain compres-sion setting for each sequence. There is also a button to return PScope to the default DC2071 settings which are optimized for the default hardware settings of the DC2071A.
There are a number of scenarios that can produce misleading results when evaluating an ADC. One that is common is feeding the converter with an input frequency that is a sub-multiple of the sample rate and which will
only exercise a small subset of the possible output codes. The proper method is to pick an M/N frequency for the input sine wave frequency. N is the number of samples in the FFT. M is a prime number between one and N/2. Multiply M/N by the sample rate to obtain the input sine wave frequency. Another scenario that can yield poor results is if you do not have a signal genera-tor capable of ppm frequency accuracy or if it cannot be locked to the clock frequency. You can use an FFT with windowing to reduce the leakage, or spreading of the fundamental, to get a close approximation of the ADC performance. If an amplifier or clock source with poor phase noise is used, the windowing will not improve the SNR.
Figure 8. PScope Tool Bar
Dc2071A setup
Figure 9. PScope Configure Sequencer Menu
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DEMO MANUAL DC2071A
DC590 Data Collection
Due to the relatively low and somewhat unpredictable sample rate of the DC590, its usefulness is limited to noise measurement and data collection of slowly moving signals. A typical data capture and histogram are shown in Figure 10. To change the default settings for the LTC2373-18 sequencer in QuikEval click on the Sequence Config. button. This will open the Sequence Configuration menu of Figure 11. In this menu, it is possible to set the number of sequences up to 16, the channel configuration, format and gain compression setting for each sequence. There is also a button to return QuikEval to the default DC2071 settings which are optimized for the default hardware settings of the DC2071A.
To get the best noise performance from the DC2071 it is recommended to place the demo board in a grounded metal enclosure filled with tissue paper.
Layout
As with any high performance ADC, this part is sensitive to layout. The area immediately surrounding the ADC on the DC2071A should be used as a guideline for place-
ment and routing of the various components associated with the ADC. Here are some things to remember when laying out a board for the LTC2373-18. A ground plane is necessary to obtain maximum performance. Keep bypass capacitors as close to supply pins as possible. Use indi-vidual low impedance returns for all bypass capacitors. Use of a symmetrical layout around the analog inputs will minimize the effects of parasitic elements. Shield analog input traces with ground to minimize coupling from other traces. Keep traces as short as possible.
Component Selection
When driving a low noise, low distortion ADC such as the LTC2373-18, component selection is important so as to not degrade performance. Resistors should have low values to minimize noise and distortion. Metal film resistors are recommended to reduce distortion caused by self heating. Because of their low voltage coefficients, to further reduce distortion, NP0 or silver mica capacitors should be used. Any buffer used to drive the LTC2373-18 should have low distortion, low noise and a fast settling time, such as the LT1469, LT6237, LT6350 or LTC6362.
Figure 10. QuikEval Screen Shot
Dc2071A setup
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DEMO MANUAL DC2071A
Figure 11. QuikEval Sequence Configuration Menu
Dc2071A setup
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DEMO MANUAL DC2071A
Dc2071A JumpersDefinitions
JP1: REF Selects INT or EXT reference for the ADC. The default setting is INT.
JP2: Selects the common mode voltage for the ADC. Choices are EXT, 2.5V, 2.048V or GND. The default set-ting is 2.048V.
JP3: VCCIO sets the output levels at J2 to either 3.3V or 2.5V. Use 2.5V to interface to the DC890 which is the default setting. Use 3.3V to interface to the DC590.
JP4: JTAG is used to program the CPLD. This is for fac-tory use only.
JP5: EEPROM is for factory use only. The default posi-tion is WP.
JP6: +IN1 COUPLING selects AC or DC coupling of +IN1. The default setting is DC.
JP7: IN3 COUPLING selects AC or DC coupling of IN3. The default setting is DC.
JP8: –IN1 COUPLING Selects AC or DC coupling of –IN1. The default setting is DC.
JP9: COM sets the DC bias voltage for the COM pin to either CM or GND. CM is the default setting.
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DEMO MANUAL DC2071A
pArts listITEM QTY REFERENCE PART DESCRIPTION MANUFACTURER/PART NUMBER
Required Circuit Components
1 18 C1–C6, C11, C12, C18, C32, C36, C61, C71, C73, C75, C82, C88, C94
CAP., X7R, 0.1µF, 16V,10%, 0603 NIC, NMC0603X7R104K16TRPF
2 10 C7, C10, C35, C40, C42, C47, C51, C57, C93, C98
CAP., X5R, 10µF 25V, 10%, 0805 TDK, C2012X5R1E106K
3 3 C8, C14, C31 CAP., C0G, 1200pF 50V 5%, 0603 MURATA GRM1885C1H122JA01D
4 0 C9, C15–C17, C20, C24, C26, C27, C29, C37, C84, C86, C96, C103, C104
CAP., 0603 OPT
5 1 C13 CAP., X7R, 47µF, 10V 10%, 1210 MURATA, GRM32ER71A476KE15L
6 2 C19, C95 CAP., X5R, 4.7µF, 10V, 20%, 0603 TDK, C1608X5R1A475M
7 3 C21, C22, C23 CAP., C0G, 3300pF 50V 5%, 0603 MURATA GRM1885C1H332JA01D
8 2 C25, C28, C55, C72, C85 CAP., C0G, 1500pF 50V 5%, 0603 MURATA GRM1885C1H152JA01D
10 1 C33 CAP., X5R, 2.2µF, 16V, 10%, 0603 TDK, C1608X5R1C225K
11 1 C38 CAP., X5R, 47µF, 25V 20%, 1206 TDK, C3216X5R1E476M
12 5 C39, C45, C50, C53, C56 CAP., NP0, 0.01µF, 25V, 5%, 0603 TDK, C1608C0G1E103J
13 11 C46, C54, C74, C76–C78, CAP., X5R, 10µF, 6.3V, 20%, 0603 TDK, C1608X5R0J106M
C87, C89, C91, C99, C101
14 1 C52 CAP., X5R, 3.3µF, 25V, 10%, 0603 TDK, C1608X5R1C335K
15 12 C58–C60, C62–C70 CAP., X7R, 0.1µF, 16V,10%, 0402 NIC, NMC0402X7R104K16TRPF
16 0 C79, C81, C92 CAP., 1206 OPT
17 3 C80, C83, C90 CAP., C0G, 15pF, 50V, 5%, 0603 TDK, C1608C0G1H150J
18 2 C97, C100 CAP., C0G, 0.22µF, 50V, 5%, 1812 TDK, C4532C0G1H224J
19 5 C102, C105–C108 CAP., NP0, 0.01µF, 25V, 5%, 0603 KEMET, C0603C103J3GAC7867
20 10 E1–E3, E5, E8–E13 TESTPOINT, TURRET, .064" pbf MILL-MAX, 2308-2-00-80-00-00-07-0
21 3 E4, E6, E7 TESTPOINT, TURRET, .094" pbf MILL-MAX, 2501-2-00-80-00-00-07-0
22 7 JP1, JP3, JP5–JP9 JMP, 1X3, .100", HD1X3-100 SAMTEC, TSW-103-07-L-S
23 1 JP2 JMP, 2X4, .100", HD2X4-100 SAMTEC, TSW-104-07-L-D
24 1 JP4 JMP, 2X5, .100", HD2X5-100 SAMTEC, TSW-105-07-L-D
25 7 J1–J7 CONN BNC FEM JACK PC MNT STRGHT,BNC5 AMPHENOL CONNEX, 112404
26 1 J8 CONN., HEADER 14POS 2MM VERT GOLD MOLEX, 87831-1420
27 15 R1, R4, R11, R12, R23, R27, R28, R31, R32, R35, R37, R111, R115, R123, R127
RES., CHIP, 1k, 1/10W, 1% 0603 NIC, NRC06F1001TRF
28 5 R2, R5, R6, R9, R10 RES., CHIP, 33, 1/10W, 5% 0603 PANASONIC, ERJ-3GEYJ330V
29 1 R3 RES., CHIP, 49.9, 1/4W, 1% 1206 NIC, NRC12F49R9TRF
30 0 R7, R13, R14, R16–R19, R91–R93, R97, R100, R106, R108, R110, R124, R129–R131, R137
RES., 0603 OPT
31 12 R8, R15, R24, R90, R94, R98, R109, R112–R114, R121, R128
RES., CHIP, 0, 1/10W, 0603 VISHAY, CRCW06030000Z0EA
32 1 R20 RES., CHIP, 787, 1/10W, 1% 0603 YAGEO, RC0603FR-07787RL
33 5 R21, R96, R99, R103, R105 RES., CHIP, 10, 1/10W, 5% 0603 PANASONIC, ERJ-3GEYJ100V
34 1 R22 RES., CHIP, 221, 1/10W, 1% 0603 YAGEO, RC0603FR-07221RL
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DEMO MANUAL DC2071A
ITEM QTY REFERENCE PART DESCRIPTION MANUFACTURER/PART NUMBER
35 1 R25 RES., CHIP, 2k, 1/10W, 1% 0603 NIC, NRC06F2001TRF
36 1 R26 RES., CHIP, 5.62k, 1/10W, 1% 0603 NIC, NRC06F5621TRF
37 1 R29 RES., CHIP, 1.07k, 1/10W, 1% 0603 NIC, NRC06F1071TRF
38 2 R30, R36 RES., CHIP, 11.5k, 1/10W, 1% 0603 YAGEO, RC0603FR-0711K5L
39 1 R33 RES., CHIP, 1.58k, 1/10W, 1% 0603 NIC, NRC06F1581TRF
40 1 R34 RES., CHIP, 3.16k, 1/10W, 1% 0603 NIC, NRC06F3161TRF
41 40 R38–R43, R45–R77, R83 RES., CHIP, 33, 1/16W, 5% 0402 VISHAY, CRCW040233R0JNED
42 4 R44, R78, R84, R86 RES., CHIP, 10k, 1/16W, 5% 0402 VISHAY, CRCW040210K0JNED
43 3 R80, R81, R82 RES., CHIP, 1k, 1/16W, 5% 0402 VISHAY, CRCW04021K00JNED
44 5 R85, R87, R88, R89, R120 RES., CHIP, 4.99k, 1/10W, 1% 0603 PANASONIC, ERJ-3EKF4991V
45 4 R95, R101, R104, R107 RES., CHIP, 24.9, 1/10W, 1% 0603 PANASONIC, ERJ-3EKF24R9V
46 1 R102 RES., CHIP, 499, 1/10W, 1% 0603 NIC, NRC06F4990TRF
47 2 R116, R125 RES., CHIP, 20k, 1/10W, 1% 0603 YAGEO, RC0603FR-0720KL
48 1 R117 RES., CHIP, 150, 1/10W, 5% 0603 NIC, NRC06J151TRF
49 2 R118, R119 RES., CHIP, 35.7, 1/10W, 1% 0603 PANASONIC, ERJ-3EKF35R7V
50 1 R122 RES., CHIP, 100, 1/10W, 5% 0603 VISHAY, CRCW0603100RJNEA
51 1 R126 RES., CHIP, 10k, 1/10W, 5% 0603 NIC, NRC06J103TRF
52 4 R132–R135 RES., CHIP, 20, 1/10W, 5% 0603 PANASONIC, ERJ-3GEYJ200V
53 0 R136 RES., 0402 OPT
54 4 U2, U3, U5, U19 IC., TINYLOGIC UHS INVERTER, SC70-5 FAIRCHILD, NC7SZ04P5X
55 1 U4 IC., SINGLE D FLIP FLOP, US8 ON SEMI., NL17SZ74USG
56 4 U6, U20, U21, U22 IC., SINGLE SPST BUS SWITCH, SC70-5 FAIRCHILD, NC7SZ66P5X
57 0 U7 IC., OP AMP/SAR ADC DRIVER, LT6237CMS8,MS8 OPT
58 1 U8 IC., 215MHz OP AMP/SAR ADC DRIVER, TSOT23-6 LINEAR TECH., LT6236CS6
59 1 U9 IC., 0.25ppm NOISE, LOW DRIFT PRECISION REF., MS8
LINEAR TECH.,LTC6655BHMS8-4.096
60 4 U10, U11, U12, U14 IC., 500mA LDO MICROPWR REGULATORS,SO8 LINEAR TECH., LT1763CS8
61 1 U13 IC., 500mA LDO MICROPWR REGULATORS,SO8 LINEAR TECH., LT1763CS8-1.8
62 2 U15, U16 IC., 200mA LDO MICROPWR REGULATORS,SOT23-5 LINEAR TECH., LT1964ES5-SD
63 1 U17 IC., I2C-BUS 8-BIT I/O, SSOP20 PHILIPS, PCF8574TS/3+118
64 1 U18 IC., MAX II FAMILY, TQFP100 ALTERA, EPM240GT100C5N
65 1 U23 IC., SERIAL EEPROM, TSSOP8 MICROCHIP, 24LC024-I/ST
66 1 U24 IC., MS8 LINEAR TECH., LT6237CMS8
67 1 U25 IC., SO8 LINEAR TECH., LT1469CS8
68 1 U26 IC., MS8E LINEAR TECH., LT5400ACMS8E-4
69 1 U27 IC., MS8 LINEAR TECH., LT6350CMS8
70 1 U28 IC., MS8 LINEAR TECH., LTC6362CMS8
71 4 MH1–MH4 STAND-OFF, NYLON, 0.25" KEYSTONE, 8831(SNAP ON)
72 8 SHUNTS–SEE ASSY DWG SHUNT, 0.1" CENTER SAMTEC, SNT-100-BK-G
pArts list
15dc2071afa
DEMO MANUAL DC2071A
ITEM QTY REFERENCE PART DESCRIPTION MANUFACTURER/PART NUMBER
DC2071A-A Required Circuit Components
1 1 DC2071A GENERAL BOM
2 1 U1 I.C., 18-Bit, 1.0Msps, QFN32UH-5X5 LINEAR TECH., LTC2373CUH-18
3 1 R79 RES., CHIP, 300, 1/10W, 5%, 0603 NIC, NRC06J301TRF
DC2071A-B Required Circuit Components
1 1 DC2071A GENERAL BOM
2 1 U1 I.C., 18-Bit, 0.5Msps, QFN32UH-5X5 LINEAR TECH., LTC2372CUH-18
3 1 R79 RES., CHIP, 300, 1/10W, 5%, 0603 NIC, NRC06J301TRF
DC2071A-D Required Circuit Components
1 1 DC2071A GENERAL BOM
2 1 U1 I.C., 16-Bit, 1.0Msps, QFN32UH-5X5 LINEAR TECH., LTC2373CUH-16
3 0 R79 RES., CHIP, 300, 1/10W, 5%, 0603 OPT
DC2071A-E Required Circuit Components
1 1 DC2071A GENERAL BOM
2 1 U1 I.C., 16-Bit, 0.5Msps, QFN32UH-5X5 LINEAR TECH., LTC2372CUH-16
3 0 R79 RES., CHIP, 300, 1/10W, 5%, 0603 OPT
pArts list
16dc2071afa
DEMO MANUAL DC2071A
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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SDO
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GND 23
RES
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GND 27
VDDLBYP28
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REFBUF12
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GND 14
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20
BU
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RD
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GND 17
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C35
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PT
C10
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PT
C33
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C30
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C30
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C16
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F1 32
C28
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PT
C20
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5 3
2
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DO
R2 33R2 33
R5 33R5 33
OE
A B
GND
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A B
GND
VCC
U6
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1
35
2
4R
231kR
231k
17dc2071afa
DEMO MANUAL DC2071A
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
-16V
/-18V
V-+1
6V/+
18V
VC
CIO +3
.3V
+2.5
V
VCC
IO
GN
D
+1.8
VV
CC
INT
V+ VDD
OPA
MP-
OPA
MP+
-16V
/-18V
+16V
/+18
V
VC
CIO
V-
+1.8
V
V+
VD
D
OPA
MP-
OP
AM
P+
SIZE
DA
TE:
IC N
O.
RE
V.
SHEE
TO
F
TITL
E:
APP
RO
VALS
PCB
DES
.
APP
EN
G.
TEC
HN
OLO
GY
Fax:
(408
)434
-050
7
Milp
itas,
CA
950
35P
hone
: (40
8)43
2-19
00
1630
McC
arth
y B
lvd.
LTC
Con
fiden
tial-F
or C
usto
mer
Use
Onl
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CU
STO
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NO
TIC
ELI
NEA
R T
ECH
NO
LOG
Y H
AS
MA
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A B
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RT
TO D
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CU
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CU
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ON
S;H
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, IT
REM
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S TH
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IFY
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LIC
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TAN
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RO
VALS
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.
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EN
G.
TEC
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GY
Fax:
(408
)434
-050
7
Milp
itas,
CA
950
35P
hone
: (40
8)43
2-19
00
1630
McC
arth
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S EN
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FO
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RO
VALS
PCB
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.
APP
EN
G.
TEC
HN
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GY
Fax:
(408
)434
-050
7
Milp
itas,
CA
950
35P
hone
: (40
8)43
2-19
00
1630
McC
arth
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lvd.
LTC
Con
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KIM
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H-1
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E4
E4
E3
E3
E12
E12
U15
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64E
S5-
SD
U15
LT19
64E
S5-
SD
AD
J4
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T5
GN
D1
IN2
SHD
N3
U12
LT17
63C
S8
U12
LT17
63C
S8
OU
T1
SEN
2
GND 3
BYP
4SH
DN
5
GND 6GND 7
IN8
R34
3.16
kR
343.
16k
C55
1uF
25V
C55
1uF
25V
C49
1uF
25V
C49
1uF
25V
E8
E8
E10
E10
C43
1uF
25V
C43
1uF
25V
C41
1uF
25V
C41
1uF
25V
E5
E5
C44
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25V
C44
1uF
25V
C51
10uF
25V
0805
C51
10uF
25V
0805
R29
1.07
kR
291.
07k
R37
1kR37
1k
U16
LT19
64E
S5-
SD
U16
LT19
64E
S5-
SD
AD
J4
OU
T5
GN
D1
IN2
SHD
N3
R31
1kR31
1k
R33
1.58
kR
331.
58k
R30
11.5
kR
3011
.5k
JP3
JP3
13 2
C56
0.01
uFC
560.
01uF
C48
1uF
25V
C48
1uF
25V
C45
0.01
uFC
450.
01uF
C46
10uF
6.3V
C46
10uF
6.3V
C40
10uF
0805
25V
C40
10uF
0805
25V
R27
1kR27
1k
U11
LT17
63C
S8
U11
LT17
63C
S8
OU
T1
SEN
2
GND 3
BYP
4SH
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5
GND 6GND 7
IN8
U10
LT17
63C
S8
U10
LT17
63C
S8
OU
T1
SEN
2
GND 3
BYP
4SH
DN
5
GND 6GND 7
IN8
C42
10uF
25V
0805
C42
10uF
25V
0805
C54
10uF
6.3V
C54
10uF
6.3V
E6
E6
E9
E9
U14
LT17
63C
S8
U14
LT17
63C
S8
OU
T1
SEN
2
GND 3
BYP
4SH
DN
5
GND 6GND 7
IN8
R26
5.62
kR
265.
62k
E7
E7
C39
0.01
uFC
390.
01uF
E11
E11
C47
10uF
0805
25V
C47
10uF
0805
25V
R32
1kR32
1k
C53
0.01
uFC
530.
01uF
R35
1kR35
1kR28
1kR28
1k
C57
10uF
25V
0805
C57
10uF
25V
0805
R36
11.5
kR
3611
.5k
C38
47uF
25V
1206
X5R
C38
47uF
25V
1206
X5R
C50
0.01
uFC
500.
01uF
C52
3.3u
F25
V
C52
3.3u
F25
V
U13
LT17
63C
S8-
1.8
U13
LT17
63C
S8-
1.8
OU
T1
SEN
2
GND 3
BYP
4SH
DN
5
GND 6GND 7
IN8
R25
2kR25
2k
Figu
re 1
3. D
C207
1A D
emo
Circ
uit S
chem
atic
, She
et 2
schemAtic DiAgrAm
18dc2071afa
DEMO MANUAL DC2071A
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
1. A
LL R
ESIS
TOR
S A
ND
CA
PAC
ITO
RS
ON
TH
IS P
AG
E A
RE
0402
.
NO
TES:
UN
LESS
OTH
ERW
ISE
SPEC
IFIE
D
2. R
79 IS
OPT
ION
AL
ON
ALL
16-
BIT
ASS
EMB
LY V
ERSI
ON
S.
16/1
8LA
DD
RES
S 4
0 H
EX W
RIT
E41
HEX
REA
D
AD
DR
ESS
A0
HEX
WR
ITE
A1
HEX
REA
D
DC
590
SEL
R0
R1
A0
A1
A2
A3
SOS
D0
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D1
SCL
SDA
D11
D12
D13
D14
D15
CN
VCLK
SYN
CSO
SSD
I_IN
SCK
_IN
CN
V_IN
A3
A2
A1
A0
R1
SEL
R0
D1
D0
D16
D17
D2
D3
D4
D5
D6
D7
D8
D9
D10
DEV
_OE
DEV
_CLR
N
WR
IN2
SD
I_IN
SC
K_I
N
CN
V_I
N
CN
VCLK
SYN
C
CN
VS
CK
SD
IS
DO
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IN
VCC
IO
VCC
IO
VCC
IO
VCC
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VCC
IO
VCC
IO
VCC
IO
VCC
IO
VC
CIO
VC
CIO +1
.8V
VC
CIO
SDI
SCK
CN
V
CSB
ID SDI
SCK
SDO
BU
SY
SDA
SCL
CLK
IN
WR
IN
SIZE
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IC N
O.
RE
V.
SHEE
TO
F
TITL
E:
APP
RO
VALS
PCB
DES
.
APP
EN
G.
TEC
HN
OLO
GY
Fax:
(408
)434
-050
7
Milp
itas,
CA
950
35P
hone
: (40
8)43
2-19
00
1630
McC
arth
y B
lvd.
LTC
Con
fiden
tial-F
or C
usto
mer
Use
Onl
y
CU
STO
MER
NO
TIC
ELI
NEA
R T
ECH
NO
LOG
Y H
AS
MA
DE
A B
EST
EFFO
RT
TO D
ESIG
N A
CIR
CU
IT T
HA
T M
EETS
CU
STO
MER
-SU
PPLI
ED S
PEC
IFIC
ATI
ON
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OW
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, IT
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S TH
E C
UST
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ER'S
RES
PON
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IFY
PRO
PER
AN
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BLE
OPE
RA
TIO
N IN
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CTU
AL
APP
LIC
ATI
ON
. C
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PON
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STIT
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ON
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D P
RIN
TED
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CU
IT B
OA
RD
LA
YOU
T M
AY
SIG
NIF
ICA
NTL
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FFEC
T C
IRC
UIT
PER
FOR
MA
NC
E O
R R
ELIA
BIL
ITY.
CO
NTA
CT
LIN
EAR
TEC
HN
OLO
GY
APP
LIC
ATI
ON
S EN
GIN
EER
ING
FO
R A
SSIS
TAN
CE.
THIS
CIR
CU
IT IS
PR
OPR
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RY
TO L
INEA
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NO
LOG
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ND
SC
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MA
TIC
SUPP
LIED
FO
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HN
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GY
PAR
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ALE
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DEM
O C
IRC
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207
1ATu
esda
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t 12,
201
43
KIM
T.
GU
Y H
.
8-C
HA
NN
EL, H
IGH
SPE
ED, S
ERIA
L, S
AR
, AD
C
LTC
237X
CU
H-1
8/16
FA
MIL
YB
4
SIZE
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TE:
IC N
O.
RE
V.
SHEE
TO
F
TITL
E:
APP
RO
VALS
PCB
DES
.
APP
EN
G.
TEC
HN
OLO
GY
Fax:
(408
)434
-050
7
Milp
itas,
CA
950
35P
hone
: (40
8)43
2-19
00
1630
McC
arth
y B
lvd.
LTC
Con
fiden
tial-F
or C
usto
mer
Use
Onl
y
CU
STO
MER
NO
TIC
ELI
NEA
R T
ECH
NO
LOG
Y H
AS
MA
DE
A B
EST
EFFO
RT
TO D
ESIG
N A
CIR
CU
IT T
HA
T M
EETS
CU
STO
MER
-SU
PPLI
ED S
PEC
IFIC
ATI
ON
S;H
OW
EVER
, IT
REM
AIN
S TH
E C
UST
OM
ER'S
RES
PON
SIB
ILIT
Y TO
VER
IFY
PRO
PER
AN
D R
ELIA
BLE
OPE
RA
TIO
N IN
TH
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CTU
AL
APP
LIC
ATI
ON
. C
OM
PON
ENT
SUB
STIT
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ON
AN
D P
RIN
TED
CIR
CU
IT B
OA
RD
LA
YOU
T M
AY
SIG
NIF
ICA
NTL
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FFEC
T C
IRC
UIT
PER
FOR
MA
NC
E O
R R
ELIA
BIL
ITY.
CO
NTA
CT
LIN
EAR
TEC
HN
OLO
GY
APP
LIC
ATI
ON
S EN
GIN
EER
ING
FO
R A
SSIS
TAN
CE.
THIS
CIR
CU
IT IS
PR
OPR
IETA
RY
TO L
INEA
R T
ECH
NO
LOG
Y A
ND
SC
HE
MA
TIC
SUPP
LIED
FO
R U
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EAR
TEC
HN
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GY
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TS.
SC
ALE
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DEM
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IRC
UIT
207
1ATu
esda
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t 12,
201
43
KIM
T.
GU
Y H
.
8-C
HA
NN
EL, H
IGH
SPE
ED, S
ERIA
L, S
AR
, AD
C
LTC
237X
CU
H-1
8/16
FA
MIL
YB
4
SIZE
DA
TE:
IC N
O.
RE
V.
SHEE
TO
F
TITL
E:
APP
RO
VALS
PCB
DES
.
APP
EN
G.
TEC
HN
OLO
GY
Fax:
(408
)434
-050
7
Milp
itas,
CA
950
35P
hone
: (40
8)43
2-19
00
1630
McC
arth
y B
lvd.
LTC
Con
fiden
tial-F
or C
usto
mer
Use
Onl
y
CU
STO
MER
NO
TIC
ELI
NEA
R T
ECH
NO
LOG
Y H
AS
MA
DE
A B
EST
EFFO
RT
TO D
ESIG
N A
CIR
CU
IT T
HA
T M
EETS
CU
STO
MER
-SU
PPLI
ED S
PEC
IFIC
ATI
ON
S;H
OW
EVER
, IT
REM
AIN
S TH
E C
UST
OM
ER'S
RES
PON
SIB
ILIT
Y TO
VER
IFY
PRO
PER
AN
D R
ELIA
BLE
OPE
RA
TIO
N IN
TH
E A
CTU
AL
APP
LIC
ATI
ON
. C
OM
PON
ENT
SUB
STIT
UTI
ON
AN
D P
RIN
TED
CIR
CU
IT B
OA
RD
LA
YOU
T M
AY
SIG
NIF
ICA
NTL
Y A
FFEC
T C
IRC
UIT
PER
FOR
MA
NC
E O
R R
ELIA
BIL
ITY.
CO
NTA
CT
LIN
EAR
TEC
HN
OLO
GY
APP
LIC
ATI
ON
S EN
GIN
EER
ING
FO
R A
SSIS
TAN
CE.
THIS
CIR
CU
IT IS
PR
OPR
IETA
RY
TO L
INEA
R T
ECH
NO
LOG
Y A
ND
SC
HE
MA
TIC
SUPP
LIED
FO
R U
SE W
ITH
LIN
EAR
TEC
HN
OLO
GY
PAR
TS.
SC
ALE
= N
ON
E
ww
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.com 3
DEM
O C
IRC
UIT
207
1ATu
esda
y, A
ugus
t 12,
201
43
KIM
T.
GU
Y H
.
8-C
HA
NN
EL, H
IGH
SPE
ED, S
ERIA
L, S
AR
, AD
C
LTC
237X
CU
H-1
8/16
FA
MIL
YB
4
R61
33R
6133
R63
33R
6333
R74
33R
7433
R84
10k
R84
10k
OE
A B
GND
VCC
U21
NC
7SZ6
6P5X
OE
A B
GND
VCC
U21
NC
7SZ6
6P5X
1
35
2
4
R64
33R
6433
EEPROMARRAY
U23
24LC
024-
I /S
T
EEPROMARRAY
U23
24LC
024-
I /S
T
SDA
5
VCC8
A0
1A
12
A2
3
GND 4
WP
7SC
L6
R88
4.99
k06
03
R88
4.99
k06
03
R44
10k
R44
10k
U18
D
EP
M24
0GT1
00C
5N
U18
D
EP
M24
0GT1
00C
5N
IO76
76IO
7777
IO78
78IO
8181
IO82
82IO
8383
IO84
84IO
8585
IO86
86IO
8787
IO88
88IO
8989
IO90
90IO
9191
IO92
92IO
9595
IO96
96IO
9797
IO98
98IO
9999
IO10
010
0
R87
4.99
k06
03
R87
4.99
k06
03
R59
33R
5933
R62
33R
6233
R69
33R
6933
U18
B
EP
M24
0GT1
00C
5N
U18
B
EP
M24
0GT1
00C
5N
IO26
26IO
2727
IO28
28IO
2929
IO30
30IO
3333
IO34
34IO
3535
IO36
36IO
3737
IO38
38IO
3939
IO40
40IO
4141
IO42
42IO
4747
IO48
48IO
4949
IO50
50
U18
F
EP
M24
0GT1
00C
5N
U18
F
EP
M24
0GT1
00C
5N
VCC
INT
13VC
CIN
T63
VCC
IO1
9VC
CIO
131
VCC
IO2
94
VCC
IO1
45VC
CIO
259
VCC
IO2
80
GN
D10
GN
D11
GN
D32
GN
D46
GN
D60
GN
D93
GN
D65
GN
D79
R65
33R
6533
JP5
PR
OG
WP
EE
PR
OM
JP5
PR
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DEMO MANUAL DC2071A
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Figu
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5. D
C207
1A D
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Circ
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chem
atic
, She
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schemAtic DiAgrAm
20dc2071afa
DEMO MANUAL DC2071A
Linear Technology Corporation1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com LINEAR TECHNOLOGY CORPORATION 2014
LT 1114 REV A • PRINTED IN USA
DEMONSTRATION BOARD IMPORTANT NOTICE
Linear Technology Corporation (LTC) provides the enclosed product(s) under the following AS IS conditions:
This demonstration board (DEMO BOARD) kit being sold or provided by Linear Technology is intended for use for ENGINEERING DEVELOPMENT OR EVALUATION PURPOSES ONLY and is not provided by LTC for commercial use. As such, the DEMO BOARD herein may not be complete in terms of required design-, marketing-, and/or manufacturing-related protective considerations, including but not limited to product safety measures typically found in finished commercial goods. As a prototype, this product does not fall within the scope of the European Union directive on electromagnetic compatibility and therefore may or may not meet the technical requirements of the directive, or other regulations.
If this evaluation kit does not meet the specifications recited in the DEMO BOARD manual the kit may be returned within 30 days from the date of delivery for a full refund. THE FOREGOING WARRANTY IS THE EXCLUSIVE WARRANTY MADE BY THE SELLER TO BUYER AND IS IN LIEU OF ALL OTHER WARRANTIES, EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. EXCEPT TO THE EXTENT OF THIS INDEMNITY, NEITHER PARTY SHALL BE LIABLE TO THE OTHER FOR ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES.
The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user releases LTC from all claims arising from the handling or use of the goods. Due to the open construction of the product, it is the user’s responsibility to take any and all appropriate precautions with regard to electrostatic discharge. Also be aware that the products herein may not be regulatory compliant or agency certified (FCC, UL, CE, etc.).
No License is granted under any patent right or other intellectual property whatsoever. LTC assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or any other intellectual property rights of any kind.
LTC currently services a variety of customers for products around the world, and therefore this transaction is not exclusive.
Please read the DEMO BOARD manual prior to handling the product. Persons handling this product must have electronics training and observe good laboratory practice standards. Common sense is encouraged.
This notice contains important safety information about temperatures and voltages. For further safety concerns, please contact a LTC applica-tion engineer.
Mailing Address:
Linear Technology
1630 McCarthy Blvd.
Milpitas, CA 95035
Copyright © 2004, Linear Technology Corporation
