Davide Zoni - Curriculum Vitae et Studiorum .Davide Zoni - Curriculum Vitae et Studiorum Name Davide

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  • Davide Zoni - Curriculum Vitae et Studiorum

    Name Davide ZoniCitizenship ItalianPhone (+39)- 02 2399 9623Email davide.zoni@polimi.itWebsite http://home.deib.polimi.it/zoniAddress Dipartimento di Elettronica Informazione e Bioingegneria (DEIB)

    Politecnico di Milano, 20133, Milan, ITALY

    Short Bio

    He received the Master in Computer Engineering in 2010 and the Ph.D. in Information Technology in2014, both from Politecnico di Milano where he holds a Post-Doc position at DEIB. During the PhD,he spent 7 months at Polytechnic University of Valencia working with Prof. Jose Flich on innovativesolutions for Networks-on-Chip (NoCs) and 4 months at University of Cyprus working with Prof. YanosSazeides and Prof. Chrys Nicopoulos on efficient power gating techniques for NoCs. He also visited ARM(Cambdridge, UK), as Post-Doc researcher, working with Dr. Stephan Diestelhorst on the next-generationcache coherence protocols for GPU-CPU multi-cores (Aug - Dec 2015).

    Short Summary

    Research Interests - His research interests include low power design methodologies for embeddedsystems with particular emphasis on the cache coherence and the on-chip interconnet. In 2015, he openeda new research area on RTL design of side-channel aware computer architectures working with Prof.Alessandro Barenghi and Prof. Gerardo Pelosi.EU Projects and International Collaborations - He participated in 3 European Projects (2PARMA(2010-2012), HARPA (2013-2016), MANGO (2015-2018), contributing from the beginning to define thestructure and the objectives of MANGO. He built a heterogeneous network of collaborations beyond theEU projects with universities (UPV and UCY) and companies (IMEC and ARM). He has a biweeklyappointment with Dr. Stephan Diestelhorst (leader of the System Modeling Group at ARM Research)with whom shared a research line on next-generation big.LITTLE architectures.Teaching and Students Supervision - He worked as teaching assistant for the Embedded Systems 1(M.Sc. Course) since 2012, and for the Architetture dei Calcolatori e Sistemi Operativi (B.Sc. Course)since 2017. Moreover, he is tutor for the Progetto Finale di Reti Logiche (B.Sc. Course) since 2017. Heco-advised 7 M.Sc. students and he is currently supervising 4 M.Sc. students.Pubblications and Awards - Since 2012, he published 19 conference papers and 6 journal articles. Healso received a best paper award in 2012, two HiPEAC Collaboration Grants in 2013 and 2014 and twoHiPEAC Industrial Grant in 2015 and 2017.

    Contents

    Position and Education 2

    Honors and Awards 4

    Teaching and Supervising 5

    Research Interests, Collaborations and Professional Activities 7

    Publications 11

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    mailto:davide.zoni@polimi.itwww.deib.polimi.it

  • Position and Education

    Record of Employment

    1st September 2015 now

    Post-Doctoral Research Assistant (according to the Italian law n.240/2010 - art.22) at the De-partment of Electronics, Computer Science and Bioengineering (DEIB) of the Politecnico diMilano working on Online Power Monitoring Methodologies and hardware-side countermeasuresto side-channel attacks.

    16th April 2014 31st August 2015

    Post-Doctoral Research Assistant (according to the Italian law n.240/2010 - art.22) at the Depart-ment of Electronics, Computer Science and Bioengineering (DEIB) of the Politecnico di Milanoworking on cache coherence and on-chip interconnect design for low-power embedded multi-cores.

    1st January 2011 21st March 2014

    PhD student at the Department of Electronics, Computer Science and Bioengineering (DEIB)of thePolitecnico di Milano.

    Education

    PhD in Information Technology at Politecnico di Milano.Title obtained on 21st March 2014 (European PhD Title with final evaluation: A+).Title: Exploring power reliability and performance aspects in on-chip networks for multi-coresAdvisor: Prof. William FornaciariReviewers: Prof. C. Brandolese, Prof. F. Catthoor, Prof. J. Flich, Prof. D. Soudris

    Minor Research Title: Server consolidation of multi-tier workloads including performance andreliability constraints (March 2011 - November 2011).Advisor: Prof. Paolo Cremonesi

    M.Sc. in Computer Science Engineering. December 2010. (110/110 cum laude)Thesis title: Gestione Dinamica delle Risorse per Sistemi Embedded Multi-Core e WorkloadEterogeneiAdvisor: Prof. William Fornaciari

    Visiting experiences

    Visiting researcher at ARM, Cambridge, UK (Aug 2015 - Dec 2015).

    Visiting researcher at University of Cyprus, Nicosia, Cyprus (Jan 2015 - Apr 2015).

    Visiting researcher at Polythecnic University of Valencia, Valencia, Spain (Jun 2014 - Jul 2014).

    Visiting researcher at Polythecnic University of Valencia, Valencia, Spain (Jan 2014 1 month).

    Visiting researcher at Polythecnic University of Valencia, Valencia, Spain (Jun 2013 - Sept 2013).

    External Courses

    Comprehensive Digital IC Implementation & Sign-Off (Using Cadence tools), STFC RutherfordAppleton Laboratory, UK (Jan 22-26 2018).

    Essential Verification with SystemVerilog and UVM, IMEC, Leuven BELGIUM (Jan 9-13 2017).

    Advanced Synthesis with Encounter RTL Compiler, EUROPRACTICE - Online Course (2017).

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  • Encounter RTL Compiler, EUROPRACTICE - Online Course (2017).

    SystemVerilog for Design and Verification, EUROPRACTICE - Online Course (2016).

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  • Honors and Awards

    AW6. HIPEAC INDUSTRIAL INTERNSHIP - (Aug 2017 - Dec 2017)Analytical Vulnerability Factor Correlation Study,Supervisor: Dr. Reiley Jeyapaul (ARM Ltd)

    AW5. HIPEAC INDUSTRIAL INTERNSHIP - (Aug 2015 - Dec 2015)Impact of weak memory models on application scalability and hardware design,Supervisor: Dr. Stephen Diestelhorst (ARM Ltd)

    AW4. HIPEAC COLLABORATION GRANT - (Jan 2015 - Apr 2015)Exploring NoC resynchronization schemes to support DVFS- and NTC-based optimizations,Supervisor: Prof. Yanos Sazeides (Univeristy of Cyprus)

    AW3. HIPEAC COLLABORATION GRANT - (JUN 2013 - Sept 2013)Dynamic router model and control to optimize power-performance tradeoff in NoCs,Supervisor: Prof. Jose Flich (Polytechnic Univeristy of Valencia)

    AW2. IEEE SoC 2012 Best Paper AwardD. Zoni, S. Corbetta and W. Fornaciari, Thermal-Performance Trade-off in Network-On-ChipArchitectures, in IEEE International Symposium on System-on-Chip, Tampere, Finland October11-12, 2012. [C7].

    AW1. IEEE SoCC 2012 Travel Grant AwardD. Zoni and W. Fornaciari, A Sensor-less NBTI mitigation methodology for NoC architectures,SoCC2012 25th IEEE International System-on-Chip Conference, Niagara Falls, New York, USA,September 1214, 2012. [C6]

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  • Teaching and Supervising

    Teaching

    2017-2018

    Progetto Finale di Reti Logiche (20 hours, Tutor) - Undergraduate Level - Master of Science inInformation Technology, BSc-IT, Politecnico di Milano, 1st semester. Lecturer: Prof. W. Fornaciari.

    Architetture dei Calcolatori e Sistemi Operativi (ACSO) (20 hours, Teaching Assistant) - Under-graduate Level - Master of Science in Information Technology, BSc-IT, Politecnico di Milano, 1stsemester. Lecturer: Prof. L. Breveglieri.

    Embedded Systems 1 (20 hours, Teaching Assistant) - Graduate level - Master of Science inInformation Technology, Politecnico di Milano, 1st semester. Lecturer: Prof. W. Fornaciari.

    2016-2017

    Energy Aware Design of Computing Systems and Applications (2 hours) - PhD Course in Informa-tion Technology, Department of Electronics, Information and Bioengineering (DEIB), Politecnicodi Milano.

    Embedded Systems 1 (20 hours, Teaching Assistant) - Graduate level - Master of Science inInformation Technology, Politecnico di Milano, 1st semester. Lecturer: Prof. W. Fornaciari.

    2015-2016

    Embedded Systems 1 (20 hours, Teaching Assistant) - Graduate level - Master of Science inInformation Technology, Politecnico di Milano, 1st semester. Lecturer: Prof. W. Fornaciari.

    2014-2015

    Embedded Systems 1 (20 hours, Teaching Assistant) - Graduate level - Master of Science inInformation Technology, Politecnico di Milano, 1st semester. Lecturer: Prof. W. Fornaciari.

    2013-2014

    Embedded Systems 1 (20 hours, Teaching Assistant) - Graduate level - Master of Science inInformation Technology, Politecnico di Milano, 1st semester. Lecturer: Prof. W. Fornaciari.

    2012-2013

    Embedded Systems 1 (20 hours, Teaching Assistant) - Graduate level - Master of Science inInformation Technology, Politecnico di Milano, 1st semester. Lecturer: Prof. W. Fornaciari.

    Graduate Students Supervision/Co-Advisor

    Luca Cremona, December 2017, A Methodology to Augment RTL Designs with Online PowerMonitoring Capability.Master of Science in Engineering of Computing Systems, Politecnico di Milano, Milano, Italy.Advisor: Prof. William Fornaciari. Co-advisor: Dr. Davide Zoni.

    Luca Colombo, April 2017, A novel Coherence Protocol for Selectively Power Gating the L2Banks in Multi-Cores to Optimize the Energy-Performance Trade-Off.Master of Science in Engineering of Computing Systems, Politecnico di Milano, Milano, Italy.Advisor: Prof. William Fornaciari. Co-advisor: Dr. Davide Zoni.

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  • Fabio Pancot, Decemberr 2016, Exploring the end-to-end compression to optimize the power-performance tradeoff in NoC-based multicores.Master of Science in Engineering of Computing Systems, Politecnico di Milano, Milano, Italy.Advisor: Prof. William Fornaciari. Co-advisor: Dr. Davide Zoni.

    Mauro Belluschi, September 2016, Exploring Future DNUCA Architectures by Bridging theApplication Behavior and the COherence protocol Support.Master of Science in Engineering of Computing Systems, Politecnico di Milano, Milano, Italy.Advisor: Prof. William Fornaciari. Co-advisor: Dr. Davide Zoni.

    Andrea Marchese, July 2016, A DVFS-Capable Heterogeneous Net