Dau Hoang KTVXL Chuong 1 Tong Quan

HC VIN CNG NGH BU CHNH VIN THNG BI GING MNK THUT VI X LGing vin: TS. Hong Xun Duin thoi/E-mail:[email protected] mn: Khoa hc my tnh - Khoa CNTT1CHNG 1 TNG QUAN V VI X L V H VI X L

BI GING MN K THUT VI X Lwww.ptit.edu.vnGING VIN: TS. HONG XUN DUB MN: KHOA HC MY TNH - KHOA CNTT1Trang *CHNG 1 TNG QUAN V VI X L V H VI X L

TI LIU THAM KHOPhm Hong Duy, Bi ging K thut vi x l, Hc vin CN BC-VT, 2010.H Khnh Lm, K thut vi x l, Nh xut bn Bu in, 2005.Vn Th Minh. K thut vi x l. NXB Gio dc 1999. Douglas V. Hall. Microprocessor and Interfacing- programming and hardware, 2nd edition. McGraw Hill. 1997.Hari BalaKrishnan & Samel Madden. The lecture notes on Computer Systems Engineering, Open Courses Ware. Massachusets Institute of Technology.


NH GI MN HCCc im thnh phn:Chuyn cn: 10%Kim tra: 10%Bi tp + tho lun: 20%Thi cui k: 60%


NI DUNGGii thiu v vi x lH vi x lCu trc h vi x lKin trc von-Neuman v HarvardCc c im cu trc ca vi x lCng sut vi x lCc c tnh nng caoLch s pht trin vi x l


Gii thiu v vi x lVi x l (microprocessor):L mt vi mch kiu VLSI (Very Large Scale Integrated Circuit)C th lp trnh cChc nng chnh ca VXL:Tnh tonVn chuyn d liuVXL thc hin cc chc nng thng qua thc hin cc lnh ca chng trnh:Thc hin cc php ton: s hc, logic, dch, quay,Kt ni v trao i d liu vi cc thit b bn ngoi thng qua cc cng vo ra.


Gii thiu v vi x lVi x l Intel 8086 (1978)Vi x l Intel Core 2 Duo (2006)


Gii thiu v vi x lPhn loi VXL da trn chc nng:Vi x l a chc nng (general-purpose microprocessors): Cha tt c cc thnh phn phc v tnh ton v iu khinKhng bao gm b nh v cc cng vo ra.Vi iu khin (micro-controllers): Cha tt c cc thnh phn phc v tnh ton v iu khinC bao gm b nh v cc cng vo raTt c cc thnh phn ca vi iu khin c tch hp trn mt chp n.


Gii thiu v vi x lThc hin lnh ca vi x l:Vi x l thc hin cc tc v da trn cc ch dn (instructions), hay cn gi l cc lnh.Mt tp hp cc lnh c sp xp theo mt trt t no --> chng trnhChng trnh thng c lu trn a. Chng trnh c np vo b nh khi n c kch hot. Vi x l s c v thc hin tng lnh ca chng trnh trong b nh.Qu trnh thc hin mt lnh:c lnhGii m lnhThc hin lnhLu kt qu ca lnh (nu c)


Gii thiu v vi x lBus:L tp cc ng dy dn vi x l trao i d liu v thng tin iu khin vi cc b phn khc. Cc loi bus:Bus trong: lin kt cc b phn trong vi x l Bus ngoi: lin kt vi x l vi cc b phn khc ca my tnh Nhp ng h (clock) Xung nhp ng h c to bi mt ng h chun c s dng : To nhp hot ng cho vi x l ng b ho hot ng ca vi x l vi cc b phn khc


H vi x l: gii thiuH VXL l mt h thng c kh nng tnh ton, iu khin v x l thng tin;H VXL cng c kh nng giao tip vi th gii bn ngoi:Tip nhn thng tin t bn ngoiKt xut thng tin ra bn ngoi.


H vi x l: gii thiuH VXL thng bao gm:CPU (Central Processing Unit): B x l trung tm c nhim v tnh ton v iu khinALU (Arithmetic and Logic Unit): khi tnh tonCU (Control Unit): khi iu khinB nh (Memory): lu tr d liu (data) v lnh (instruction) cho CPU x lB nh ROM: lu lnh v d liu ca h thngB nh RAM: lu lnh v d liu ca h thng v ca ngi dngCc thit b vo (Inputs):Tip nhn d liu v thng tin iu khin, chuyn cho CPU x lCc thit b ra (Oututs):Kt xut thng tin ra (mn hnh, giy, ...)Lu tr thng tin lu di (a t, a quang, ....)


H vi x l: Kin trc von-NeumannKin trc my tnh von-Neumann nguyn thu Kin trc my tnh von-Neumann hin i


H vi x l: Kin trc von-NeumannKin trc my tnh von-Neumann: Kin trc von-Neumann c nh ton hc John von-Neumann a ra vo nm 1945 trong mt bo co v my tnh EDVAC. Cc c im ca kin trc my tnh von-Neumann: Mt b nh duy nht c dng lu tr d liu (data) v lnh (instructions)D liu v lnh c lu tr trong cc phn ring ca b nhB nh c nh a ch theo vng, khng ph thuc vo loi d liu m n lu tr.Qu trnh thc hin cc lnh din ra tun t.


H vi x l: Kin trc von-NeumannChu trnh thc hin lnh (c - gii m - thc hin):c lnh t b nh a vo thanh ghi lnh IR.Thay i ni dung b m chng trnh (PC) n tr sang lnh tip theoXc nh kiu lnh va cNu lnh c yu cu d liu, xc nh v tr ca d liu c d liu (nu c) vo cc thanh ghi ca vi x l Thc hin lnhLu gi kt qu (nu c) Bus h thng gm:Bus a ch (Address Bus)Bus d liu (Data Bus)Bus iu khin (Control Bus)


H vi x l: Kin trc Harvard


H vi x l: Kin trc HarvardB nh c chia thnh 2 phn ring:B nh lu chng trnhB nh lu d liuCPU s dng 2 h thng bus giao tip vi b nh:H thng bus giao tip vi b nh lu chng trnhH thng bus giao tip vi b nh lu d liuNhn xt:Kin trc Harvard phc tp hn kin trc von-NeumannKin trc Harvard nhanh hn kin trc von-Neumann do CPU c th giao tip ng thi vi c b nh chng trnh v d liu, thch hp vi cc c ch ng lnh v x l song song.


T chc ca my tnh hin iS khi my tnh vi b chipset cu Bc v cu Nam


S khi my tnh vi CPU c tch hp memory controller v graphic chip


Cc c im cu trc ca vi x lCng sut vi x l: di t d liu (data word length):Ph thuc vo th h vi x l: 4, 8, 16, 32 v 64 bits rng ca cc thanh ghi, bus trong, bus ngoi thng bng di ca t d liu di t x l ln -> tng kh nng biu din d liu, tng tc tnh ton.Kh nng nh a ch (addressing capacity):Quyt nh dung lng b nh m vi x l c th nh a chKh nng nh a ch ca vi x l theo s bit a ch V d: H thng c 8 bt a ch c th qun l c 28 = 256 nhH thng c 16 bt a ch c th qun l c 216 = 65536 = 64K nhH thng c 32 bt a ch c th qun l c 232 = 4GB nh


Cc c im cu trc ca vi x lCng sut vi x l:Tc x l lnh (instruction execution speed):Thng c o bng tc thc hin : Triu lnh du phy ng (MFLOPS Millions of Floating Point Operations Per Second, hoc Triu lnh/giy (MIPS - Millions of Instructions Per Second).MIPS c tnh theo kin trc von-Neumann:MIPS = (f x N) / (M + T)Trong :f- tn s lm vic ca b vi x l N- s lng cc b ALU c lp trong vi x l M- s lng cc vi lnh (microinstructions) trung bnh ca mt lnh ca vi x l (thng thng 4-7 vi lnh/lnh)T- h s thi gian truy cp b nh


Cc c im cu trc ca vi x lCc c tnh nng cao:X l song song (parallel processing):Kt hp nhiu vi x l trong mt my tnhTng tc x l d liu, c bit vi cc h thng my chng x l (co-processing):S dng b ng x l tng tc : chuyn tnh ton s du phy ng (n 386). Cc b ng x l kt ni vi vi x l thng qua bus h thngCc module x l du phy ng c tch hp vo vi x l trong cc vi x l hin iK thut lu khay (cache)B nh c t chc theo m hnh phn cpTng c tc , gim gi thnh


Cc c im cu trc ca vi x lCc c tnh nng cao:K thut ng ng (pipelining): l kh nng x l ng thi nhiu lnh.Mt lnh c chia lm nhiu bcCc bc ca nhiu lnh c thc hin xen k nhau ti cc b phn khc nhau ca vi x l Siu ng ng: super-pipelining: ng ng di vi nhiu giai onBus rng: tng tc x l nh tng di t d liu x lK thut ng ng


Lch s pht trin VXLNm 1970, Intel cho ra i chip vi x l u tin 4004: di t x l: 4 bitBus d liu 4 bit, bus a ch 12 bit (dng chung vi bus d liu)Kch thc 24mm2, 16 chn, cha 2250 transitors


Lch s pht trin VXLNm 1972, Intel cho ra i chip vi x l 8008: di t x l: 8 bitBus d liu 8 bit, bus a ch 14 bit (dng chung vi bus d liu)Tn s lm vic 300KHz, 18 chn, cha 3300 transitors


Lch s pht trin VXLNm 1976, Zilog cho ra i chip vi x l Z80: di t x l: 8 bitBus d liu 8 bit, bus a ch 16 bit (dng chung vi bus d liu)Tn s lm vic 2.5, 4, 6, 8 v 10MHz; 40 chn


Lch s pht trin VXLNm 1978, Intel cho ra i chip vi x l 8086: di t x l: 16 bitBus d liu 16 bit, bus a ch 20 bit (dng chung vi bus d liu)Tn s lm vic 5-10MHz, 40 chn


Lch s pht trin VXLNm 1982, Motorola cho ra i chip vi x l MC68020: di t x l: 32 bitBus d liu 32 bit, bus a ch 32 bitTn s lm vic 16.67-33.33 MHz


Lch s pht trin VXLNm 1982, Intel cho ra i chip vi x l 80286: di t x l: 16 bitBus d liu 16 bit, bus a ch 24 bit (dng chung vi bus d liu)B nh max: 16MBTn s lm vic 6-25MHz


Lch s pht trin VXLNm 1985, Intel cho ra i chip vi x l 80386: di t x l: 32 bitBus d liu 32 bit, bus a ch 32 bit (dng chung vi bus d liu)B nh max: 4GBTn s lm vic 16-33MHz


Lch s pht trin VXLNm 1989, Intel cho ra i chip vi x l 80486: di t x l: 32 bitBus d liu 32 bit, bus a ch 32 bit (dng chung vi bus d liu)B nh max: 4GBTn s lm vic 25-100MHzTch hp cache L1 8KTch hp ng x l s thc 80487.


Lch s pht trin VXLNm 1993, Intel cho ra i chip vi x l Pentium: di t x l: 32 bitBus d liu 32 bit, bus a ch 32 bit (dng chung vi bus d liu)B nh max: 4GBTn s lm vic 60, 75, 90, 120MHzTch hp cache I-L1 8K v D-L1 8KH tr tp lnh x l multimedia MMX.


Lch s pht trin VXLNm 1997, Intel cho ra i chip vi x l Pentium II:Tn s lm vic 233-450MHzTch hp cache I-L1 16-32K v D-L1 16-32KTch hp cache L2 256-512KS dng khe cm kiu slot I.


Lch s pht trin VXLNm 1999, Intel cho ra i chip vi x l Pentium III:Tn s lm vic 450MHz-1.4GHzTch hp cache L1, L2Gii thiu tp lnh SSE (Streaming SIMD Extensions)


Lch s pht trin VXLNm 2000, Intel cho ra i chip vi x l Pentium IV:Tn s lm vic 1.5-3.8GHz, cng ngh 180-130nmH tr cc tp lnh tin tin SSE, SSE2, SSE3Mt s phin bn mi nht h tr cng ngh siu phn lung v o ho.Pentium IV socket 478


Lch s pht trin VXLPentium IV socket 775


Lch s pht trin VXLNm 2003, Intel cho ra i chip vi x l Pentium M:Cng ngh 130-90nmTn s lm vic 900MHz-2.26GHzThit k dnh ring cho my xch tayCache L1 32K, L2 n 2MBH tr cc tp lnh tin tin MMX, SSE, SSE2Cng ngh qun l ngun tin tin Intel Speedstep


Lch s pht trin VXLNm 2006, Intel cho ra i cc chip vi x l da trn vi kin trc Core v Core 2:Cng ngh 65nmH tr cc tp lnh tin tin MMX, SSE, SSE2, SSE3, SSE4Cache ln v thng minhNhiu nhn/liCng ngh tit kim in nng Dynamic Power Coordination v Enhanced Intel Deeper Sleep


Lch s pht trin VXLNm 2008, Intel cho ra i vi x l Atom:Cng ngh 45nmVi kin trc Atom ti u ho cho cc thit b c kch thc nh v tiu th t nng lngEnhanced SpeedStep TechnologyDeep Power Down Technology with Dynamic Cache SizingIntel Virutalization Technology


Lch s pht trin VXLThng 11.2008, Intel cho ra i vi x l da trn vi kin trc Intel Core i7:Cng ngh 45nmKin trc 64 btTch hp 4 nhn, h tr 2 lung o/nhn8MB Smart Cache L2Tn s lm vic: 1.6-3.47GHz


Lch s pht trin VXLThng 1.2011, Intel cho ra i vi x l Core i5, i7 da trn vi kin trc Sandy Bridge:Cng ngh 32nmKin trc 64 btTch hp 2/4 nhn, h tr 2 lung o/nhn4-8MB Smart Cache L2Tn s lm vic: 1.4-2.7GHz


Lch s pht trin VXLThng 4.2012, Intel cho ra i vi x l Core i5, i7 da trn vi kin trc Ivy Bridge:Cng ngh 22nmVi kin trc tng t Sandy BridgeKin trc 64 btTch hp 2/4 nhn, h tr 2 lung o/nhnNhanh hn Sandy Bridge n 20%, tiu th t in hn, ho mnh hn.


VXL k tip trong tng lai gn Li Haswell

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Dau Hoang KTVXL Chuong 1 Tong Quan